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authorJon Mason <mason@myri.com>2011-10-14 15:56:14 -0400
committerJesse Barnes <jbarnes@virtuousgeek.org>2011-10-27 15:45:43 -0400
commit62f392ea5b5f87b641e16e61a4cedda21ef7341f (patch)
tree3392e1c0b10f851df98b18797c0637608887d624 /drivers/pci
parentd387a8d66670371e6be3b6d6bde2e38b8cade076 (diff)
PCI: enable MPS "performance" setting to properly handle bridge MPS
Rework the "performance" MPS option to configure the device MPS with the smaller of the device MPSS or the bridge MPS (which is assumed to be properly configured at this point to the largest allowable MPS based on its parent bus). Also, rework the MRRS setting to report an inability to set the MRRS to a valid setting. Signed-off-by: Jon Mason <mason@myri.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/probe.c55
1 files changed, 24 insertions, 31 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 6ab6bd3df4b2..482942439852 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1363,31 +1363,25 @@ static int pcie_find_smpss(struct pci_dev *dev, void *data)
1363 1363
1364static void pcie_write_mps(struct pci_dev *dev, int mps) 1364static void pcie_write_mps(struct pci_dev *dev, int mps)
1365{ 1365{
1366 int rc, dev_mpss; 1366 int rc;
1367
1368 dev_mpss = 128 << dev->pcie_mpss;
1369 1367
1370 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 1368 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1371 if (dev->bus->self) { 1369 mps = 128 << dev->pcie_mpss;
1372 dev_dbg(&dev->bus->dev, "Bus MPSS %d\n",
1373 128 << dev->bus->self->pcie_mpss);
1374 1370
1375 /* For "MPS Force Max", the assumption is made that 1371 if (dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self)
1372 /* For "Performance", the assumption is made that
1376 * downstream communication will never be larger than 1373 * downstream communication will never be larger than
1377 * the MRRS. So, the MPS only needs to be configured 1374 * the MRRS. So, the MPS only needs to be configured
1378 * for the upstream communication. This being the case, 1375 * for the upstream communication. This being the case,
1379 * walk from the top down and set the MPS of the child 1376 * walk from the top down and set the MPS of the child
1380 * to that of the parent bus. 1377 * to that of the parent bus.
1378 *
1379 * Configure the device MPS with the smaller of the
1380 * device MPSS or the bridge MPS (which is assumed to be
1381 * properly configured at this point to the largest
1382 * allowable MPS based on its parent bus).
1381 */ 1383 */
1382 mps = 128 << dev->bus->self->pcie_mpss; 1384 mps = min(mps, pcie_get_mps(dev->bus->self));
1383 if (mps > dev_mpss)
1384 dev_warn(&dev->dev, "MPS configured higher than"
1385 " maximum supported by the device. If"
1386 " a bus issue occurs, try running with"
1387 " pci=pcie_bus_safe.\n");
1388 }
1389
1390 dev->pcie_mpss = ffs(mps) - 8;
1391 } 1385 }
1392 1386
1393 rc = pcie_set_mps(dev, mps); 1387 rc = pcie_set_mps(dev, mps);
@@ -1395,25 +1389,22 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
1395 dev_err(&dev->dev, "Failed attempting to set the MPS\n"); 1389 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1396} 1390}
1397 1391
1398static void pcie_write_mrrs(struct pci_dev *dev, int mps) 1392static void pcie_write_mrrs(struct pci_dev *dev)
1399{ 1393{
1400 int rc, mrrs, dev_mpss; 1394 int rc, mrrs;
1401 1395
1402 /* In the "safe" case, do not configure the MRRS. There appear to be 1396 /* In the "safe" case, do not configure the MRRS. There appear to be
1403 * issues with setting MRRS to 0 on a number of devices. 1397 * issues with setting MRRS to 0 on a number of devices.
1404 */ 1398 */
1405
1406 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 1399 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1407 return; 1400 return;
1408 1401
1409 dev_mpss = 128 << dev->pcie_mpss;
1410
1411 /* For Max performance, the MRRS must be set to the largest supported 1402 /* For Max performance, the MRRS must be set to the largest supported
1412 * value. However, it cannot be configured larger than the MPS the 1403 * value. However, it cannot be configured larger than the MPS the
1413 * device or the bus can support. This assumes that the largest MRRS 1404 * device or the bus can support. This should already be properly
1414 * available on the device cannot be smaller than the device MPSS. 1405 * configured by a prior call to pcie_write_mps.
1415 */ 1406 */
1416 mrrs = min(mps, dev_mpss); 1407 mrrs = pcie_get_mps(dev);
1417 1408
1418 /* MRRS is a R/W register. Invalid values can be written, but a 1409 /* MRRS is a R/W register. Invalid values can be written, but a
1419 * subsequent read will verify if the value is acceptable or not. 1410 * subsequent read will verify if the value is acceptable or not.
@@ -1421,16 +1412,18 @@ static void pcie_write_mrrs(struct pci_dev *dev, int mps)
1421 * shrink the value until it is acceptable to the HW. 1412 * shrink the value until it is acceptable to the HW.
1422 */ 1413 */
1423 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 1414 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1424 dev_warn(&dev->dev, "Attempting to modify the PCI-E MRRS value"
1425 " to %d. If any issues are encountered, please try "
1426 "running with pci=pcie_bus_safe\n", mrrs);
1427 rc = pcie_set_readrq(dev, mrrs); 1415 rc = pcie_set_readrq(dev, mrrs);
1428 if (rc) 1416 if (!rc)
1429 dev_err(&dev->dev, 1417 break;
1430 "Failed attempting to set the MRRS\n");
1431 1418
1419 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1432 mrrs /= 2; 1420 mrrs /= 2;
1433 } 1421 }
1422
1423 if (mrrs < 128)
1424 dev_err(&dev->dev, "MRRS was unable to be configured with a "
1425 "safe value. If problems are experienced, try running "
1426 "with pci=pcie_bus_safe.\n");
1434} 1427}
1435 1428
1436static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 1429static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
@@ -1444,7 +1437,7 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1444 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev)); 1437 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));
1445 1438
1446 pcie_write_mps(dev, mps); 1439 pcie_write_mps(dev, mps);
1447 pcie_write_mrrs(dev, mps); 1440 pcie_write_mrrs(dev);
1448 1441
1449 dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", 1442 dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
1450 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev)); 1443 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));