diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-16 20:25:46 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-16 20:25:46 -0400 |
commit | dc7c65db2845a8d17432d89252c4227a9a7cb15f (patch) | |
tree | 79030b0aaaafc04bc4303c21495134e744afc058 /drivers/pci/setup-bus.c | |
parent | 8a0ca91e1db5de5eb5b18cfa919d52ff8be375af (diff) | |
parent | 58b6e5538460be358fdf1286d9a2fbcfcc2cfaba (diff) |
Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (72 commits)
Revert "x86/PCI: ACPI based PCI gap calculation"
PCI: remove unnecessary volatile in PCIe hotplug struct controller
x86/PCI: ACPI based PCI gap calculation
PCI: include linux/pm_wakeup.h for device_set_wakeup_capable
PCI PM: Fix pci_prepare_to_sleep
x86/PCI: Fix PCI config space for domains > 0
Fix acpi_pm_device_sleep_wake() by providing a stub for CONFIG_PM_SLEEP=n
PCI: Simplify PCI device PM code
PCI PM: Introduce pci_prepare_to_sleep and pci_back_from_sleep
PCI ACPI: Rework PCI handling of wake-up
ACPI: Introduce new device wakeup flag 'prepared'
ACPI: Introduce acpi_device_sleep_wake function
PCI: rework pci_set_power_state function to call platform first
PCI: Introduce platform_pci_power_manageable function
ACPI: Introduce acpi_bus_power_manageable function
PCI: make pci_name use dev_name
PCI: handle pci_name() being const
PCI: add stub for pci_set_consistent_dma_mask()
PCI: remove unused arch pcibios_update_resource() functions
PCI: fix pci_setup_device()'s sprinting into a const buffer
...
Fixed up conflicts in various files (arch/x86/kernel/setup_64.c,
arch/x86/pci/irq.c, arch/x86/pci/pci.h, drivers/acpi/sleep/main.c,
drivers/pci/pci.c, drivers/pci/pci.h, include/acpi/acpi_bus.h) from x86
and ACPI updates manually.
Diffstat (limited to 'drivers/pci/setup-bus.c')
-rw-r--r-- | drivers/pci/setup-bus.c | 43 |
1 files changed, 18 insertions, 25 deletions
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 8ddb918f5f57..827c0a520e2b 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c | |||
@@ -27,13 +27,6 @@ | |||
27 | #include <linux/slab.h> | 27 | #include <linux/slab.h> |
28 | 28 | ||
29 | 29 | ||
30 | #define DEBUG_CONFIG 1 | ||
31 | #if DEBUG_CONFIG | ||
32 | #define DBG(x...) printk(x) | ||
33 | #else | ||
34 | #define DBG(x...) | ||
35 | #endif | ||
36 | |||
37 | static void pbus_assign_resources_sorted(struct pci_bus *bus) | 30 | static void pbus_assign_resources_sorted(struct pci_bus *bus) |
38 | { | 31 | { |
39 | struct pci_dev *dev; | 32 | struct pci_dev *dev; |
@@ -81,8 +74,8 @@ void pci_setup_cardbus(struct pci_bus *bus) | |||
81 | struct pci_dev *bridge = bus->self; | 74 | struct pci_dev *bridge = bus->self; |
82 | struct pci_bus_region region; | 75 | struct pci_bus_region region; |
83 | 76 | ||
84 | printk("PCI: Bus %d, cardbus bridge: %s\n", | 77 | dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n", |
85 | bus->number, pci_name(bridge)); | 78 | pci_domain_nr(bus), bus->number); |
86 | 79 | ||
87 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); | 80 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); |
88 | if (bus->resource[0]->flags & IORESOURCE_IO) { | 81 | if (bus->resource[0]->flags & IORESOURCE_IO) { |
@@ -90,7 +83,7 @@ void pci_setup_cardbus(struct pci_bus *bus) | |||
90 | * The IO resource is allocated a range twice as large as it | 83 | * The IO resource is allocated a range twice as large as it |
91 | * would normally need. This allows us to set both IO regs. | 84 | * would normally need. This allows us to set both IO regs. |
92 | */ | 85 | */ |
93 | printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n", | 86 | dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n", |
94 | (unsigned long)region.start, | 87 | (unsigned long)region.start, |
95 | (unsigned long)region.end); | 88 | (unsigned long)region.end); |
96 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, | 89 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
@@ -101,7 +94,7 @@ void pci_setup_cardbus(struct pci_bus *bus) | |||
101 | 94 | ||
102 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); | 95 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); |
103 | if (bus->resource[1]->flags & IORESOURCE_IO) { | 96 | if (bus->resource[1]->flags & IORESOURCE_IO) { |
104 | printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n", | 97 | dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n", |
105 | (unsigned long)region.start, | 98 | (unsigned long)region.start, |
106 | (unsigned long)region.end); | 99 | (unsigned long)region.end); |
107 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, | 100 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
@@ -112,7 +105,7 @@ void pci_setup_cardbus(struct pci_bus *bus) | |||
112 | 105 | ||
113 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); | 106 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); |
114 | if (bus->resource[2]->flags & IORESOURCE_MEM) { | 107 | if (bus->resource[2]->flags & IORESOURCE_MEM) { |
115 | printk(KERN_INFO " PREFETCH window: 0x%08lx-0x%08lx\n", | 108 | dev_info(&bridge->dev, " PREFETCH window: %#08lx-%#08lx\n", |
116 | (unsigned long)region.start, | 109 | (unsigned long)region.start, |
117 | (unsigned long)region.end); | 110 | (unsigned long)region.end); |
118 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, | 111 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
@@ -123,7 +116,7 @@ void pci_setup_cardbus(struct pci_bus *bus) | |||
123 | 116 | ||
124 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]); | 117 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]); |
125 | if (bus->resource[3]->flags & IORESOURCE_MEM) { | 118 | if (bus->resource[3]->flags & IORESOURCE_MEM) { |
126 | printk(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n", | 119 | dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n", |
127 | (unsigned long)region.start, | 120 | (unsigned long)region.start, |
128 | (unsigned long)region.end); | 121 | (unsigned long)region.end); |
129 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, | 122 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
@@ -151,7 +144,8 @@ static void pci_setup_bridge(struct pci_bus *bus) | |||
151 | struct pci_bus_region region; | 144 | struct pci_bus_region region; |
152 | u32 l, bu, lu, io_upper16; | 145 | u32 l, bu, lu, io_upper16; |
153 | 146 | ||
154 | DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge)); | 147 | dev_info(&bridge->dev, "PCI bridge, secondary bus %04x:%02x\n", |
148 | pci_domain_nr(bus), bus->number); | ||
155 | 149 | ||
156 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | 150 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ |
157 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); | 151 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); |
@@ -162,7 +156,7 @@ static void pci_setup_bridge(struct pci_bus *bus) | |||
162 | l |= region.end & 0xf000; | 156 | l |= region.end & 0xf000; |
163 | /* Set up upper 16 bits of I/O base/limit. */ | 157 | /* Set up upper 16 bits of I/O base/limit. */ |
164 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | 158 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); |
165 | DBG(KERN_INFO " IO window: %04lx-%04lx\n", | 159 | dev_info(&bridge->dev, " IO window: %#04lx-%#04lx\n", |
166 | (unsigned long)region.start, | 160 | (unsigned long)region.start, |
167 | (unsigned long)region.end); | 161 | (unsigned long)region.end); |
168 | } | 162 | } |
@@ -170,7 +164,7 @@ static void pci_setup_bridge(struct pci_bus *bus) | |||
170 | /* Clear upper 16 bits of I/O base/limit. */ | 164 | /* Clear upper 16 bits of I/O base/limit. */ |
171 | io_upper16 = 0; | 165 | io_upper16 = 0; |
172 | l = 0x00f0; | 166 | l = 0x00f0; |
173 | DBG(KERN_INFO " IO window: disabled.\n"); | 167 | dev_info(&bridge->dev, " IO window: disabled\n"); |
174 | } | 168 | } |
175 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | 169 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ |
176 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | 170 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); |
@@ -185,13 +179,13 @@ static void pci_setup_bridge(struct pci_bus *bus) | |||
185 | if (bus->resource[1]->flags & IORESOURCE_MEM) { | 179 | if (bus->resource[1]->flags & IORESOURCE_MEM) { |
186 | l = (region.start >> 16) & 0xfff0; | 180 | l = (region.start >> 16) & 0xfff0; |
187 | l |= region.end & 0xfff00000; | 181 | l |= region.end & 0xfff00000; |
188 | DBG(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n", | 182 | dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n", |
189 | (unsigned long)region.start, | 183 | (unsigned long)region.start, |
190 | (unsigned long)region.end); | 184 | (unsigned long)region.end); |
191 | } | 185 | } |
192 | else { | 186 | else { |
193 | l = 0x0000fff0; | 187 | l = 0x0000fff0; |
194 | DBG(KERN_INFO " MEM window: disabled.\n"); | 188 | dev_info(&bridge->dev, " MEM window: disabled\n"); |
195 | } | 189 | } |
196 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | 190 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); |
197 | 191 | ||
@@ -208,13 +202,13 @@ static void pci_setup_bridge(struct pci_bus *bus) | |||
208 | l |= region.end & 0xfff00000; | 202 | l |= region.end & 0xfff00000; |
209 | bu = upper_32_bits(region.start); | 203 | bu = upper_32_bits(region.start); |
210 | lu = upper_32_bits(region.end); | 204 | lu = upper_32_bits(region.end); |
211 | DBG(KERN_INFO " PREFETCH window: 0x%016llx-0x%016llx\n", | 205 | dev_info(&bridge->dev, " PREFETCH window: %#016llx-%#016llx\n", |
212 | (unsigned long long)region.start, | 206 | (unsigned long long)region.start, |
213 | (unsigned long long)region.end); | 207 | (unsigned long long)region.end); |
214 | } | 208 | } |
215 | else { | 209 | else { |
216 | l = 0x0000fff0; | 210 | l = 0x0000fff0; |
217 | DBG(KERN_INFO " PREFETCH window: disabled.\n"); | 211 | dev_info(&bridge->dev, " PREFETCH window: disabled\n"); |
218 | } | 212 | } |
219 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | 213 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); |
220 | 214 | ||
@@ -361,9 +355,8 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long | |||
361 | align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start; | 355 | align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start; |
362 | order = __ffs(align) - 20; | 356 | order = __ffs(align) - 20; |
363 | if (order > 11) { | 357 | if (order > 11) { |
364 | printk(KERN_WARNING "PCI: region %s/%d " | 358 | dev_warn(&dev->dev, "BAR %d too large: " |
365 | "too large: 0x%016llx-0x%016llx\n", | 359 | "%#016llx-%#016llx\n", i, |
366 | pci_name(dev), i, | ||
367 | (unsigned long long)r->start, | 360 | (unsigned long long)r->start, |
368 | (unsigned long long)r->end); | 361 | (unsigned long long)r->end); |
369 | r->flags = 0; | 362 | r->flags = 0; |
@@ -529,8 +522,8 @@ void __ref pci_bus_assign_resources(struct pci_bus *bus) | |||
529 | break; | 522 | break; |
530 | 523 | ||
531 | default: | 524 | default: |
532 | printk(KERN_INFO "PCI: not setting up bridge %s " | 525 | dev_info(&dev->dev, "not setting up bridge for bus " |
533 | "for bus %d\n", pci_name(dev), b->number); | 526 | "%04x:%02x\n", pci_domain_nr(b), b->number); |
534 | break; | 527 | break; |
535 | } | 528 | } |
536 | } | 529 | } |