vsprintf: use %pR, %pr instead of %pRt, %pRf

Jesse accidentally applied v1 [1] of the patchset instead of v2 [2].  This
is the diff between v1 and v2.

The changes in this patch are:
    - tidied vsprintf stack buffer to shrink and compute size more
      accurately
    - use %pR for decoding and %pr for "raw" (with type and flags) instead
      of adding %pRt and %pRf

[1] http://lkml.org/lkml/2009/10/6/491
[2] http://lkml.org/lkml/2009/10/13/441

Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

1 files changed, 36 insertions, 43 deletions

diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index ceb75333862b..ed6916bac675 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -71,53 +71,50 @@ static void pbus_assign_resources_sorted(const struct pci_bus *bus)
 void pci_setup_cardbus(struct pci_bus *bus)
 {
         struct pci_dev *bridge = bus->self;
+        struct resource *res;
         struct pci_bus_region region;
 
         dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n",
                  pci_domain_nr(bus), bus->number);
 
-        pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
-        if (bus->resource[0]->flags & IORESOURCE_IO) {
+        res = bus->resource[0];
+        pcibios_resource_to_bus(bridge, &region, res);
+        if (res->flags & IORESOURCE_IO) {
                 /*
                  * The IO resource is allocated a range twice as large as it
                  * would normally need.  This allows us to set both IO regs.
                  */
-                dev_info(&bridge->dev, "  IO window: %#08lx-%#08lx\n",
-                       (unsigned long)region.start,
-                       (unsigned long)region.end);
+                dev_info(&bridge->dev, "  bridge window %pR\n", res);
                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
                                         region.start);
                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
                                         region.end);
         }
 
-        pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
-        if (bus->resource[1]->flags & IORESOURCE_IO) {
-                dev_info(&bridge->dev, "  IO window: %#08lx-%#08lx\n",
-                       (unsigned long)region.start,
-                       (unsigned long)region.end);
+        res = bus->resource[1];
+        pcibios_resource_to_bus(bridge, &region, res);
+        if (res->flags & IORESOURCE_IO) {
+                dev_info(&bridge->dev, "  bridge window %pR\n", res);
                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
                                         region.start);
                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
                                         region.end);
         }
 
-        pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
-        if (bus->resource[2]->flags & IORESOURCE_MEM) {
-                dev_info(&bridge->dev, "  PREFETCH window: %#08lx-%#08lx\n",
-                       (unsigned long)region.start,
-                       (unsigned long)region.end);
+        res = bus->resource[2];
+        pcibios_resource_to_bus(bridge, &region, res);
+        if (res->flags & IORESOURCE_MEM) {
+                dev_info(&bridge->dev, "  bridge window %pR\n", res);
                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
                                         region.start);
                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
                                         region.end);
         }
 
-        pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
-        if (bus->resource[3]->flags & IORESOURCE_MEM) {
-                dev_info(&bridge->dev, "  MEM window: %#08lx-%#08lx\n",
-                       (unsigned long)region.start,
-                       (unsigned long)region.end);
+        res = bus->resource[3];
+        pcibios_resource_to_bus(bridge, &region, res);
+        if (res->flags & IORESOURCE_MEM) {
+                dev_info(&bridge->dev, "  bridge window %pR\n", res);
                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
                                         region.start);
                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
@@ -140,6 +137,7 @@ EXPORT_SYMBOL(pci_setup_cardbus);
 static void pci_setup_bridge(struct pci_bus *bus)
 {
         struct pci_dev *bridge = bus->self;
+        struct resource *res;
         struct pci_bus_region region;
         u32 l, bu, lu, io_upper16;
         int pref_mem64;
@@ -151,23 +149,22 @@ static void pci_setup_bridge(struct pci_bus *bus)
                  pci_domain_nr(bus), bus->number);
 
         /* Set up the top and bottom of the PCI I/O segment for this bus. */
-        pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
-        if (bus->resource[0]->flags & IORESOURCE_IO) {
+        res = bus->resource[0];
+        pcibios_resource_to_bus(bridge, &region, res);
+        if (res->flags & IORESOURCE_IO) {
                 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
                 l &= 0xffff0000;
                 l |= (region.start >> 8) & 0x00f0;
                 l |= region.end & 0xf000;
                 /* Set up upper 16 bits of I/O base/limit. */
                 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
-                dev_info(&bridge->dev, "  IO window: %#04lx-%#04lx\n",
-                    (unsigned long)region.start,
-                    (unsigned long)region.end);
+                dev_info(&bridge->dev, "  bridge window %pR\n", res);
         }
         else {
                 /* Clear upper 16 bits of I/O base/limit. */
                 io_upper16 = 0;
                 l = 0x00f0;
-                dev_info(&bridge->dev, "  IO window: disabled\n");
+                dev_info(&bridge->dev, "  bridge window [io  disabled]\n");
         }
         /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
         pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
@@ -178,17 +175,16 @@ static void pci_setup_bridge(struct pci_bus *bus)
 
         /* Set up the top and bottom of the PCI Memory segment
            for this bus. */
-        pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
-        if (bus->resource[1]->flags & IORESOURCE_MEM) {
+        res = bus->resource[1];
+        pcibios_resource_to_bus(bridge, &region, res);
+        if (res->flags & IORESOURCE_MEM) {
                 l = (region.start >> 16) & 0xfff0;
                 l |= region.end & 0xfff00000;
-                dev_info(&bridge->dev, "  MEM window: %#08lx-%#08lx\n",
-                    (unsigned long)region.start,
-                    (unsigned long)region.end);
+                dev_info(&bridge->dev, "  bridge window %pR\n", res);
         }
         else {
                 l = 0x0000fff0;
-                dev_info(&bridge->dev, "  MEM window: disabled\n");
+                dev_info(&bridge->dev, "  bridge window [mem disabled]\n");
         }
         pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
 
@@ -200,24 +196,21 @@ static void pci_setup_bridge(struct pci_bus *bus)
         /* Set up PREF base/limit. */
         pref_mem64 = 0;
         bu = lu = 0;
-        pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
-        if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
-                int width = 8;
+        res = bus->resource[2];
+        pcibios_resource_to_bus(bridge, &region, res);
+        if (res->flags & IORESOURCE_PREFETCH) {
                 l = (region.start >> 16) & 0xfff0;
                 l |= region.end & 0xfff00000;
-                if (bus->resource[2]->flags & IORESOURCE_MEM_64) {
+                if (res->flags & IORESOURCE_MEM_64) {
                         pref_mem64 = 1;
                         bu = upper_32_bits(region.start);
                         lu = upper_32_bits(region.end);
-                        width = 16;
                 }
-                dev_info(&bridge->dev, "  PREFETCH window: %#0*llx-%#0*llx\n",
-                                width, (unsigned long long)region.start,
-                                width, (unsigned long long)region.end);
+                dev_info(&bridge->dev, "  bridge window %pR\n", res);
         }
         else {
                 l = 0x0000fff0;
-                dev_info(&bridge->dev, "  PREFETCH window: disabled\n");
+                dev_info(&bridge->dev, "  bridge window [mem pref disabled]\n");
         }
         pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
 
@@ -391,7 +384,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
                         order = __ffs(align) - 20;
                         if (order > 11) {
                                 dev_warn(&dev->dev, "BAR %d: bad alignment %llx: "
-                                         "%pRt\n", i, (unsigned long long)align, r);
+                                         "%pR\n", i, (unsigned long long)align, r);
                                 r->flags = 0;
                                 continue;
                         }
@@ -582,7 +575,7 @@ static void pci_bus_dump_res(struct pci_bus *bus)
                 if (!res || !res->end)
                         continue;
 
-                dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pRt\n", i, res);
+                dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
         }
 }