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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/pci/quirks.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r--drivers/pci/quirks.c1352
1 files changed, 1352 insertions, 0 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
new file mode 100644
index 000000000000..1cfe9538fd19
--- /dev/null
+++ b/drivers/pci/quirks.c
@@ -0,0 +1,1352 @@
1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * The bridge optimization stuff has been removed. If you really
11 * have a silly BIOS which is unable to set your host bridge right,
12 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
13 */
14
15#include <linux/config.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/delay.h>
21
22/* Deal with broken BIOS'es that neglect to enable passive release,
23 which can cause problems in combination with the 82441FX/PPro MTRRs */
24static void __devinit quirk_passive_release(struct pci_dev *dev)
25{
26 struct pci_dev *d = NULL;
27 unsigned char dlc;
28
29 /* We have to make sure a particular bit is set in the PIIX3
30 ISA bridge, so we have to go out and find it. */
31 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
32 pci_read_config_byte(d, 0x82, &dlc);
33 if (!(dlc & 1<<1)) {
34 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
35 dlc |= 1<<1;
36 pci_write_config_byte(d, 0x82, dlc);
37 }
38 }
39}
40DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
41
42/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
43 but VIA don't answer queries. If you happen to have good contacts at VIA
44 ask them for me please -- Alan
45
46 This appears to be BIOS not version dependent. So presumably there is a
47 chipset level fix */
48int isa_dma_bridge_buggy; /* Exported */
49
50static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
51{
52 if (!isa_dma_bridge_buggy) {
53 isa_dma_bridge_buggy=1;
54 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
55 }
56}
57 /*
58 * Its not totally clear which chipsets are the problematic ones
59 * We know 82C586 and 82C596 variants are affected.
60 */
61DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
62DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
63DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
64DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
65DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
66DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
67DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
68
69int pci_pci_problems;
70
71/*
72 * Chipsets where PCI->PCI transfers vanish or hang
73 */
74static void __devinit quirk_nopcipci(struct pci_dev *dev)
75{
76 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
77 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
78 pci_pci_problems |= PCIPCI_FAIL;
79 }
80}
81DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
83
84/*
85 * Triton requires workarounds to be used by the drivers
86 */
87static void __devinit quirk_triton(struct pci_dev *dev)
88{
89 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
90 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
91 pci_pci_problems |= PCIPCI_TRITON;
92 }
93}
94DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
95DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
98
99/*
100 * VIA Apollo KT133 needs PCI latency patch
101 * Made according to a windows driver based patch by George E. Breese
102 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
103 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
104 * the info on which Mr Breese based his work.
105 *
106 * Updated based on further information from the site and also on
107 * information provided by VIA
108 */
109static void __devinit quirk_vialatency(struct pci_dev *dev)
110{
111 struct pci_dev *p;
112 u8 rev;
113 u8 busarb;
114 /* Ok we have a potential problem chipset here. Now see if we have
115 a buggy southbridge */
116
117 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
118 if (p!=NULL) {
119 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
120 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
121 /* Check for buggy part revisions */
122 if (rev < 0x40 || rev > 0x42)
123 goto exit;
124 } else {
125 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
126 if (p==NULL) /* No problem parts */
127 goto exit;
128 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
129 /* Check for buggy part revisions */
130 if (rev < 0x10 || rev > 0x12)
131 goto exit;
132 }
133
134 /*
135 * Ok we have the problem. Now set the PCI master grant to
136 * occur every master grant. The apparent bug is that under high
137 * PCI load (quite common in Linux of course) you can get data
138 * loss when the CPU is held off the bus for 3 bus master requests
139 * This happens to include the IDE controllers....
140 *
141 * VIA only apply this fix when an SB Live! is present but under
142 * both Linux and Windows this isnt enough, and we have seen
143 * corruption without SB Live! but with things like 3 UDMA IDE
144 * controllers. So we ignore that bit of the VIA recommendation..
145 */
146
147 pci_read_config_byte(dev, 0x76, &busarb);
148 /* Set bit 4 and bi 5 of byte 76 to 0x01
149 "Master priority rotation on every PCI master grant */
150 busarb &= ~(1<<5);
151 busarb |= (1<<4);
152 pci_write_config_byte(dev, 0x76, busarb);
153 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
154exit:
155 pci_dev_put(p);
156}
157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
160
161/*
162 * VIA Apollo VP3 needs ETBF on BT848/878
163 */
164static void __devinit quirk_viaetbf(struct pci_dev *dev)
165{
166 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
167 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
168 pci_pci_problems |= PCIPCI_VIAETBF;
169 }
170}
171DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
172
173static void __devinit quirk_vsfx(struct pci_dev *dev)
174{
175 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
176 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
177 pci_pci_problems |= PCIPCI_VSFX;
178 }
179}
180DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
181
182/*
183 * Ali Magik requires workarounds to be used by the drivers
184 * that DMA to AGP space. Latency must be set to 0xA and triton
185 * workaround applied too
186 * [Info kindly provided by ALi]
187 */
188static void __init quirk_alimagik(struct pci_dev *dev)
189{
190 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
191 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
192 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
193 }
194}
195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
197
198/*
199 * Natoma has some interesting boundary conditions with Zoran stuff
200 * at least
201 */
202static void __devinit quirk_natoma(struct pci_dev *dev)
203{
204 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
205 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
206 pci_pci_problems |= PCIPCI_NATOMA;
207 }
208}
209DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
210DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
213DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
215
216/*
217 * This chip can cause PCI parity errors if config register 0xA0 is read
218 * while DMAs are occurring.
219 */
220static void __devinit quirk_citrine(struct pci_dev *dev)
221{
222 dev->cfg_size = 0xA0;
223}
224DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
225
226/*
227 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
228 * If it's needed, re-allocate the region.
229 */
230static void __devinit quirk_s3_64M(struct pci_dev *dev)
231{
232 struct resource *r = &dev->resource[0];
233
234 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
235 r->start = 0;
236 r->end = 0x3ffffff;
237 }
238}
239DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
240DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
241
242static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
243{
244 region &= ~(size-1);
245 if (region) {
246 struct resource *res = dev->resource + nr;
247
248 res->name = pci_name(dev);
249 res->start = region;
250 res->end = region + size - 1;
251 res->flags = IORESOURCE_IO;
252 pci_claim_resource(dev, nr);
253 }
254}
255
256/*
257 * ATI Northbridge setups MCE the processor if you even
258 * read somewhere between 0x3b0->0x3bb or read 0x3d3
259 */
260static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
261{
262 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
263 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
264 request_region(0x3b0, 0x0C, "RadeonIGP");
265 request_region(0x3d3, 0x01, "RadeonIGP");
266}
267DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
268
269/*
270 * Let's make the southbridge information explicit instead
271 * of having to worry about people probing the ACPI areas,
272 * for example.. (Yes, it happens, and if you read the wrong
273 * ACPI register it will put the machine to sleep with no
274 * way of waking it up again. Bummer).
275 *
276 * ALI M7101: Two IO regions pointed to by words at
277 * 0xE0 (64 bytes of ACPI registers)
278 * 0xE2 (32 bytes of SMB registers)
279 */
280static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
281{
282 u16 region;
283
284 pci_read_config_word(dev, 0xE0, &region);
285 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
286 pci_read_config_word(dev, 0xE2, &region);
287 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
288}
289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
290
291/*
292 * PIIX4 ACPI: Two IO regions pointed to by longwords at
293 * 0x40 (64 bytes of ACPI registers)
294 * 0x90 (32 bytes of SMB registers)
295 */
296static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
297{
298 u32 region;
299
300 pci_read_config_dword(dev, 0x40, &region);
301 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
302 pci_read_config_dword(dev, 0x90, &region);
303 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
304}
305DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
306
307/*
308 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
309 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
310 * 0x58 (64 bytes of GPIO I/O space)
311 */
312static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
313{
314 u32 region;
315
316 pci_read_config_dword(dev, 0x40, &region);
317 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES);
318
319 pci_read_config_dword(dev, 0x58, &region);
320 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1);
321}
322DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
323DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
326DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
327DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
328DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
329DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
330DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
331
332/*
333 * VIA ACPI: One IO region pointed to by longword at
334 * 0x48 or 0x20 (256 bytes of ACPI registers)
335 */
336static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
337{
338 u8 rev;
339 u32 region;
340
341 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
342 if (rev & 0x10) {
343 pci_read_config_dword(dev, 0x48, &region);
344 region &= PCI_BASE_ADDRESS_IO_MASK;
345 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
346 }
347}
348DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
349
350/*
351 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
352 * 0x48 (256 bytes of ACPI registers)
353 * 0x70 (128 bytes of hardware monitoring register)
354 * 0x90 (16 bytes of SMB registers)
355 */
356static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
357{
358 u16 hm;
359 u32 smb;
360
361 quirk_vt82c586_acpi(dev);
362
363 pci_read_config_word(dev, 0x70, &hm);
364 hm &= PCI_BASE_ADDRESS_IO_MASK;
365 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
366
367 pci_read_config_dword(dev, 0x90, &smb);
368 smb &= PCI_BASE_ADDRESS_IO_MASK;
369 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
370}
371DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
372
373
374#ifdef CONFIG_X86_IO_APIC
375
376#include <asm/io_apic.h>
377
378/*
379 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
380 * devices to the external APIC.
381 *
382 * TODO: When we have device-specific interrupt routers,
383 * this code will go away from quirks.
384 */
385static void __devinit quirk_via_ioapic(struct pci_dev *dev)
386{
387 u8 tmp;
388
389 if (nr_ioapics < 1)
390 tmp = 0; /* nothing routed to external APIC */
391 else
392 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
393
394 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
395 tmp == 0 ? "Disa" : "Ena");
396
397 /* Offset 0x58: External APIC IRQ output control */
398 pci_write_config_byte (dev, 0x58, tmp);
399}
400DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
401
402/*
403 * The AMD io apic can hang the box when an apic irq is masked.
404 * We check all revs >= B0 (yet not in the pre production!) as the bug
405 * is currently marked NoFix
406 *
407 * We have multiple reports of hangs with this chipset that went away with
408 * noapic specified. For the moment we assume its the errata. We may be wrong
409 * of course. However the advice is demonstrably good even if so..
410 */
411static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
412{
413 u8 rev;
414
415 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
416 if (rev >= 0x02) {
417 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
418 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
419 }
420}
421DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
422
423static void __init quirk_ioapic_rmw(struct pci_dev *dev)
424{
425 if (dev->devfn == 0 && dev->bus->number == 0)
426 sis_apic_bug = 1;
427}
428DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
429
430int pci_msi_quirk;
431
432#define AMD8131_revA0 0x01
433#define AMD8131_revB0 0x11
434#define AMD8131_MISC 0x40
435#define AMD8131_NIOAMODE_BIT 0
436static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
437{
438 unsigned char revid, tmp;
439
440 pci_msi_quirk = 1;
441 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
442
443 if (nr_ioapics == 0)
444 return;
445
446 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
447 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
448 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
449 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
450 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
451 pci_write_config_byte( dev, AMD8131_MISC, tmp);
452 }
453}
454DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic );
455
456#endif /* CONFIG_X86_IO_APIC */
457
458
459/*
460 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
461 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
462 * when written, it makes an internal connection to the PIC.
463 * For these devices, this register is defined to be 4 bits wide.
464 * Normally this is fine. However for IO-APIC motherboards, or
465 * non-x86 architectures (yes Via exists on PPC among other places),
466 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
467 * interrupts delivered properly.
468 *
469 * TODO: When we have device-specific interrupt routers,
470 * quirk_via_irqpic will go away from quirks.
471 */
472
473/*
474 * FIXME: it is questionable that quirk_via_acpi
475 * is needed. It shows up as an ISA bridge, and does not
476 * support the PCI_INTERRUPT_LINE register at all. Therefore
477 * it seems like setting the pci_dev's 'irq' to the
478 * value of the ACPI SCI interrupt is only done for convenience.
479 * -jgarzik
480 */
481static void __devinit quirk_via_acpi(struct pci_dev *d)
482{
483 /*
484 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
485 */
486 u8 irq;
487 pci_read_config_byte(d, 0x42, &irq);
488 irq &= 0xf;
489 if (irq && (irq != 2))
490 d->irq = irq;
491}
492DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
493DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
494
495/*
496 * PIIX3 USB: We have to disable USB interrupts that are
497 * hardwired to PIRQD# and may be shared with an
498 * external device.
499 *
500 * Legacy Support Register (LEGSUP):
501 * bit13: USB PIRQ Enable (USBPIRQDEN),
502 * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
503 *
504 * We mask out all r/wc bits, too.
505 */
506static void __devinit quirk_piix3_usb(struct pci_dev *dev)
507{
508 u16 legsup;
509
510 pci_read_config_word(dev, 0xc0, &legsup);
511 legsup &= 0x50ef;
512 pci_write_config_word(dev, 0xc0, legsup);
513}
514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb );
515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb );
516
517/*
518 * VIA VT82C598 has its device ID settable and many BIOSes
519 * set it to the ID of VT82C597 for backward compatibility.
520 * We need to switch it off to be able to recognize the real
521 * type of the chip.
522 */
523static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
524{
525 pci_write_config_byte(dev, 0xfc, 0);
526 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
527}
528DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
529
530/*
531 * CardBus controllers have a legacy base address that enables them
532 * to respond as i82365 pcmcia controllers. We don't want them to
533 * do this even if the Linux CardBus driver is not loaded, because
534 * the Linux i82365 driver does not (and should not) handle CardBus.
535 */
536static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
537{
538 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
539 return;
540 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
541}
542DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
543
544/*
545 * Following the PCI ordering rules is optional on the AMD762. I'm not
546 * sure what the designers were smoking but let's not inhale...
547 *
548 * To be fair to AMD, it follows the spec by default, its BIOS people
549 * who turn it off!
550 */
551static void __devinit quirk_amd_ordering(struct pci_dev *dev)
552{
553 u32 pcic;
554 pci_read_config_dword(dev, 0x4C, &pcic);
555 if ((pcic&6)!=6) {
556 pcic |= 6;
557 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
558 pci_write_config_dword(dev, 0x4C, pcic);
559 pci_read_config_dword(dev, 0x84, &pcic);
560 pcic |= (1<<23); /* Required in this mode */
561 pci_write_config_dword(dev, 0x84, pcic);
562 }
563}
564DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
565
566/*
567 * DreamWorks provided workaround for Dunord I-3000 problem
568 *
569 * This card decodes and responds to addresses not apparently
570 * assigned to it. We force a larger allocation to ensure that
571 * nothing gets put too close to it.
572 */
573static void __devinit quirk_dunord ( struct pci_dev * dev )
574{
575 struct resource *r = &dev->resource [1];
576 r->start = 0;
577 r->end = 0xffffff;
578}
579DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
580
581/*
582 * i82380FB mobile docking controller: its PCI-to-PCI bridge
583 * is subtractive decoding (transparent), and does indicate this
584 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
585 * instead of 0x01.
586 */
587static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
588{
589 dev->transparent = 1;
590}
591DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
592DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
593
594/*
595 * Common misconfiguration of the MediaGX/Geode PCI master that will
596 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
597 * datasheets found at http://www.national.com/ds/GX for info on what
598 * these bits do. <christer@weinigel.se>
599 */
600static void __init quirk_mediagx_master(struct pci_dev *dev)
601{
602 u8 reg;
603 pci_read_config_byte(dev, 0x41, &reg);
604 if (reg & 2) {
605 reg &= ~2;
606 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
607 pci_write_config_byte(dev, 0x41, reg);
608 }
609}
610DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
611
612/*
613 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
614 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
615 * secondary channels respectively). If the device reports Compatible mode
616 * but does use BAR0-3 for address decoding, we assume that firmware has
617 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
618 * Exceptions (if they exist) must be handled in chip/architecture specific
619 * fixups.
620 *
621 * Note: for non x86 people. You may need an arch specific quirk to handle
622 * moving IDE devices to native mode as well. Some plug in card devices power
623 * up in compatible mode and assume the BIOS will adjust them.
624 *
625 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
626 * we do now ? We don't want is pci_enable_device to come along
627 * and assign new resources. Both approaches work for that.
628 */
629static void __devinit quirk_ide_bases(struct pci_dev *dev)
630{
631 struct resource *res;
632 int first_bar = 2, last_bar = 0;
633
634 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
635 return;
636
637 res = &dev->resource[0];
638
639 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
640 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
641 res[0].start = res[0].end = res[0].flags = 0;
642 res[1].start = res[1].end = res[1].flags = 0;
643 first_bar = 0;
644 last_bar = 1;
645 }
646
647 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
648 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
649 res[2].start = res[2].end = res[2].flags = 0;
650 res[3].start = res[3].end = res[3].flags = 0;
651 last_bar = 3;
652 }
653
654 if (!last_bar)
655 return;
656
657 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
658 first_bar, last_bar, pci_name(dev));
659}
660DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
661
662/*
663 * Ensure C0 rev restreaming is off. This is normally done by
664 * the BIOS but in the odd case it is not the results are corruption
665 * hence the presence of a Linux check
666 */
667static void __init quirk_disable_pxb(struct pci_dev *pdev)
668{
669 u16 config;
670 u8 rev;
671
672 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
673 if (rev != 0x04) /* Only C0 requires this */
674 return;
675 pci_read_config_word(pdev, 0x40, &config);
676 if (config & (1<<6)) {
677 config &= ~(1<<6);
678 pci_write_config_word(pdev, 0x40, config);
679 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
680 }
681}
682DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
683
684/*
685 * VIA northbridges care about PCI_INTERRUPT_LINE
686 */
687int via_interrupt_line_quirk;
688
689static void __devinit quirk_via_bridge(struct pci_dev *pdev)
690{
691 if(pdev->devfn == 0) {
692 printk(KERN_INFO "PCI: Via IRQ fixup\n");
693 via_interrupt_line_quirk = 1;
694 }
695}
696DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_bridge );
697
698/*
699 * Serverworks CSB5 IDE does not fully support native mode
700 */
701static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
702{
703 u8 prog;
704 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
705 if (prog & 5) {
706 prog &= ~5;
707 pdev->class &= ~5;
708 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
709 /* need to re-assign BARs for compat mode */
710 quirk_ide_bases(pdev);
711 }
712}
713DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
714
715/*
716 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
717 */
718static void __init quirk_ide_samemode(struct pci_dev *pdev)
719{
720 u8 prog;
721
722 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
723
724 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
725 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
726 prog &= ~5;
727 pdev->class &= ~5;
728 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
729 /* need to re-assign BARs for compat mode */
730 quirk_ide_bases(pdev);
731 }
732}
733DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
734
735/* This was originally an Alpha specific thing, but it really fits here.
736 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
737 */
738static void __init quirk_eisa_bridge(struct pci_dev *dev)
739{
740 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
741}
742DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
743
744/*
745 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
746 * is not activated. The myth is that Asus said that they do not want the
747 * users to be irritated by just another PCI Device in the Win98 device
748 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
749 * package 2.7.0 for details)
750 *
751 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
752 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
753 * becomes necessary to do this tweak in two steps -- I've chosen the Host
754 * bridge as trigger.
755 */
756static int __initdata asus_hides_smbus = 0;
757
758static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
759{
760 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
761 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
762 switch(dev->subsystem_device) {
763 case 0x8070: /* P4B */
764 case 0x8088: /* P4B533 */
765 case 0x1626: /* L3C notebook */
766 asus_hides_smbus = 1;
767 }
768 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
769 switch(dev->subsystem_device) {
770 case 0x80b1: /* P4GE-V */
771 case 0x80b2: /* P4PE */
772 case 0x8093: /* P4B533-V */
773 asus_hides_smbus = 1;
774 }
775 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
776 switch(dev->subsystem_device) {
777 case 0x8030: /* P4T533 */
778 asus_hides_smbus = 1;
779 }
780 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
781 switch (dev->subsystem_device) {
782 case 0x8070: /* P4G8X Deluxe */
783 asus_hides_smbus = 1;
784 }
785 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
786 switch (dev->subsystem_device) {
787 case 0x1751: /* M2N notebook */
788 case 0x1821: /* M5N notebook */
789 asus_hides_smbus = 1;
790 }
791 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
792 switch (dev->subsystem_device) {
793 case 0x184b: /* W1N notebook */
794 case 0x186a: /* M6Ne notebook */
795 asus_hides_smbus = 1;
796 }
797 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
798 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
799 switch(dev->subsystem_device) {
800 case 0x088C: /* HP Compaq nc8000 */
801 case 0x0890: /* HP Compaq nc6000 */
802 asus_hides_smbus = 1;
803 }
804 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
805 switch (dev->subsystem_device) {
806 case 0x12bc: /* HP D330L */
807 asus_hides_smbus = 1;
808 }
809 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
810 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
811 switch(dev->subsystem_device) {
812 case 0x0001: /* Toshiba Satellite A40 */
813 asus_hides_smbus = 1;
814 }
815 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
816 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
817 switch(dev->subsystem_device) {
818 case 0xC00C: /* Samsung P35 notebook */
819 asus_hides_smbus = 1;
820 }
821 }
822}
823DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
824DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
825DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
826DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
827DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
828DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
829DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
830
831static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
832{
833 u16 val;
834
835 if (likely(!asus_hides_smbus))
836 return;
837
838 pci_read_config_word(dev, 0xF2, &val);
839 if (val & 0x8) {
840 pci_write_config_word(dev, 0xF2, val & (~0x8));
841 pci_read_config_word(dev, 0xF2, &val);
842 if (val & 0x8)
843 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
844 else
845 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
846 }
847}
848DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
849DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
850DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
851DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
852DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
853
854/*
855 * SiS 96x south bridge: BIOS typically hides SMBus device...
856 */
857static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
858{
859 u8 val = 0;
860 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
861 pci_read_config_byte(dev, 0x77, &val);
862 pci_write_config_byte(dev, 0x77, val & ~0x10);
863 pci_read_config_byte(dev, 0x77, &val);
864}
865
866
867#define UHCI_USBLEGSUP 0xc0 /* legacy support */
868#define UHCI_USBCMD 0 /* command register */
869#define UHCI_USBSTS 2 /* status register */
870#define UHCI_USBINTR 4 /* interrupt register */
871#define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
872#define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
873#define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */
874#define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */
875#define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */
876
877#define OHCI_CONTROL 0x04
878#define OHCI_CMDSTATUS 0x08
879#define OHCI_INTRSTATUS 0x0c
880#define OHCI_INTRENABLE 0x10
881#define OHCI_INTRDISABLE 0x14
882#define OHCI_OCR (1 << 3) /* ownership change request */
883#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
884#define OHCI_INTR_OC (1 << 30) /* ownership change */
885
886#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
887#define EHCI_USBCMD 0 /* command register */
888#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
889#define EHCI_USBSTS 4 /* status register */
890#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
891#define EHCI_USBINTR 8 /* interrupt register */
892#define EHCI_USBLEGSUP 0 /* legacy support register */
893#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
894#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
895#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
896#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
897
898int usb_early_handoff __devinitdata = 0;
899static int __init usb_handoff_early(char *str)
900{
901 usb_early_handoff = 1;
902 return 0;
903}
904__setup("usb-handoff", usb_handoff_early);
905
906static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
907{
908 unsigned long base = 0;
909 int wait_time, delta;
910 u16 val, sts;
911 int i;
912
913 for (i = 0; i < PCI_ROM_RESOURCE; i++)
914 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
915 base = pci_resource_start(pdev, i);
916 break;
917 }
918
919 if (!base)
920 return;
921
922 /*
923 * stop controller
924 */
925 sts = inw(base + UHCI_USBSTS);
926 val = inw(base + UHCI_USBCMD);
927 val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE);
928 outw(val, base + UHCI_USBCMD);
929
930 /*
931 * wait while it stops if it was running
932 */
933 if ((sts & UHCI_USBSTS_HALTED) == 0)
934 {
935 wait_time = 1000;
936 delta = 100;
937
938 do {
939 outw(0x1f, base + UHCI_USBSTS);
940 udelay(delta);
941 wait_time -= delta;
942 val = inw(base + UHCI_USBSTS);
943 if (val & UHCI_USBSTS_HALTED)
944 break;
945 } while (wait_time > 0);
946 }
947
948 /*
949 * disable interrupts & legacy support
950 */
951 outw(0, base + UHCI_USBINTR);
952 outw(0x1f, base + UHCI_USBSTS);
953 pci_read_config_word(pdev, UHCI_USBLEGSUP, &val);
954 if (val & 0xbf)
955 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT);
956
957}
958
959static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
960{
961 void __iomem *base;
962 int wait_time;
963
964 base = ioremap_nocache(pci_resource_start(pdev, 0),
965 pci_resource_len(pdev, 0));
966 if (base == NULL) return;
967
968 if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
969 wait_time = 500; /* 0.5 seconds */
970 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
971 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
972 while (wait_time > 0 &&
973 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
974 wait_time -= 10;
975 msleep(10);
976 }
977 }
978
979 /*
980 * disable interrupts
981 */
982 writel(~(u32)0, base + OHCI_INTRDISABLE);
983 writel(~(u32)0, base + OHCI_INTRSTATUS);
984
985 iounmap(base);
986}
987
988static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
989{
990 int wait_time, delta;
991 void __iomem *base, *op_reg_base;
992 u32 hcc_params, val, temp;
993 u8 cap_length;
994
995 base = ioremap_nocache(pci_resource_start(pdev, 0),
996 pci_resource_len(pdev, 0));
997 if (base == NULL) return;
998
999 cap_length = readb(base);
1000 op_reg_base = base + cap_length;
1001 hcc_params = readl(base + EHCI_HCC_PARAMS);
1002 hcc_params = (hcc_params >> 8) & 0xff;
1003 if (hcc_params) {
1004 pci_read_config_dword(pdev,
1005 hcc_params + EHCI_USBLEGSUP,
1006 &val);
1007 if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) {
1008 /*
1009 * Ok, BIOS is in smm mode, try to hand off...
1010 */
1011 pci_read_config_dword(pdev,
1012 hcc_params + EHCI_USBLEGCTLSTS,
1013 &temp);
1014 pci_write_config_dword(pdev,
1015 hcc_params + EHCI_USBLEGCTLSTS,
1016 temp | EHCI_USBLEGCTLSTS_SOOE);
1017 val |= EHCI_USBLEGSUP_OS;
1018 pci_write_config_dword(pdev,
1019 hcc_params + EHCI_USBLEGSUP,
1020 val);
1021
1022 wait_time = 500;
1023 do {
1024 msleep(10);
1025 wait_time -= 10;
1026 pci_read_config_dword(pdev,
1027 hcc_params + EHCI_USBLEGSUP,
1028 &val);
1029 } while (wait_time && (val & EHCI_USBLEGSUP_BIOS));
1030 if (!wait_time) {
1031 /*
1032 * well, possibly buggy BIOS...
1033 */
1034 printk(KERN_WARNING "EHCI early BIOS handoff "
1035 "failed (BIOS bug ?)\n");
1036 pci_write_config_dword(pdev,
1037 hcc_params + EHCI_USBLEGSUP,
1038 EHCI_USBLEGSUP_OS);
1039 pci_write_config_dword(pdev,
1040 hcc_params + EHCI_USBLEGCTLSTS,
1041 0);
1042 }
1043 }
1044 }
1045
1046 /*
1047 * halt EHCI & disable its interrupts in any case
1048 */
1049 val = readl(op_reg_base + EHCI_USBSTS);
1050 if ((val & EHCI_USBSTS_HALTED) == 0) {
1051 val = readl(op_reg_base + EHCI_USBCMD);
1052 val &= ~EHCI_USBCMD_RUN;
1053 writel(val, op_reg_base + EHCI_USBCMD);
1054
1055 wait_time = 2000;
1056 delta = 100;
1057 do {
1058 writel(0x3f, op_reg_base + EHCI_USBSTS);
1059 udelay(delta);
1060 wait_time -= delta;
1061 val = readl(op_reg_base + EHCI_USBSTS);
1062 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
1063 break;
1064 }
1065 } while (wait_time > 0);
1066 }
1067 writel(0, op_reg_base + EHCI_USBINTR);
1068 writel(0x3f, op_reg_base + EHCI_USBSTS);
1069
1070 iounmap(base);
1071
1072 return;
1073}
1074
1075
1076
1077static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
1078{
1079 if (!usb_early_handoff)
1080 return;
1081
1082 if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */
1083 quirk_usb_handoff_uhci(pdev);
1084 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */
1085 quirk_usb_handoff_ohci(pdev);
1086 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */
1087 quirk_usb_disable_ehci(pdev);
1088 }
1089
1090 return;
1091}
1092DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
1093
1094/*
1095 * ... This is further complicated by the fact that some SiS96x south
1096 * bridges pretend to be 85C503/5513 instead. In that case see if we
1097 * spotted a compatible north bridge to make sure.
1098 * (pci_find_device doesn't work yet)
1099 *
1100 * We can also enable the sis96x bit in the discovery register..
1101 */
1102static int __devinitdata sis_96x_compatible = 0;
1103
1104#define SIS_DETECT_REGISTER 0x40
1105
1106static void __init quirk_sis_503(struct pci_dev *dev)
1107{
1108 u8 reg;
1109 u16 devid;
1110
1111 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1112 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1113 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1114 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1115 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1116 return;
1117 }
1118
1119 /* Make people aware that we changed the config.. */
1120 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1121
1122 /*
1123 * Ok, it now shows up as a 96x.. The 96x quirks are after
1124 * the 503 quirk in the quirk table, so they'll automatically
1125 * run and enable things like the SMBus device
1126 */
1127 dev->device = devid;
1128}
1129
1130static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1131{
1132 sis_96x_compatible = 1;
1133}
1134DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1135DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1136DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1137DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1138DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1139DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1140
1141DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1142
1143DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1144DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1145DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1146DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1147
1148#ifdef CONFIG_X86_IO_APIC
1149static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1150{
1151 int i;
1152
1153 if ((pdev->class >> 8) != 0xff00)
1154 return;
1155
1156 /* the first BAR is the location of the IO APIC...we must
1157 * not touch this (and it's already covered by the fixmap), so
1158 * forcibly insert it into the resource tree */
1159 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1160 insert_resource(&iomem_resource, &pdev->resource[0]);
1161
1162 /* The next five BARs all seem to be rubbish, so just clean
1163 * them out */
1164 for (i=1; i < 6; i++) {
1165 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1166 }
1167
1168}
1169DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1170#endif
1171
1172#ifdef CONFIG_SCSI_SATA
1173static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1174{
1175 u8 prog, comb, tmp;
1176 int ich = 0;
1177
1178 /*
1179 * Narrow down to Intel SATA PCI devices.
1180 */
1181 switch (pdev->device) {
1182 /* PCI ids taken from drivers/scsi/ata_piix.c */
1183 case 0x24d1:
1184 case 0x24df:
1185 case 0x25a3:
1186 case 0x25b0:
1187 ich = 5;
1188 break;
1189 case 0x2651:
1190 case 0x2652:
1191 case 0x2653:
1192 ich = 6;
1193 break;
1194 case 0x27c0:
1195 case 0x27c4:
1196 ich = 7;
1197 break;
1198 default:
1199 /* we do not handle this PCI device */
1200 return;
1201 }
1202
1203 /*
1204 * Read combined mode register.
1205 */
1206 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1207
1208 if (ich == 5) {
1209 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1210 if (tmp == 0x4) /* bits 10x */
1211 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1212 else if (tmp == 0x6) /* bits 11x */
1213 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1214 else
1215 return; /* not in combined mode */
1216 } else {
1217 WARN_ON((ich != 6) && (ich != 7));
1218 tmp &= 0x3; /* interesting bits 1:0 */
1219 if (tmp & (1 << 0))
1220 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1221 else if (tmp & (1 << 1))
1222 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1223 else
1224 return; /* not in combined mode */
1225 }
1226
1227 /*
1228 * Read programming interface register.
1229 * (Tells us if it's legacy or native mode)
1230 */
1231 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1232
1233 /* if SATA port is in native mode, we're ok. */
1234 if (prog & comb)
1235 return;
1236
1237 /* SATA port is in legacy mode. Reserve port so that
1238 * IDE driver does not attempt to use it. If request_region
1239 * fails, it will be obvious at boot time, so we don't bother
1240 * checking return values.
1241 */
1242 if (comb == (1 << 0))
1243 request_region(0x1f0, 8, "libata"); /* port 0 */
1244 else
1245 request_region(0x170, 8, "libata"); /* port 1 */
1246}
1247DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
1248#endif /* CONFIG_SCSI_SATA */
1249
1250
1251int pcie_mch_quirk;
1252
1253static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1254{
1255 pcie_mch_quirk = 1;
1256}
1257DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1258DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1260
1261static void __devinit quirk_netmos(struct pci_dev *dev)
1262{
1263 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1264 unsigned int num_serial = dev->subsystem_device & 0xf;
1265
1266 /*
1267 * These Netmos parts are multiport serial devices with optional
1268 * parallel ports. Even when parallel ports are present, they
1269 * are identified as class SERIAL, which means the serial driver
1270 * will claim them. To prevent this, mark them as class OTHER.
1271 * These combo devices should be claimed by parport_serial.
1272 *
1273 * The subdevice ID is of the form 0x00PS, where <P> is the number
1274 * of parallel ports and <S> is the number of serial ports.
1275 */
1276 switch (dev->device) {
1277 case PCI_DEVICE_ID_NETMOS_9735:
1278 case PCI_DEVICE_ID_NETMOS_9745:
1279 case PCI_DEVICE_ID_NETMOS_9835:
1280 case PCI_DEVICE_ID_NETMOS_9845:
1281 case PCI_DEVICE_ID_NETMOS_9855:
1282 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1283 num_parallel) {
1284 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1285 "%u serial); changing class SERIAL to OTHER "
1286 "(use parport_serial)\n",
1287 dev->device, num_parallel, num_serial);
1288 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1289 (dev->class & 0xff);
1290 }
1291 }
1292}
1293DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1294
1295static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1296{
1297 while (f < end) {
1298 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1299 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1300 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1301 f->hook(dev);
1302 }
1303 f++;
1304 }
1305}
1306
1307extern struct pci_fixup __start_pci_fixups_early[];
1308extern struct pci_fixup __end_pci_fixups_early[];
1309extern struct pci_fixup __start_pci_fixups_header[];
1310extern struct pci_fixup __end_pci_fixups_header[];
1311extern struct pci_fixup __start_pci_fixups_final[];
1312extern struct pci_fixup __end_pci_fixups_final[];
1313extern struct pci_fixup __start_pci_fixups_enable[];
1314extern struct pci_fixup __end_pci_fixups_enable[];
1315
1316
1317void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1318{
1319 struct pci_fixup *start, *end;
1320
1321 switch(pass) {
1322 case pci_fixup_early:
1323 start = __start_pci_fixups_early;
1324 end = __end_pci_fixups_early;
1325 break;
1326
1327 case pci_fixup_header:
1328 start = __start_pci_fixups_header;
1329 end = __end_pci_fixups_header;
1330 break;
1331
1332 case pci_fixup_final:
1333 start = __start_pci_fixups_final;
1334 end = __end_pci_fixups_final;
1335 break;
1336
1337 case pci_fixup_enable:
1338 start = __start_pci_fixups_enable;
1339 end = __end_pci_fixups_enable;
1340 break;
1341
1342 default:
1343 /* stupid compiler warning, you would think with an enum... */
1344 return;
1345 }
1346 pci_do_fixups(dev, start, end);
1347}
1348
1349EXPORT_SYMBOL(pcie_mch_quirk);
1350#ifdef CONFIG_HOTPLUG
1351EXPORT_SYMBOL(pci_fixup_device);
1352#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 01:03:04 -0500