aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pci/quirks.c
diff options
context:
space:
mode:
authorRyan Desfosses <ryan@desfo.org>2014-04-18 20:13:50 -0400
committerBjorn Helgaas <bhelgaas@google.com>2014-06-10 22:20:42 -0400
commit227f06470502c4fea3d93df1f12a77e3e37f6263 (patch)
tree817a80fa89d17305a47a3e4e4012d36ae6cac36c /drivers/pci/quirks.c
parent3c78bc61f5ef3bc87e7f94f67ec737d2273f120b (diff)
PCI: Merge multi-line quoted strings
Merge quoted strings that are broken across lines into a single entity. The compiler merges them anyway, but checkpatch complains about it, and merging them makes it easier to grep for strings. No functional change. [bhelgaas: changelog, do the same for everything under drivers/pci] Signed-off-by: Ryan Desfosses <ryan@desfo.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r--drivers/pci/quirks.c79
1 files changed, 33 insertions, 46 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index e0d78d23483a..f01c50d9f6d7 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -315,8 +315,7 @@ static void quirk_cs5536_vsa(struct pci_dev *dev)
315 if (pci_resource_len(dev, 0) != 8) { 315 if (pci_resource_len(dev, 0) != 8) {
316 struct resource *res = &dev->resource[0]; 316 struct resource *res = &dev->resource[0];
317 res->end = res->start + 8 - 1; 317 res->end = res->start + 8 - 1;
318 dev_info(&dev->dev, "CS5536 ISA bridge bug detected " 318 dev_info(&dev->dev, "CS5536 ISA bridge bug detected (incorrect header); workaround applied\n");
319 "(incorrect header); workaround applied.\n");
320 } 319 }
321} 320}
322DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
@@ -400,7 +399,8 @@ static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int p
400 * let's get enough confirmation reports first. 399 * let's get enough confirmation reports first.
401 */ 400 */
402 base &= -size; 401 base &= -size;
403 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 402 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
403 base + size - 1);
404} 404}
405 405
406static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 406static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
@@ -425,7 +425,8 @@ static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int
425 * reserve it, but let's get enough confirmation reports first. 425 * reserve it, but let's get enough confirmation reports first.
426 */ 426 */
427 base &= -size; 427 base &= -size;
428 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 428 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
429 base + size - 1);
429} 430}
430 431
431/* 432/*
@@ -668,8 +669,7 @@ static void quirk_xio2000a(struct pci_dev *dev)
668 struct pci_dev *pdev; 669 struct pci_dev *pdev;
669 u16 command; 670 u16 command;
670 671
671 dev_warn(&dev->dev, "TI XIO2000a quirk detected; " 672 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
672 "secondary bus fast back-to-back transfers disabled\n");
673 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 673 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
674 pci_read_config_word(pdev, PCI_COMMAND, &command); 674 pci_read_config_word(pdev, PCI_COMMAND, &command);
675 if (command & PCI_COMMAND_FAST_BACK) 675 if (command & PCI_COMMAND_FAST_BACK)
@@ -761,8 +761,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
761static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 761static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
762{ 762{
763 if (dev->subordinate && dev->revision <= 0x12) { 763 if (dev->subordinate && dev->revision <= 0x12) {
764 dev_info(&dev->dev, "AMD8131 rev %x detected; " 764 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
765 "disabling PCI-X MMRBC\n", dev->revision); 765 dev->revision);
766 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 766 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
767 } 767 }
768} 768}
@@ -971,7 +971,8 @@ static void quirk_mediagx_master(struct pci_dev *dev)
971 pci_read_config_byte(dev, 0x41, &reg); 971 pci_read_config_byte(dev, 0x41, &reg);
972 if (reg & 2) { 972 if (reg & 2) {
973 reg &= ~2; 973 reg &= ~2;
974 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 974 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
975 reg);
975 pci_write_config_byte(dev, 0x41, reg); 976 pci_write_config_byte(dev, 0x41, reg);
976 } 977 }
977} 978}
@@ -1262,7 +1263,8 @@ static void asus_hides_smbus_lpc(struct pci_dev *dev)
1262 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1263 pci_write_config_word(dev, 0xF2, val & (~0x8));
1263 pci_read_config_word(dev, 0xF2, &val); 1264 pci_read_config_word(dev, 0xF2, &val);
1264 if (val & 0x8) 1265 if (val & 0x8)
1265 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 1266 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1267 val);
1266 else 1268 else
1267 dev_info(&dev->dev, "Enabled i801 SMBus device\n"); 1269 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1268 } 1270 }
@@ -1410,7 +1412,8 @@ static void asus_hides_ac97_lpc(struct pci_dev *dev)
1410 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1412 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1411 pci_read_config_byte(dev, 0x50, &val); 1413 pci_read_config_byte(dev, 0x50, &val);
1412 if (val & 0xc0) 1414 if (val & 0xc0)
1413 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); 1415 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1416 val);
1414 else 1417 else
1415 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); 1418 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1416 } 1419 }
@@ -1720,8 +1723,8 @@ static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1720 1723
1721 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 1724 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1722 if (!pci_config_word) { 1725 if (!pci_config_word) {
1723 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] " 1726 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1724 "already disabled\n", dev->vendor, dev->device); 1727 dev->vendor, dev->device);
1725 return; 1728 return;
1726 } 1729 }
1727 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 1730 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
@@ -1769,8 +1772,7 @@ static void quirk_plx_pci9050(struct pci_dev *dev)
1769 if (pci_resource_len(dev, bar) == 0x80 && 1772 if (pci_resource_len(dev, bar) == 0x80 &&
1770 (pci_resource_start(dev, bar) & 0x80)) { 1773 (pci_resource_start(dev, bar) & 0x80)) {
1771 struct resource *r = &dev->resource[bar]; 1774 struct resource *r = &dev->resource[bar];
1772 dev_info(&dev->dev, 1775 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1773 "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1774 bar); 1776 bar);
1775 r->flags |= IORESOURCE_UNSET; 1777 r->flags |= IORESOURCE_UNSET;
1776 r->start = 0; 1778 r->start = 0;
@@ -1817,9 +1819,7 @@ static void quirk_netmos(struct pci_dev *dev)
1817 case PCI_DEVICE_ID_NETMOS_9845: 1819 case PCI_DEVICE_ID_NETMOS_9845:
1818 case PCI_DEVICE_ID_NETMOS_9855: 1820 case PCI_DEVICE_ID_NETMOS_9855:
1819 if (num_parallel) { 1821 if (num_parallel) {
1820 dev_info(&dev->dev, "Netmos %04x (%u parallel, " 1822 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1821 "%u serial); changing class SERIAL to OTHER "
1822 "(use parport_serial)\n",
1823 dev->device, num_parallel, num_serial); 1823 dev->device, num_parallel, num_serial);
1824 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 1824 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1825 (dev->class & 0xff); 1825 (dev->class & 0xff);
@@ -1886,8 +1886,7 @@ static void quirk_e100_interrupt(struct pci_dev *dev)
1886 1886
1887 cmd_hi = readb(csr + 3); 1887 cmd_hi = readb(csr + 3);
1888 if (cmd_hi == 0) { 1888 if (cmd_hi == 0) {
1889 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; " 1889 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
1890 "disabling\n");
1891 writeb(1, csr + 3); 1890 writeb(1, csr + 3);
1892 } 1891 }
1893 1892
@@ -1957,8 +1956,7 @@ static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1957 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 1956 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1958 if (!(b & 0x20)) { 1957 if (!(b & 0x20)) {
1959 pci_write_config_byte(dev, 0xf41, b | 0x20); 1958 pci_write_config_byte(dev, 0xf41, b | 0x20);
1960 dev_info(&dev->dev, 1959 dev_info(&dev->dev, "Linking AER extended capability\n");
1961 "Linking AER extended capability\n");
1962 } 1960 }
1963 } 1961 }
1964} 1962}
@@ -1996,8 +1994,7 @@ static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1996 /* Turn off PCI Bus Parking */ 1994 /* Turn off PCI Bus Parking */
1997 pci_write_config_byte(dev, 0x76, b ^ 0x40); 1995 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1998 1996
1999 dev_info(&dev->dev, 1997 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
2000 "Disabling VIA CX700 PCI parking\n");
2001 } 1998 }
2002 } 1999 }
2003 2000
@@ -2012,8 +2009,7 @@ static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2012 /* Disable "Read FIFO Timer" */ 2009 /* Disable "Read FIFO Timer" */
2013 pci_write_config_byte(dev, 0x77, 0x0); 2010 pci_write_config_byte(dev, 0x77, 0x0);
2014 2011
2015 dev_info(&dev->dev, 2012 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
2016 "Disabling VIA CX700 PCI caching\n");
2017 } 2013 }
2018 } 2014 }
2019} 2015}
@@ -2148,8 +2144,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disab
2148static void quirk_disable_msi(struct pci_dev *dev) 2144static void quirk_disable_msi(struct pci_dev *dev)
2149{ 2145{
2150 if (dev->subordinate) { 2146 if (dev->subordinate) {
2151 dev_warn(&dev->dev, "MSI quirk detected; " 2147 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2152 "subordinate MSI disabled\n");
2153 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2148 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2154 } 2149 }
2155} 2150}
@@ -2205,8 +2200,7 @@ static int msi_ht_cap_enabled(struct pci_dev *dev)
2205static void quirk_msi_ht_cap(struct pci_dev *dev) 2200static void quirk_msi_ht_cap(struct pci_dev *dev)
2206{ 2201{
2207 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2202 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2208 dev_warn(&dev->dev, "MSI quirk detected; " 2203 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2209 "subordinate MSI disabled\n");
2210 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2204 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2211 } 2205 }
2212} 2206}
@@ -2230,8 +2224,7 @@ static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2230 if (!pdev) 2224 if (!pdev)
2231 return; 2225 return;
2232 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 2226 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2233 dev_warn(&dev->dev, "MSI quirk detected; " 2227 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2234 "subordinate MSI disabled\n");
2235 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2228 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2236 } 2229 }
2237 pci_dev_put(pdev); 2230 pci_dev_put(pdev);
@@ -2277,8 +2270,7 @@ static void nvenet_msi_disable(struct pci_dev *dev)
2277 if (board_name && 2270 if (board_name &&
2278 (strstr(board_name, "P5N32-SLI PREMIUM") || 2271 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2279 strstr(board_name, "P5N32-E SLI"))) { 2272 strstr(board_name, "P5N32-E SLI"))) {
2280 dev_info(&dev->dev, 2273 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2281 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2282 dev->no_msi = 1; 2274 dev->no_msi = 1;
2283 } 2275 }
2284} 2276}
@@ -2487,8 +2479,7 @@ static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2487 */ 2479 */
2488 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 2480 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2489 if (host_bridge == NULL) { 2481 if (host_bridge == NULL) {
2490 dev_warn(&dev->dev, 2482 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2491 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2492 return; 2483 return;
2493 } 2484 }
2494 2485
@@ -2815,8 +2806,7 @@ static void quirk_intel_mc_errata(struct pci_dev *dev)
2815 */ 2806 */
2816 err = pci_read_config_word(dev, 0x48, &rcc); 2807 err = pci_read_config_word(dev, 0x48, &rcc);
2817 if (err) { 2808 if (err) {
2818 dev_err(&dev->dev, "Error attempting to read the read " 2809 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
2819 "completion coalescing register.\n");
2820 return; 2810 return;
2821 } 2811 }
2822 2812
@@ -2827,13 +2817,11 @@ static void quirk_intel_mc_errata(struct pci_dev *dev)
2827 2817
2828 err = pci_write_config_word(dev, 0x48, rcc); 2818 err = pci_write_config_word(dev, 0x48, rcc);
2829 if (err) { 2819 if (err) {
2830 dev_err(&dev->dev, "Error attempting to write the read " 2820 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
2831 "completion coalescing register.\n");
2832 return; 2821 return;
2833 } 2822 }
2834 2823
2835 pr_info_once("Read completion coalescing disabled due to hardware " 2824 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
2836 "errata relating to 256B MPS.\n");
2837} 2825}
2838/* Intel 5000 series memory controllers and ports 2-7 */ 2826/* Intel 5000 series memory controllers and ports 2-7 */
2839DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 2827DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
@@ -2942,8 +2930,7 @@ static void disable_igfx_irq(struct pci_dev *dev)
2942 2930
2943 /* Check if any interrupt line is still enabled */ 2931 /* Check if any interrupt line is still enabled */
2944 if (readl(regs + I915_DEIER_REG) != 0) { 2932 if (readl(regs + I915_DEIER_REG) != 0) {
2945 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; " 2933 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
2946 "disabling\n");
2947 2934
2948 writel(0, regs + I915_DEIER_REG); 2935 writel(0, regs + I915_DEIER_REG);
2949 } 2936 }
@@ -3110,8 +3097,8 @@ static int __init pci_apply_final_quirks(void)
3110 if (!tmp || cls == tmp) 3097 if (!tmp || cls == tmp)
3111 continue; 3098 continue;
3112 3099
3113 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), " 3100 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3114 "using %u bytes\n", cls << 2, tmp << 2, 3101 cls << 2, tmp << 2,
3115 pci_dfl_cache_line_size << 2); 3102 pci_dfl_cache_line_size << 2);
3116 pci_cache_line_size = pci_dfl_cache_line_size; 3103 pci_cache_line_size = pci_dfl_cache_line_size;
3117 } 3104 }