PCI: determine CLS more intelligently

Till now, CLS has been determined either by arch code or as
L1_CACHE_BYTES.  Only x86 and ia64 set CLS explicitly and x86 doesn't
always get it right.  On most configurations, the chance is that
firmware configures the correct value during boot.

This patch makes pci_init() determine CLS by looking at what firmware
has configured.  It scans all devices and if all non-zero values
agree, the value is used.  If none is configured or there is a
disagreement, pci_dfl_cache_line_size is used.  arch can set the dfl
value (via PCI_CACHE_LINE_BYTES or pci_dfl_cache_line_size) or
override the actual one.

ia64, x86 and sparc64 updated to set the default cls instead of the
actual one.

While at it, declare pci_cache_line_size and pci_dfl_cache_line_size
in pci.h and drop private declarations from arch code.

Signed-off-by: Tejun Heo <tj@kernel.org>
Acked-by: David Miller <davem@davemloft.net>
Acked-by: Greg KH <gregkh@suse.de>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

1 files changed, 28 insertions, 0 deletions

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 245d2cdb4765..1812ae7698de 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2595,9 +2595,37 @@ void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
 static int __init pci_apply_final_quirks(void)
 {
         struct pci_dev *dev = NULL;
+        u8 cls = 0;
+        u8 tmp;
+
+        if (pci_cache_line_size)
+                printk(KERN_DEBUG "PCI: CLS %u bytes\n",
+                       pci_cache_line_size << 2);
 
         while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
                 pci_fixup_device(pci_fixup_final, dev);
+                /*
+                 * If arch hasn't set it explicitly yet, use the CLS
+                 * value shared by all PCI devices.  If there's a
+                 * mismatch, fall back to the default value.
+                 */
+                if (!pci_cache_line_size) {
+                        pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
+                        if (!cls)
+                                cls = tmp;
+                        if (!tmp || cls == tmp)
+                                continue;
+
+                        printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
+                               "using %u bytes\n", cls << 2, tmp << 2,
+                               pci_dfl_cache_line_size << 2);
+                        pci_cache_line_size = pci_dfl_cache_line_size;
+                }
+        }
+        if (!pci_cache_line_size) {
+                printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
+                       cls << 2, pci_dfl_cache_line_size << 2);
+                pci_cache_line_size = cls;
         }
 
         return 0;