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authorJames Bottomley <jejb@mulgrave.il.steeleye.com>2006-08-27 22:59:59 -0400
committerJames Bottomley <jejb@mulgrave.il.steeleye.com>2006-08-27 22:59:59 -0400
commit8ce7a9c159c8c4eb480f0a65c6af753dbf9a1a70 (patch)
treebe59573c0af3617d0cd8a7d61f0ed119e58b1156 /drivers/pci/quirks.c
parentd2afb3ae04e36dbc6e9eb2d8bd54406ff7b6b3bd (diff)
parent01da5fd83d6b2c5e36b77539f6cbdd8f49849225 (diff)
Merge ../linux-2.6
Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r--drivers/pci/quirks.c66
1 files changed, 65 insertions, 1 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index e3c78c39b7e4..73177429fe74 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -438,6 +438,7 @@ static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
438 pci_read_config_dword(dev, 0x48, &region); 438 pci_read_config_dword(dev, 0x48, &region);
439 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); 439 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
440} 440}
441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi );
441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi ); 442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
442 443
443/* 444/*
@@ -990,6 +991,11 @@ static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
990 case 0x8070: /* P4G8X Deluxe */ 991 case 0x8070: /* P4G8X Deluxe */
991 asus_hides_smbus = 1; 992 asus_hides_smbus = 1;
992 } 993 }
994 if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
995 switch (dev->subsystem_device) {
996 case 0x80c9: /* PU-DLS */
997 asus_hides_smbus = 1;
998 }
993 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 999 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
994 switch (dev->subsystem_device) { 1000 switch (dev->subsystem_device) {
995 case 0x1751: /* M2N notebook */ 1001 case 0x1751: /* M2N notebook */
@@ -1058,6 +1064,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asu
1058DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); 1064DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
1059DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); 1065DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
1060DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); 1066DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
1067DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge );
1061DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); 1068DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
1062DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); 1069DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
1063DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge ); 1070DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
@@ -1081,10 +1088,10 @@ static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
1081} 1088}
1082DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); 1089DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1083DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); 1090DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
1091DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc );
1084DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); 1092DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1085DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 1093DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1086DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 1094DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
1087DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc );
1088 1095
1089static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1096static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1090{ 1097{
@@ -1511,6 +1518,63 @@ static void __devinit quirk_netmos(struct pci_dev *dev)
1511} 1518}
1512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); 1519DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1513 1520
1521static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1522{
1523 u16 command;
1524 u32 bar;
1525 u8 __iomem *csr;
1526 u8 cmd_hi;
1527
1528 switch (dev->device) {
1529 /* PCI IDs taken from drivers/net/e100.c */
1530 case 0x1029:
1531 case 0x1030 ... 0x1034:
1532 case 0x1038 ... 0x103E:
1533 case 0x1050 ... 0x1057:
1534 case 0x1059:
1535 case 0x1064 ... 0x106B:
1536 case 0x1091 ... 0x1095:
1537 case 0x1209:
1538 case 0x1229:
1539 case 0x2449:
1540 case 0x2459:
1541 case 0x245D:
1542 case 0x27DC:
1543 break;
1544 default:
1545 return;
1546 }
1547
1548 /*
1549 * Some firmware hands off the e100 with interrupts enabled,
1550 * which can cause a flood of interrupts if packets are
1551 * received before the driver attaches to the device. So
1552 * disable all e100 interrupts here. The driver will
1553 * re-enable them when it's ready.
1554 */
1555 pci_read_config_word(dev, PCI_COMMAND, &command);
1556 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar);
1557
1558 if (!(command & PCI_COMMAND_MEMORY) || !bar)
1559 return;
1560
1561 csr = ioremap(bar, 8);
1562 if (!csr) {
1563 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n",
1564 pci_name(dev));
1565 return;
1566 }
1567
1568 cmd_hi = readb(csr + 3);
1569 if (cmd_hi == 0) {
1570 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts "
1571 "enabled, disabling\n", pci_name(dev));
1572 writeb(1, csr + 3);
1573 }
1574
1575 iounmap(csr);
1576}
1577DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1514 1578
1515static void __devinit fixup_rev1_53c810(struct pci_dev* dev) 1579static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1516{ 1580{