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authorStefan Assmann <sassmann@suse.de>2008-06-11 10:35:16 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-08 11:50:52 -0400
commit426b3b8d535e3e141331dc19c40f457b997c4d6d (patch)
tree561025af63fc8fbe7a4941cb9c7a7c9f4d1fcfdd /drivers/pci/quirks.c
parent9197979b518573999d52d9e85bce1680682ed85c (diff)
pci: add quirk to disable boot interrupt generation on intel 6300ESB
Add a quirk to disable legacy boot interrupt generation on intel devices that support disabling it. This patch benefited from discussions with Alexander Graf, Torsten Duwe, Ihno Krumreich, Daniel Gollub, Hannes Reinecke. The conclusions we drew and the patch itself are the authors' responsibility alone. Signed-off-by: Stefan Assmann <sassmann@suse.de> Signed-off-by: Olaf Dabrunz <od@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r--drivers/pci/quirks.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 338a3f94b4d4..eb97564316d0 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1363,6 +1363,36 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1363DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 1363DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1364DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 1364DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1365 1365
1366#ifdef CONFIG_X86_IO_APIC
1367/*
1368 * On some chipsets we can disable the generation of legacy INTx boot
1369 * interrupts.
1370 */
1371
1372/*
1373 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1374 * 300641-004US, section 5.7.3.
1375 */
1376#define INTEL_6300_IOAPIC_ABAR 0x40
1377#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1378
1379static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1380{
1381 u16 pci_config_word;
1382
1383 if (noioapicquirk)
1384 return;
1385
1386 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1387 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1388 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1389
1390 printk(KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n",
1391 dev->vendor, dev->device);
1392}
1393DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1394#endif /* CONFIG_X86_IO_APIC */
1395
1366/* 1396/*
1367 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 1397 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1368 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1398 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.