PCI: quirks: fix the festering mess that claims to handle IDE quirks

The number of permutations of crap we do is amazing and almost all of it
has the wrong effect in 2.6.

At the heart of this is the PCI SFF magic which says that compatibility
mode PCI IDE controllers use ISA IRQ routing and hard coded addresses
not the BAR values. The old quirks variously clears them, sets them,
adjusts them and then IDE ignores the result.

In order to drive all this garbage out and to do it portably we need to
handle the SFF rules directly and properly. Because we know the device
BAR 0-3 are not used in compatibility mode we load them with the values
that are implied (and indeed which many controllers actually
thoughtfully put there in this mode anyway).

This removes special cases in the IDE layer and libata which now knows
that bar 0/1/2/3 always contain the correct address. It means our
resource allocation map is accurate from boot, not "mostly accurate"
after ide is loaded, and it shoots lots of code. There is also lots more
code and magic constant knowledge to shoot once this is in and settled.

Been in my test tree for a while both with drivers/ide and with libata.
Wants some -mm shakedown in case I've missed something dumb or there are
corner cases lurking.

Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 27 insertions, 0 deletions

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index e159d6604494..0eeac60042b3 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -679,6 +679,33 @@ static int pci_setup_device(struct pci_dev * dev)
                 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
                 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
                 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
+
+                /*
+                 *      Do the ugly legacy mode stuff here rather than broken chip
+                 *      quirk code. Legacy mode ATA controllers have fixed
+                 *      addresses. These are not always echoed in BAR0-3, and
+                 *      BAR0-3 in a few cases contain junk!
+                 */
+                if (class == PCI_CLASS_STORAGE_IDE) {
+                        u8 progif;
+                        pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
+                        if ((progif & 1) == 0) {
+                                dev->resource[0].start = 0x1F0;
+                                dev->resource[0].end = 0x1F7;
+                                dev->resource[0].flags = IORESOURCE_IO;
+                                dev->resource[1].start = 0x3F6;
+                                dev->resource[1].end = 0x3F6;
+                                dev->resource[1].flags = IORESOURCE_IO;
+                        }
+                        if ((progif & 4) == 0) {
+                                dev->resource[2].start = 0x170;
+                                dev->resource[2].end = 0x177;
+                                dev->resource[2].flags = IORESOURCE_IO;
+                                dev->resource[3].start = 0x376;
+                                dev->resource[3].end = 0x376;
+                                dev->resource[3].flags = IORESOURCE_IO;
+                        }
+                }
                 break;
 
         case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */