PCI/x86: detect host bridge config space size w/o using quirks

Many host bridges support a 4k config space, so check them directy
instead of using quirks to add them.

We only need to do this extra check for host bridges at this point,
because only host bridges are known to have extended address space
without also having a PCI-X/PCI-E caps.  Other devices with this
property could be done with quirks (if there are any).

As a bonus, we can remove the quirks for AMD host bridges with family
10h and 11h since they're not needed any more.

With this patch, we can get correct pci cfg size of new Intel CPUs/IOHs
with host bridges.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Reviewed-by: Matthew Wilcox <willy@linux.intel.com>
Cc: <stable@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

1 files changed, 8 insertions, 1 deletions

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 9e7d642e66b0..579a56c8181f 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -847,6 +847,11 @@ int pci_cfg_space_size(struct pci_dev *dev)
 {
         int pos;
         u32 status;
+        u16 class;
+
+        class = dev->class >> 8;
+        if (class == PCI_CLASS_BRIDGE_HOST)
+                return pci_cfg_space_size_ext(dev);
 
         pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
         if (!pos) {
@@ -936,7 +941,6 @@ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
         dev->multifunction = !!(hdr_type & 0x80);
         dev->vendor = l & 0xffff;
         dev->device = (l >> 16) & 0xffff;
-        dev->cfg_size = pci_cfg_space_size(dev);
         dev->error_state = pci_channel_io_normal;
         set_pcie_port_type(dev);
 
@@ -952,6 +956,9 @@ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
                 return NULL;
         }
 
+        /* need to have dev->class ready */
+        dev->cfg_size = pci_cfg_space_size(dev);
+
         return dev;
 }