Merge branch 'pci/aw-reset-v5' into next

* pci/aw-reset-v5:
  PCI: Add pci_probe_reset_slot() and pci_probe_reset_bus()
  PCI: Remove aer_do_secondary_bus_reset()
  PCI: Tune secondary bus reset timing
  PCI: Wake-up devices before saving config space for reset
  PCI: Add pci_reset_slot() and pci_reset_bus()
  PCI: Split out pci_dev lock/unlock and save/restore
  PCI: Add slot reset option to pci_dev_reset()
  PCI: pciehp: Add reset_slot() method
  PCI: Add hotplug_slot_ops.reset_slot()
  PCI: Add pci_reset_bridge_secondary_bus()

3 files changed, 2 insertions, 36 deletions

diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c
index 76ef634caf6f..0bf82a20a0fb 100644
--- a/drivers/pci/pcie/aer/aerdrv.c
+++ b/drivers/pci/pcie/aer/aerdrv.c
@@ -352,7 +352,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
         reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
         pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);
 
-        aer_do_secondary_bus_reset(dev);
+        pci_reset_bridge_secondary_bus(dev);
         dev_printk(KERN_DEBUG, &dev->dev, "Root Port link has been reset\n");
 
         /* Clear Root Error Status */
diff --git a/drivers/pci/pcie/aer/aerdrv.h b/drivers/pci/pcie/aer/aerdrv.h
index 90ea3e88041f..84420b7c9456 100644
--- a/drivers/pci/pcie/aer/aerdrv.h
+++ b/drivers/pci/pcie/aer/aerdrv.h
@@ -106,7 +106,6 @@ static inline pci_ers_result_t merge_result(enum pci_ers_result orig,
 }
 
 extern struct bus_type pcie_port_bus_type;
-void aer_do_secondary_bus_reset(struct pci_dev *dev);
 int aer_init(struct pcie_device *dev);
 void aer_isr(struct work_struct *work);
 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index 8b68ae59b7b6..85ca36f2136d 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -367,39 +367,6 @@ static pci_ers_result_t broadcast_error_message(struct pci_dev *dev,
 }
 
 /**
- * aer_do_secondary_bus_reset - perform secondary bus reset
- * @dev: pointer to bridge's pci_dev data structure
- *
- * Invoked when performing link reset at Root Port or Downstream Port.
- */
-void aer_do_secondary_bus_reset(struct pci_dev *dev)
-{
-        u16 p2p_ctrl;
-
-        /* Assert Secondary Bus Reset */
-        pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &p2p_ctrl);
-        p2p_ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
-        pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl);
-
-        /*
-         * we should send hot reset message for 2ms to allow it time to
-         * propagate to all downstream ports
-         */
-        msleep(2);
-
-        /* De-assert Secondary Bus Reset */
-        p2p_ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
-        pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl);
-
-        /*
-         * System software must wait for at least 100ms from the end
-         * of a reset of one or more device before it is permitted
-         * to issue Configuration Requests to those devices.
-         */
-        msleep(200);
-}
-
-/**
  * default_reset_link - default reset function
  * @dev: pointer to pci_dev data structure
  *
@@ -408,7 +375,7 @@ void aer_do_secondary_bus_reset(struct pci_dev *dev)
  */
 static pci_ers_result_t default_reset_link(struct pci_dev *dev)
 {
-        aer_do_secondary_bus_reset(dev);
+        pci_reset_bridge_secondary_bus(dev);
         dev_printk(KERN_DEBUG, &dev->dev, "downstream link has been reset\n");
         return PCI_ERS_RESULT_RECOVERED;
 }