Merge commit 'v2.6.38-rc1' into kbuild/packaging

1 files changed, 337 insertions, 86 deletions

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 315fea47e784..b714d787bddd 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/pm.h>
+#include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/spinlock.h>
 #include <linux/string.h>
@@ -19,8 +20,8 @@
 #include <linux/pci-aspm.h>
 #include <linux/pm_wakeup.h>
 #include <linux/interrupt.h>
-#include <asm/dma.h>    /* isa_dma_bridge_buggy */
 #include <linux/device.h>
+#include <linux/pm_runtime.h>
 #include <asm/setup.h>
 #include "pci.h"
 
@@ -29,8 +30,27 @@ const char *pci_power_names[] = {
 };
 EXPORT_SYMBOL_GPL(pci_power_names);
 
+int isa_dma_bridge_buggy;
+EXPORT_SYMBOL(isa_dma_bridge_buggy);
+
+int pci_pci_problems;
+EXPORT_SYMBOL(pci_pci_problems);
+
 unsigned int pci_pm_d3_delay;
 
+static void pci_pme_list_scan(struct work_struct *work);
+
+static LIST_HEAD(pci_pme_list);
+static DEFINE_MUTEX(pci_pme_list_mutex);
+static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
+
+struct pci_pme_device {
+        struct list_head list;
+        struct pci_dev *dev;
+};
+
+#define PME_TIMEOUT 1000 /* How long between PME checks */
+
 static void pci_dev_d3_sleep(struct pci_dev *dev)
 {
         unsigned int delay = dev->d3_delay;
@@ -297,6 +317,49 @@ int pci_find_ext_capability(struct pci_dev *dev, int cap)
 }
 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
 
+/**
+ * pci_bus_find_ext_capability - find an extended capability
+ * @bus:   the PCI bus to query
+ * @devfn: PCI device to query
+ * @cap:   capability code
+ *
+ * Like pci_find_ext_capability() but works for pci devices that do not have a
+ * pci_dev structure set up yet.
+ *
+ * Returns the address of the requested capability structure within the
+ * device's PCI configuration space or 0 in case the device does not
+ * support it.
+ */
+int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
+                                int cap)
+{
+        u32 header;
+        int ttl;
+        int pos = PCI_CFG_SPACE_SIZE;
+
+        /* minimum 8 bytes per capability */
+        ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
+
+        if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
+                return 0;
+        if (header == 0xffffffff || header == 0)
+                return 0;
+
+        while (ttl-- > 0) {
+                if (PCI_EXT_CAP_ID(header) == cap)
+                        return pos;
+
+                pos = PCI_EXT_CAP_NEXT(header);
+                if (pos < PCI_CFG_SPACE_SIZE)
+                        break;
+
+                if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
+                        break;
+        }
+
+        return 0;
+}
+
 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
 {
         int rc, ttl = PCI_FIND_CAP_TTL;
@@ -380,10 +443,9 @@ pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
 {
         const struct pci_bus *bus = dev->bus;
         int i;
-        struct resource *best = NULL;
+        struct resource *best = NULL, *r;
 
-        for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
-                struct resource *r = bus->resource[i];
+        pci_bus_for_each_resource(bus, r, i) {
                 if (!r)
                         continue;
                 if (res->start && !(res->start >= r->start && res->end <= r->end))
@@ -457,6 +519,12 @@ static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
                         pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
 }
 
+static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
+{
+        return pci_platform_pm ?
+                        pci_platform_pm->run_wake(dev, enable) : -ENODEV;
+}
+
 /**
  * pci_raw_set_power_state - Use PCI PM registers to set the power state of
  *                           given PCI device
@@ -624,7 +692,7 @@ static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
  */
 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
 {
-        return state > PCI_D0 ?
+        return state >= PCI_D0 ?
                         pci_platform_power_transition(dev, state) : -EINVAL;
 }
 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
@@ -661,10 +729,6 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
                  */
                 return 0;
 
-        /* Check if we're already there */
-        if (dev->current_state == state)
-                return 0;
-
         __pci_start_power_transition(dev, state);
 
         /* This device is quirked not to be put into D3, so
@@ -873,14 +937,13 @@ pci_save_state(struct pci_dev *dev)
  * pci_restore_state - Restore the saved state of a PCI device
  * @dev: - PCI device that we're dealing with
  */
-int 
-pci_restore_state(struct pci_dev *dev)
+void pci_restore_state(struct pci_dev *dev)
 {
         int i;
         u32 val;
 
         if (!dev->state_saved)
-                return 0;
+                return;
 
         /* PCI Express register must be restored first */
         pci_restore_pcie_state(dev);
@@ -904,8 +967,6 @@ pci_restore_state(struct pci_dev *dev)
         pci_restore_iov_state(dev);
 
         dev->state_saved = false;
-
-        return 0;
 }
 
 static int do_pci_enable_device(struct pci_dev *dev, int bars)
@@ -943,6 +1004,18 @@ static int __pci_enable_device_flags(struct pci_dev *dev,
         int err;
         int i, bars = 0;
 
+        /*
+         * Power state could be unknown at this point, either due to a fresh
+         * boot or a device removal call.  So get the current power state
+         * so that things like MSI message writing will behave as expected
+         * (e.g. if the device really is in D0 at enable time).
+         */
+        if (dev->pm_cap) {
+                u16 pmcsr;
+                pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
+                dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
+        }
+
         if (atomic_add_return(1, &dev->enable_cnt) > 1)
                 return 0;               /* already enabled */
 
@@ -1142,7 +1215,7 @@ void pci_disable_enabled_device(struct pci_dev *dev)
  * anymore.  This only involves disabling PCI bus-mastering, if active.
  *
  * Note we don't actually disable the device until all callers of
- * pci_device_enable() have called pci_device_disable().
+ * pci_enable_device() have called pci_disable_device().
  */
 void
 pci_disable_device(struct pci_dev *dev)
@@ -1190,6 +1263,68 @@ int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
 }
 
 /**
+ * pci_check_pme_status - Check if given device has generated PME.
+ * @dev: Device to check.
+ *
+ * Check the PME status of the device and if set, clear it and clear PME enable
+ * (if set).  Return 'true' if PME status and PME enable were both set or
+ * 'false' otherwise.
+ */
+bool pci_check_pme_status(struct pci_dev *dev)
+{
+        int pmcsr_pos;
+        u16 pmcsr;
+        bool ret = false;
+
+        if (!dev->pm_cap)
+                return false;
+
+        pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
+        pci_read_config_word(dev, pmcsr_pos, &pmcsr);
+        if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
+                return false;
+
+        /* Clear PME status. */
+        pmcsr |= PCI_PM_CTRL_PME_STATUS;
+        if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
+                /* Disable PME to avoid interrupt flood. */
+                pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
+                ret = true;
+        }
+
+        pci_write_config_word(dev, pmcsr_pos, pmcsr);
+
+        return ret;
+}
+
+/**
+ * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
+ * @dev: Device to handle.
+ * @ign: Ignored.
+ *
+ * Check if @dev has generated PME and queue a resume request for it in that
+ * case.
+ */
+static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
+{
+        if (pci_check_pme_status(dev)) {
+                pci_wakeup_event(dev);
+                pm_request_resume(&dev->dev);
+        }
+        return 0;
+}
+
+/**
+ * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
+ * @bus: Top bus of the subtree to walk.
+ */
+void pci_pme_wakeup_bus(struct pci_bus *bus)
+{
+        if (bus)
+                pci_walk_bus(bus, pci_pme_wakeup, NULL);
+}
+
+/**
  * pci_pme_capable - check the capability of PCI device to generate PME#
  * @dev: PCI device to handle.
  * @state: PCI state from which device will issue PME#.
@@ -1202,6 +1337,32 @@ bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
         return !!(dev->pme_support & (1 << state));
 }
 
+static void pci_pme_list_scan(struct work_struct *work)
+{
+        struct pci_pme_device *pme_dev;
+
+        mutex_lock(&pci_pme_list_mutex);
+        if (!list_empty(&pci_pme_list)) {
+                list_for_each_entry(pme_dev, &pci_pme_list, list)
+                        pci_pme_wakeup(pme_dev->dev, NULL);
+                schedule_delayed_work(&pci_pme_work, msecs_to_jiffies(PME_TIMEOUT));
+        }
+        mutex_unlock(&pci_pme_list_mutex);
+}
+
+/**
+ * pci_external_pme - is a device an external PCI PME source?
+ * @dev: PCI device to check
+ *
+ */
+
+static bool pci_external_pme(struct pci_dev *dev)
+{
+        if (pci_is_pcie(dev) || dev->bus->number == 0)
+                return false;
+        return true;
+}
+
 /**
  * pci_pme_active - enable or disable PCI device's PME# function
  * @dev: PCI device to handle.
@@ -1225,14 +1386,53 @@ void pci_pme_active(struct pci_dev *dev, bool enable)
 
         pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
 
+        /* PCI (as opposed to PCIe) PME requires that the device have
+           its PME# line hooked up correctly. Not all hardware vendors
+           do this, so the PME never gets delivered and the device
+           remains asleep. The easiest way around this is to
+           periodically walk the list of suspended devices and check
+           whether any have their PME flag set. The assumption is that
+           we'll wake up often enough anyway that this won't be a huge
+           hit, and the power savings from the devices will still be a
+           win. */
+
+        if (pci_external_pme(dev)) {
+                struct pci_pme_device *pme_dev;
+                if (enable) {
+                        pme_dev = kmalloc(sizeof(struct pci_pme_device),
+                                          GFP_KERNEL);
+                        if (!pme_dev)
+                                goto out;
+                        pme_dev->dev = dev;
+                        mutex_lock(&pci_pme_list_mutex);
+                        list_add(&pme_dev->list, &pci_pme_list);
+                        if (list_is_singular(&pci_pme_list))
+                                schedule_delayed_work(&pci_pme_work,
+                                                      msecs_to_jiffies(PME_TIMEOUT));
+                        mutex_unlock(&pci_pme_list_mutex);
+                } else {
+                        mutex_lock(&pci_pme_list_mutex);
+                        list_for_each_entry(pme_dev, &pci_pme_list, list) {
+                                if (pme_dev->dev == dev) {
+                                        list_del(&pme_dev->list);
+                                        kfree(pme_dev);
+                                        break;
+                                }
+                        }
+                        mutex_unlock(&pci_pme_list_mutex);
+                }
+        }
+
+out:
         dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
                         enable ? "enabled" : "disabled");
 }
 
 /**
- * pci_enable_wake - enable PCI device as wakeup event source
+ * __pci_enable_wake - enable PCI device as wakeup event source
  * @dev: PCI device affected
  * @state: PCI state from which device will issue wakeup events
+ * @runtime: True if the events are to be generated at run time
  * @enable: True to enable event generation; false to disable
  *
  * This enables the device as a wakeup event source, or disables it.
@@ -1248,11 +1448,12 @@ void pci_pme_active(struct pci_dev *dev, bool enable)
  * Error code depending on the platform is returned if both the platform and
  * the native mechanism fail to enable the generation of wake-up events
  */
-int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
+int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
+                      bool runtime, bool enable)
 {
         int ret = 0;
 
-        if (enable && !device_may_wakeup(&dev->dev))
+        if (enable && !runtime && !device_may_wakeup(&dev->dev))
                 return -EINVAL;
 
         /* Don't do the same thing twice in a row for one device. */
@@ -1272,19 +1473,24 @@ int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
                         pci_pme_active(dev, true);
                 else
                         ret = 1;
-                error = platform_pci_sleep_wake(dev, true);
+                error = runtime ? platform_pci_run_wake(dev, true) :
+                                        platform_pci_sleep_wake(dev, true);
                 if (ret)
                         ret = error;
                 if (!ret)
                         dev->wakeup_prepared = true;
         } else {
-                platform_pci_sleep_wake(dev, false);
+                if (runtime)
+                        platform_pci_run_wake(dev, false);
+                else
+                        platform_pci_sleep_wake(dev, false);
                 pci_pme_active(dev, false);
                 dev->wakeup_prepared = false;
         }
 
         return ret;
 }
+EXPORT_SYMBOL(__pci_enable_wake);
 
 /**
  * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
@@ -1385,7 +1591,7 @@ int pci_prepare_to_sleep(struct pci_dev *dev)
  * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
  * @dev: Device to handle.
  *
- * Disable device's sytem wake-up capability and put it into D0.
+ * Disable device's system wake-up capability and put it into D0.
  */
 int pci_back_from_sleep(struct pci_dev *dev)
 {
@@ -1394,6 +1600,66 @@ int pci_back_from_sleep(struct pci_dev *dev)
 }
 
 /**
+ * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
+ * @dev: PCI device being suspended.
+ *
+ * Prepare @dev to generate wake-up events at run time and put it into a low
+ * power state.
+ */
+int pci_finish_runtime_suspend(struct pci_dev *dev)
+{
+        pci_power_t target_state = pci_target_state(dev);
+        int error;
+
+        if (target_state == PCI_POWER_ERROR)
+                return -EIO;
+
+        __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
+
+        error = pci_set_power_state(dev, target_state);
+
+        if (error)
+                __pci_enable_wake(dev, target_state, true, false);
+
+        return error;
+}
+
+/**
+ * pci_dev_run_wake - Check if device can generate run-time wake-up events.
+ * @dev: Device to check.
+ *
+ * Return true if the device itself is cabable of generating wake-up events
+ * (through the platform or using the native PCIe PME) or if the device supports
+ * PME and one of its upstream bridges can generate wake-up events.
+ */
+bool pci_dev_run_wake(struct pci_dev *dev)
+{
+        struct pci_bus *bus = dev->bus;
+
+        if (device_run_wake(&dev->dev))
+                return true;
+
+        if (!dev->pme_support)
+                return false;
+
+        while (bus->parent) {
+                struct pci_dev *bridge = bus->self;
+
+                if (device_run_wake(&bridge->dev))
+                        return true;
+
+                bus = bus->parent;
+        }
+
+        /* We have reached the root bus. */
+        if (bus->bridge)
+                return device_run_wake(bus->bridge);
+
+        return false;
+}
+EXPORT_SYMBOL_GPL(pci_dev_run_wake);
+
+/**
  * pci_pm_init - Initialize PM functions of given PCI device
  * @dev: PCI device to handle.
  */
@@ -1402,7 +1668,10 @@ void pci_pm_init(struct pci_dev *dev)
         int pm;
         u16 pmc;
 
+        pm_runtime_forbid(&dev->dev);
+        device_enable_async_suspend(&dev->dev);
         dev->wakeup_prepared = false;
+
         dev->pm_cap = 0;
 
         /* find PCI PM capability in list */
@@ -1450,7 +1719,6 @@ void pci_pm_init(struct pci_dev *dev)
                  * let the user space enable it to wake up the system as needed.
                  */
                 device_set_wakeup_capable(&dev->dev, true);
-                device_set_wakeup_enable(&dev->dev, false);
                 /* Disable the PME# generation functionality */
                 pci_pme_active(dev, false);
         } else {
@@ -1474,7 +1742,6 @@ void platform_pci_wakeup_init(struct pci_dev *dev)
                 return;
 
         device_set_wakeup_capable(&dev->dev, true);
-        device_set_wakeup_enable(&dev->dev, false);
         platform_pci_sleep_wake(dev, false);
 }
 
@@ -2113,51 +2380,19 @@ void pci_msi_off(struct pci_dev *dev)
                 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
         }
 }
+EXPORT_SYMBOL_GPL(pci_msi_off);
 
-#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
-/*
- * These can be overridden by arch-specific implementations
- */
-int
-pci_set_dma_mask(struct pci_dev *dev, u64 mask)
-{
-        if (!pci_dma_supported(dev, mask))
-                return -EIO;
-
-        dev->dma_mask = mask;
-        dev_dbg(&dev->dev, "using %dbit DMA mask\n", fls64(mask));
-
-        return 0;
-}
-    
-int
-pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
-{
-        if (!pci_dma_supported(dev, mask))
-                return -EIO;
-
-        dev->dev.coherent_dma_mask = mask;
-        dev_dbg(&dev->dev, "using %dbit consistent DMA mask\n", fls64(mask));
-
-        return 0;
-}
-#endif
-
-#ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
 {
         return dma_set_max_seg_size(&dev->dev, size);
 }
 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
-#endif
 
-#ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
 {
         return dma_set_seg_boundary(&dev->dev, mask);
 }
 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
-#endif
 
 static int pcie_flr(struct pci_dev *dev, int probe)
 {
@@ -2304,7 +2539,7 @@ static int pci_dev_reset(struct pci_dev *dev, int probe)
         if (!probe) {
                 pci_block_user_cfg_access(dev);
                 /* block PM suspend, driver probe, etc. */
-                down(&dev->dev.sem);
+                device_lock(&dev->dev);
         }
 
         rc = pci_dev_specific_reset(dev, probe);
@@ -2326,7 +2561,7 @@ static int pci_dev_reset(struct pci_dev *dev, int probe)
         rc = pci_parent_bus_reset(dev, probe);
 done:
         if (!probe) {
-                up(&dev->dev.sem);
+                device_unlock(&dev->dev);
                 pci_unblock_user_cfg_access(dev);
         }
 
@@ -2421,18 +2656,17 @@ EXPORT_SYMBOL_GPL(pci_reset_function);
  */
 int pcix_get_max_mmrbc(struct pci_dev *dev)
 {
-        int err, cap;
+        int cap;
         u32 stat;
 
         cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
         if (!cap)
                 return -EINVAL;
 
-        err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
-        if (err)
+        if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
                 return -EINVAL;
 
-        return (stat & PCI_X_STATUS_MAX_READ) >> 12;
+        return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
 }
 EXPORT_SYMBOL(pcix_get_max_mmrbc);
 
@@ -2445,18 +2679,17 @@ EXPORT_SYMBOL(pcix_get_max_mmrbc);
  */
 int pcix_get_mmrbc(struct pci_dev *dev)
 {
-        int ret, cap;
-        u32 cmd;
+        int cap;
+        u16 cmd;
 
         cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
         if (!cap)
                 return -EINVAL;
 
-        ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
-        if (!ret)
-                ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
+        if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
+                return -EINVAL;
 
-        return ret;
+        return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
 }
 EXPORT_SYMBOL(pcix_get_mmrbc);
 
@@ -2471,28 +2704,27 @@ EXPORT_SYMBOL(pcix_get_mmrbc);
  */
 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
 {
-        int cap, err = -EINVAL;
-        u32 stat, cmd, v, o;
+        int cap;
+        u32 stat, v, o;
+        u16 cmd;
 
         if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
-                goto out;
+                return -EINVAL;
 
         v = ffs(mmrbc) - 10;
 
         cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
         if (!cap)
-                goto out;
+                return -EINVAL;
 
-        err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
-        if (err)
-                goto out;
+        if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
+                return -EINVAL;
 
         if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
                 return -E2BIG;
 
-        err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
-        if (err)
-                goto out;
+        if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
+                return -EINVAL;
 
         o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
         if (o != v) {
@@ -2502,10 +2734,10 @@ int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
 
                 cmd &= ~PCI_X_CMD_MAX_READ;
                 cmd |= v << 2;
-                err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
+                if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
+                        return -EIO;
         }
-out:
-        return err;
+        return 0;
 }
 EXPORT_SYMBOL(pcix_set_mmrbc);
 
@@ -2527,7 +2759,7 @@ int pcie_get_readrq(struct pci_dev *dev)
 
         ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
         if (!ret)
-        ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
+                ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
 
         return ret;
 }
@@ -2615,6 +2847,23 @@ int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
         return 0;
 }
 
+/* Some architectures require additional programming to enable VGA */
+static arch_set_vga_state_t arch_set_vga_state;
+
+void __init pci_register_set_vga_state(arch_set_vga_state_t func)
+{
+        arch_set_vga_state = func;      /* NULL disables */
+}
+
+static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
+                      unsigned int command_bits, bool change_bridge)
+{
+        if (arch_set_vga_state)
+                return arch_set_vga_state(dev, decode, command_bits,
+                                                change_bridge);
+        return 0;
+}
+
 /**
  * pci_set_vga_state - set VGA decode state on device and parents if requested
  * @dev: the PCI device
@@ -2628,9 +2877,15 @@ int pci_set_vga_state(struct pci_dev *dev, bool decode,
         struct pci_bus *bus;
         struct pci_dev *bridge;
         u16 cmd;
+        int rc;
 
         WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
 
+        /* ARCH specific VGA enables */
+        rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge);
+        if (rc)
+                return rc;
+
         pci_read_config_word(dev, PCI_COMMAND, &cmd);
         if (decode == true)
                 cmd |= command_bits;
@@ -2860,8 +3115,6 @@ EXPORT_SYMBOL(pci_set_mwi);
 EXPORT_SYMBOL(pci_try_set_mwi);
 EXPORT_SYMBOL(pci_clear_mwi);
 EXPORT_SYMBOL_GPL(pci_intx);
-EXPORT_SYMBOL(pci_set_dma_mask);
-EXPORT_SYMBOL(pci_set_consistent_dma_mask);
 EXPORT_SYMBOL(pci_assign_resource);
 EXPORT_SYMBOL(pci_find_parent_resource);
 EXPORT_SYMBOL(pci_select_bars);
@@ -2871,10 +3124,8 @@ EXPORT_SYMBOL(pci_save_state);
 EXPORT_SYMBOL(pci_restore_state);
 EXPORT_SYMBOL(pci_pme_capable);
 EXPORT_SYMBOL(pci_pme_active);
-EXPORT_SYMBOL(pci_enable_wake);
 EXPORT_SYMBOL(pci_wake_from_d3);
 EXPORT_SYMBOL(pci_target_state);
 EXPORT_SYMBOL(pci_prepare_to_sleep);
 EXPORT_SYMBOL(pci_back_from_sleep);
 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
-