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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/pci/pci.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/pci/pci.c')
-rw-r--r--drivers/pci/pci.c837
1 files changed, 837 insertions, 0 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
new file mode 100644
index 000000000000..bfbff8335268
--- /dev/null
+++ b/drivers/pci/pci.c
@@ -0,0 +1,837 @@
1/*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 */
11
12#include <linux/kernel.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
18#include <asm/dma.h> /* isa_dma_bridge_buggy */
19
20
21/**
22 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
23 * @bus: pointer to PCI bus structure to search
24 *
25 * Given a PCI bus, returns the highest PCI bus number present in the set
26 * including the given PCI bus and its list of child PCI buses.
27 */
28unsigned char __devinit
29pci_bus_max_busnr(struct pci_bus* bus)
30{
31 struct list_head *tmp;
32 unsigned char max, n;
33
34 max = bus->number;
35 list_for_each(tmp, &bus->children) {
36 n = pci_bus_max_busnr(pci_bus_b(tmp));
37 if(n > max)
38 max = n;
39 }
40 return max;
41}
42
43/**
44 * pci_max_busnr - returns maximum PCI bus number
45 *
46 * Returns the highest PCI bus number present in the system global list of
47 * PCI buses.
48 */
49unsigned char __devinit
50pci_max_busnr(void)
51{
52 struct pci_bus *bus = NULL;
53 unsigned char max, n;
54
55 max = 0;
56 while ((bus = pci_find_next_bus(bus)) != NULL) {
57 n = pci_bus_max_busnr(bus);
58 if(n > max)
59 max = n;
60 }
61 return max;
62}
63
64static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap)
65{
66 u16 status;
67 u8 pos, id;
68 int ttl = 48;
69
70 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
71 if (!(status & PCI_STATUS_CAP_LIST))
72 return 0;
73
74 switch (hdr_type) {
75 case PCI_HEADER_TYPE_NORMAL:
76 case PCI_HEADER_TYPE_BRIDGE:
77 pci_bus_read_config_byte(bus, devfn, PCI_CAPABILITY_LIST, &pos);
78 break;
79 case PCI_HEADER_TYPE_CARDBUS:
80 pci_bus_read_config_byte(bus, devfn, PCI_CB_CAPABILITY_LIST, &pos);
81 break;
82 default:
83 return 0;
84 }
85 while (ttl-- && pos >= 0x40) {
86 pos &= ~3;
87 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, &id);
88 if (id == 0xff)
89 break;
90 if (id == cap)
91 return pos;
92 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_NEXT, &pos);
93 }
94 return 0;
95}
96
97/**
98 * pci_find_capability - query for devices' capabilities
99 * @dev: PCI device to query
100 * @cap: capability code
101 *
102 * Tell if a device supports a given PCI capability.
103 * Returns the address of the requested capability structure within the
104 * device's PCI configuration space or 0 in case the device does not
105 * support it. Possible values for @cap:
106 *
107 * %PCI_CAP_ID_PM Power Management
108 * %PCI_CAP_ID_AGP Accelerated Graphics Port
109 * %PCI_CAP_ID_VPD Vital Product Data
110 * %PCI_CAP_ID_SLOTID Slot Identification
111 * %PCI_CAP_ID_MSI Message Signalled Interrupts
112 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
113 * %PCI_CAP_ID_PCIX PCI-X
114 * %PCI_CAP_ID_EXP PCI Express
115 */
116int pci_find_capability(struct pci_dev *dev, int cap)
117{
118 return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap);
119}
120
121/**
122 * pci_bus_find_capability - query for devices' capabilities
123 * @bus: the PCI bus to query
124 * @devfn: PCI device to query
125 * @cap: capability code
126 *
127 * Like pci_find_capability() but works for pci devices that do not have a
128 * pci_dev structure set up yet.
129 *
130 * Returns the address of the requested capability structure within the
131 * device's PCI configuration space or 0 in case the device does not
132 * support it.
133 */
134int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
135{
136 u8 hdr_type;
137
138 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
139
140 return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap);
141}
142
143/**
144 * pci_find_ext_capability - Find an extended capability
145 * @dev: PCI device to query
146 * @cap: capability code
147 *
148 * Returns the address of the requested extended capability structure
149 * within the device's PCI configuration space or 0 if the device does
150 * not support it. Possible values for @cap:
151 *
152 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
153 * %PCI_EXT_CAP_ID_VC Virtual Channel
154 * %PCI_EXT_CAP_ID_DSN Device Serial Number
155 * %PCI_EXT_CAP_ID_PWR Power Budgeting
156 */
157int pci_find_ext_capability(struct pci_dev *dev, int cap)
158{
159 u32 header;
160 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
161 int pos = 0x100;
162
163 if (dev->cfg_size <= 256)
164 return 0;
165
166 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
167 return 0;
168
169 /*
170 * If we have no capabilities, this is indicated by cap ID,
171 * cap version and next pointer all being 0.
172 */
173 if (header == 0)
174 return 0;
175
176 while (ttl-- > 0) {
177 if (PCI_EXT_CAP_ID(header) == cap)
178 return pos;
179
180 pos = PCI_EXT_CAP_NEXT(header);
181 if (pos < 0x100)
182 break;
183
184 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
185 break;
186 }
187
188 return 0;
189}
190
191/**
192 * pci_find_parent_resource - return resource region of parent bus of given region
193 * @dev: PCI device structure contains resources to be searched
194 * @res: child resource record for which parent is sought
195 *
196 * For given resource region of given device, return the resource
197 * region of parent bus the given region is contained in or where
198 * it should be allocated from.
199 */
200struct resource *
201pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
202{
203 const struct pci_bus *bus = dev->bus;
204 int i;
205 struct resource *best = NULL;
206
207 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
208 struct resource *r = bus->resource[i];
209 if (!r)
210 continue;
211 if (res->start && !(res->start >= r->start && res->end <= r->end))
212 continue; /* Not contained */
213 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
214 continue; /* Wrong type */
215 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
216 return r; /* Exact match */
217 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
218 best = r; /* Approximating prefetchable by non-prefetchable */
219 }
220 return best;
221}
222
223/**
224 * pci_set_power_state - Set the power state of a PCI device
225 * @dev: PCI device to be suspended
226 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
227 *
228 * Transition a device to a new power state, using the Power Management
229 * Capabilities in the device's config space.
230 *
231 * RETURN VALUE:
232 * -EINVAL if trying to enter a lower state than we're already in.
233 * 0 if we're already in the requested state.
234 * -EIO if device does not support PCI PM.
235 * 0 if we can successfully change the power state.
236 */
237
238int
239pci_set_power_state(struct pci_dev *dev, pci_power_t state)
240{
241 int pm;
242 u16 pmcsr, pmc;
243
244 /* bound the state we're entering */
245 if (state > PCI_D3hot)
246 state = PCI_D3hot;
247
248 /* Validate current state:
249 * Can enter D0 from any state, but if we can only go deeper
250 * to sleep if we're already in a low power state
251 */
252 if (state != PCI_D0 && dev->current_state > state)
253 return -EINVAL;
254 else if (dev->current_state == state)
255 return 0; /* we're already there */
256
257 /* find PCI PM capability in list */
258 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
259
260 /* abort if the device doesn't support PM capabilities */
261 if (!pm)
262 return -EIO;
263
264 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
265 if ((pmc & PCI_PM_CAP_VER_MASK) > 2) {
266 printk(KERN_DEBUG
267 "PCI: %s has unsupported PM cap regs version (%u)\n",
268 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
269 return -EIO;
270 }
271
272 /* check if this device supports the desired state */
273 if (state == PCI_D1 || state == PCI_D2) {
274 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
275 return -EIO;
276 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
277 return -EIO;
278 }
279
280 /* If we're in D3, force entire word to 0.
281 * This doesn't affect PME_Status, disables PME_En, and
282 * sets PowerState to 0.
283 */
284 if (dev->current_state >= PCI_D3hot)
285 pmcsr = 0;
286 else {
287 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
288 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
289 pmcsr |= state;
290 }
291
292 /* enter specified state */
293 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
294
295 /* Mandatory power management transition delays */
296 /* see PCI PM 1.1 5.6.1 table 18 */
297 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
298 msleep(10);
299 else if (state == PCI_D2 || dev->current_state == PCI_D2)
300 udelay(200);
301 dev->current_state = state;
302
303 return 0;
304}
305
306/**
307 * pci_choose_state - Choose the power state of a PCI device
308 * @dev: PCI device to be suspended
309 * @state: target sleep state for the whole system. This is the value
310 * that is passed to suspend() function.
311 *
312 * Returns PCI power state suitable for given device and given system
313 * message.
314 */
315
316pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
317{
318 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
319 return PCI_D0;
320
321 switch (state) {
322 case 0: return PCI_D0;
323 case 3: return PCI_D3hot;
324 default:
325 printk("They asked me for state %d\n", state);
326 BUG();
327 }
328 return PCI_D0;
329}
330
331EXPORT_SYMBOL(pci_choose_state);
332
333/**
334 * pci_save_state - save the PCI configuration space of a device before suspending
335 * @dev: - PCI device that we're dealing with
336 * @buffer: - buffer to hold config space context
337 *
338 * @buffer must be large enough to hold the entire PCI 2.2 config space
339 * (>= 64 bytes).
340 */
341int
342pci_save_state(struct pci_dev *dev)
343{
344 int i;
345 /* XXX: 100% dword access ok here? */
346 for (i = 0; i < 16; i++)
347 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
348 return 0;
349}
350
351/**
352 * pci_restore_state - Restore the saved state of a PCI device
353 * @dev: - PCI device that we're dealing with
354 * @buffer: - saved PCI config space
355 *
356 */
357int
358pci_restore_state(struct pci_dev *dev)
359{
360 int i;
361
362 for (i = 0; i < 16; i++)
363 pci_write_config_dword(dev,i * 4, dev->saved_config_space[i]);
364 return 0;
365}
366
367/**
368 * pci_enable_device_bars - Initialize some of a device for use
369 * @dev: PCI device to be initialized
370 * @bars: bitmask of BAR's that must be configured
371 *
372 * Initialize device before it's used by a driver. Ask low-level code
373 * to enable selected I/O and memory resources. Wake up the device if it
374 * was suspended. Beware, this function can fail.
375 */
376
377int
378pci_enable_device_bars(struct pci_dev *dev, int bars)
379{
380 int err;
381
382 pci_set_power_state(dev, PCI_D0);
383 if ((err = pcibios_enable_device(dev, bars)) < 0)
384 return err;
385 return 0;
386}
387
388/**
389 * pci_enable_device - Initialize device before it's used by a driver.
390 * @dev: PCI device to be initialized
391 *
392 * Initialize device before it's used by a driver. Ask low-level code
393 * to enable I/O and memory. Wake up the device if it was suspended.
394 * Beware, this function can fail.
395 */
396int
397pci_enable_device(struct pci_dev *dev)
398{
399 int err;
400
401 dev->is_enabled = 1;
402 if ((err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1)))
403 return err;
404 pci_fixup_device(pci_fixup_enable, dev);
405 return 0;
406}
407
408/**
409 * pcibios_disable_device - disable arch specific PCI resources for device dev
410 * @dev: the PCI device to disable
411 *
412 * Disables architecture specific PCI resources for the device. This
413 * is the default implementation. Architecture implementations can
414 * override this.
415 */
416void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
417
418/**
419 * pci_disable_device - Disable PCI device after use
420 * @dev: PCI device to be disabled
421 *
422 * Signal to the system that the PCI device is not in use by the system
423 * anymore. This only involves disabling PCI bus-mastering, if active.
424 */
425void
426pci_disable_device(struct pci_dev *dev)
427{
428 u16 pci_command;
429
430 dev->is_enabled = 0;
431 dev->is_busmaster = 0;
432
433 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
434 if (pci_command & PCI_COMMAND_MASTER) {
435 pci_command &= ~PCI_COMMAND_MASTER;
436 pci_write_config_word(dev, PCI_COMMAND, pci_command);
437 }
438
439 pcibios_disable_device(dev);
440}
441
442/**
443 * pci_enable_wake - enable device to generate PME# when suspended
444 * @dev: - PCI device to operate on
445 * @state: - Current state of device.
446 * @enable: - Flag to enable or disable generation
447 *
448 * Set the bits in the device's PM Capabilities to generate PME# when
449 * the system is suspended.
450 *
451 * -EIO is returned if device doesn't have PM Capabilities.
452 * -EINVAL is returned if device supports it, but can't generate wake events.
453 * 0 if operation is successful.
454 *
455 */
456int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
457{
458 int pm;
459 u16 value;
460
461 /* find PCI PM capability in list */
462 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
463
464 /* If device doesn't support PM Capabilities, but request is to disable
465 * wake events, it's a nop; otherwise fail */
466 if (!pm)
467 return enable ? -EIO : 0;
468
469 /* Check device's ability to generate PME# */
470 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
471
472 value &= PCI_PM_CAP_PME_MASK;
473 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
474
475 /* Check if it can generate PME# from requested state. */
476 if (!value || !(value & (1 << state)))
477 return enable ? -EINVAL : 0;
478
479 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
480
481 /* Clear PME_Status by writing 1 to it and enable PME# */
482 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
483
484 if (!enable)
485 value &= ~PCI_PM_CTRL_PME_ENABLE;
486
487 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
488
489 return 0;
490}
491
492int
493pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
494{
495 u8 pin;
496
497 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
498 if (!pin)
499 return -1;
500 pin--;
501 while (dev->bus->self) {
502 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
503 dev = dev->bus->self;
504 }
505 *bridge = dev;
506 return pin;
507}
508
509/**
510 * pci_release_region - Release a PCI bar
511 * @pdev: PCI device whose resources were previously reserved by pci_request_region
512 * @bar: BAR to release
513 *
514 * Releases the PCI I/O and memory resources previously reserved by a
515 * successful call to pci_request_region. Call this function only
516 * after all use of the PCI regions has ceased.
517 */
518void pci_release_region(struct pci_dev *pdev, int bar)
519{
520 if (pci_resource_len(pdev, bar) == 0)
521 return;
522 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
523 release_region(pci_resource_start(pdev, bar),
524 pci_resource_len(pdev, bar));
525 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
526 release_mem_region(pci_resource_start(pdev, bar),
527 pci_resource_len(pdev, bar));
528}
529
530/**
531 * pci_request_region - Reserved PCI I/O and memory resource
532 * @pdev: PCI device whose resources are to be reserved
533 * @bar: BAR to be reserved
534 * @res_name: Name to be associated with resource.
535 *
536 * Mark the PCI region associated with PCI device @pdev BR @bar as
537 * being reserved by owner @res_name. Do not access any
538 * address inside the PCI regions unless this call returns
539 * successfully.
540 *
541 * Returns 0 on success, or %EBUSY on error. A warning
542 * message is also printed on failure.
543 */
544int pci_request_region(struct pci_dev *pdev, int bar, char *res_name)
545{
546 if (pci_resource_len(pdev, bar) == 0)
547 return 0;
548
549 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
550 if (!request_region(pci_resource_start(pdev, bar),
551 pci_resource_len(pdev, bar), res_name))
552 goto err_out;
553 }
554 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
555 if (!request_mem_region(pci_resource_start(pdev, bar),
556 pci_resource_len(pdev, bar), res_name))
557 goto err_out;
558 }
559
560 return 0;
561
562err_out:
563 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
564 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
565 bar + 1, /* PCI BAR # */
566 pci_resource_len(pdev, bar), pci_resource_start(pdev, bar),
567 pci_name(pdev));
568 return -EBUSY;
569}
570
571
572/**
573 * pci_release_regions - Release reserved PCI I/O and memory resources
574 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
575 *
576 * Releases all PCI I/O and memory resources previously reserved by a
577 * successful call to pci_request_regions. Call this function only
578 * after all use of the PCI regions has ceased.
579 */
580
581void pci_release_regions(struct pci_dev *pdev)
582{
583 int i;
584
585 for (i = 0; i < 6; i++)
586 pci_release_region(pdev, i);
587}
588
589/**
590 * pci_request_regions - Reserved PCI I/O and memory resources
591 * @pdev: PCI device whose resources are to be reserved
592 * @res_name: Name to be associated with resource.
593 *
594 * Mark all PCI regions associated with PCI device @pdev as
595 * being reserved by owner @res_name. Do not access any
596 * address inside the PCI regions unless this call returns
597 * successfully.
598 *
599 * Returns 0 on success, or %EBUSY on error. A warning
600 * message is also printed on failure.
601 */
602int pci_request_regions(struct pci_dev *pdev, char *res_name)
603{
604 int i;
605
606 for (i = 0; i < 6; i++)
607 if(pci_request_region(pdev, i, res_name))
608 goto err_out;
609 return 0;
610
611err_out:
612 while(--i >= 0)
613 pci_release_region(pdev, i);
614
615 return -EBUSY;
616}
617
618/**
619 * pci_set_master - enables bus-mastering for device dev
620 * @dev: the PCI device to enable
621 *
622 * Enables bus-mastering on the device and calls pcibios_set_master()
623 * to do the needed arch specific settings.
624 */
625void
626pci_set_master(struct pci_dev *dev)
627{
628 u16 cmd;
629
630 pci_read_config_word(dev, PCI_COMMAND, &cmd);
631 if (! (cmd & PCI_COMMAND_MASTER)) {
632 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
633 cmd |= PCI_COMMAND_MASTER;
634 pci_write_config_word(dev, PCI_COMMAND, cmd);
635 }
636 dev->is_busmaster = 1;
637 pcibios_set_master(dev);
638}
639
640#ifndef HAVE_ARCH_PCI_MWI
641/* This can be overridden by arch code. */
642u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
643
644/**
645 * pci_generic_prep_mwi - helper function for pci_set_mwi
646 * @dev: the PCI device for which MWI is enabled
647 *
648 * Helper function for generic implementation of pcibios_prep_mwi
649 * function. Originally copied from drivers/net/acenic.c.
650 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
651 *
652 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
653 */
654static int
655pci_generic_prep_mwi(struct pci_dev *dev)
656{
657 u8 cacheline_size;
658
659 if (!pci_cache_line_size)
660 return -EINVAL; /* The system doesn't support MWI. */
661
662 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
663 equal to or multiple of the right value. */
664 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
665 if (cacheline_size >= pci_cache_line_size &&
666 (cacheline_size % pci_cache_line_size) == 0)
667 return 0;
668
669 /* Write the correct value. */
670 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
671 /* Read it back. */
672 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
673 if (cacheline_size == pci_cache_line_size)
674 return 0;
675
676 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
677 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
678
679 return -EINVAL;
680}
681#endif /* !HAVE_ARCH_PCI_MWI */
682
683/**
684 * pci_set_mwi - enables memory-write-invalidate PCI transaction
685 * @dev: the PCI device for which MWI is enabled
686 *
687 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
688 * and then calls @pcibios_set_mwi to do the needed arch specific
689 * operations or a generic mwi-prep function.
690 *
691 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
692 */
693int
694pci_set_mwi(struct pci_dev *dev)
695{
696 int rc;
697 u16 cmd;
698
699#ifdef HAVE_ARCH_PCI_MWI
700 rc = pcibios_prep_mwi(dev);
701#else
702 rc = pci_generic_prep_mwi(dev);
703#endif
704
705 if (rc)
706 return rc;
707
708 pci_read_config_word(dev, PCI_COMMAND, &cmd);
709 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
710 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
711 cmd |= PCI_COMMAND_INVALIDATE;
712 pci_write_config_word(dev, PCI_COMMAND, cmd);
713 }
714
715 return 0;
716}
717
718/**
719 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
720 * @dev: the PCI device to disable
721 *
722 * Disables PCI Memory-Write-Invalidate transaction on the device
723 */
724void
725pci_clear_mwi(struct pci_dev *dev)
726{
727 u16 cmd;
728
729 pci_read_config_word(dev, PCI_COMMAND, &cmd);
730 if (cmd & PCI_COMMAND_INVALIDATE) {
731 cmd &= ~PCI_COMMAND_INVALIDATE;
732 pci_write_config_word(dev, PCI_COMMAND, cmd);
733 }
734}
735
736#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
737/*
738 * These can be overridden by arch-specific implementations
739 */
740int
741pci_set_dma_mask(struct pci_dev *dev, u64 mask)
742{
743 if (!pci_dma_supported(dev, mask))
744 return -EIO;
745
746 dev->dma_mask = mask;
747
748 return 0;
749}
750
751int
752pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask)
753{
754 if (!pci_dac_dma_supported(dev, mask))
755 return -EIO;
756
757 dev->dma_mask = mask;
758
759 return 0;
760}
761
762int
763pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
764{
765 if (!pci_dma_supported(dev, mask))
766 return -EIO;
767
768 dev->dev.coherent_dma_mask = mask;
769
770 return 0;
771}
772#endif
773
774static int __devinit pci_init(void)
775{
776 struct pci_dev *dev = NULL;
777
778 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
779 pci_fixup_device(pci_fixup_final, dev);
780 }
781 return 0;
782}
783
784static int __devinit pci_setup(char *str)
785{
786 while (str) {
787 char *k = strchr(str, ',');
788 if (k)
789 *k++ = 0;
790 if (*str && (str = pcibios_setup(str)) && *str) {
791 /* PCI layer options should be handled here */
792 printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
793 }
794 str = k;
795 }
796 return 1;
797}
798
799device_initcall(pci_init);
800
801__setup("pci=", pci_setup);
802
803#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
804/* FIXME: Some boxes have multiple ISA bridges! */
805struct pci_dev *isa_bridge;
806EXPORT_SYMBOL(isa_bridge);
807#endif
808
809EXPORT_SYMBOL(pci_enable_device_bars);
810EXPORT_SYMBOL(pci_enable_device);
811EXPORT_SYMBOL(pci_disable_device);
812EXPORT_SYMBOL(pci_max_busnr);
813EXPORT_SYMBOL(pci_bus_max_busnr);
814EXPORT_SYMBOL(pci_find_capability);
815EXPORT_SYMBOL(pci_bus_find_capability);
816EXPORT_SYMBOL(pci_release_regions);
817EXPORT_SYMBOL(pci_request_regions);
818EXPORT_SYMBOL(pci_release_region);
819EXPORT_SYMBOL(pci_request_region);
820EXPORT_SYMBOL(pci_set_master);
821EXPORT_SYMBOL(pci_set_mwi);
822EXPORT_SYMBOL(pci_clear_mwi);
823EXPORT_SYMBOL(pci_set_dma_mask);
824EXPORT_SYMBOL(pci_dac_set_dma_mask);
825EXPORT_SYMBOL(pci_set_consistent_dma_mask);
826EXPORT_SYMBOL(pci_assign_resource);
827EXPORT_SYMBOL(pci_find_parent_resource);
828
829EXPORT_SYMBOL(pci_set_power_state);
830EXPORT_SYMBOL(pci_save_state);
831EXPORT_SYMBOL(pci_restore_state);
832EXPORT_SYMBOL(pci_enable_wake);
833
834/* Quirk info */
835
836EXPORT_SYMBOL(isa_dma_bridge_buggy);
837EXPORT_SYMBOL(pci_pci_problems);