Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:
  PCIe AER: prevent AER injection if hardware masks error reporting
  PCI/PM: Use per-device D3 delays
  PCI: Check the node argument passed to cpumask_of_node
  PCI: AER: fix aer inject result in kernel oops
  PCI: pcie portdrv: style cleanup

1 files changed, 15 insertions, 4 deletions

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 0906599ebfde..315fea47e784 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -29,7 +29,17 @@ const char *pci_power_names[] = {
 };
 EXPORT_SYMBOL_GPL(pci_power_names);
 
-unsigned int pci_pm_d3_delay = PCI_PM_D3_WAIT;
+unsigned int pci_pm_d3_delay;
+
+static void pci_dev_d3_sleep(struct pci_dev *dev)
+{
+        unsigned int delay = dev->d3_delay;
+
+        if (delay < pci_pm_d3_delay)
+                delay = pci_pm_d3_delay;
+
+        msleep(delay);
+}
 
 #ifdef CONFIG_PCI_DOMAINS
 int pci_domains_supported = 1;
@@ -522,7 +532,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
         /* Mandatory power management transition delays */
         /* see PCI PM 1.1 5.6.1 table 18 */
         if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
-                msleep(pci_pm_d3_delay);
+                pci_dev_d3_sleep(dev);
         else if (state == PCI_D2 || dev->current_state == PCI_D2)
                 udelay(PCI_PM_D2_DELAY);
 
@@ -1409,6 +1419,7 @@ void pci_pm_init(struct pci_dev *dev)
         }
 
         dev->pm_cap = pm;
+        dev->d3_delay = PCI_PM_D3_WAIT;
 
         dev->d1_support = false;
         dev->d2_support = false;
@@ -2247,12 +2258,12 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
         csr &= ~PCI_PM_CTRL_STATE_MASK;
         csr |= PCI_D3hot;
         pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
-        msleep(pci_pm_d3_delay);
+        pci_dev_d3_sleep(dev);
 
         csr &= ~PCI_PM_CTRL_STATE_MASK;
         csr |= PCI_D0;
         pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
-        msleep(pci_pm_d3_delay);
+        pci_dev_d3_sleep(dev);
 
         return 0;
 }