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authorMatthew Wilcox <matthew@wil.cx>2008-07-25 17:42:58 -0400
committerJesse Barnes <jbarnes@virtuousgeek.org>2008-07-28 17:43:22 -0400
commitce6fce4295ba727b36fdc73040e444bd1aae64cd (patch)
tree7c8e4134b799d3d0ed56888bb8936e0071a05caf /drivers/pci/msi.c
parent29111f579f4f3f2a07385f931854ab0527ae7ea5 (diff)
PCI MSI: Don't disable MSIs if the mask bit isn't supported
David Vrabel has a device which generates an interrupt storm on the INTx pin if we disable MSI interrupts altogether. Masking interrupts is only a performance optimisation, so we can ignore the request to mask the interrupt. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci/msi.c')
-rw-r--r--drivers/pci/msi.c15
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 15af618d36e2..18354817173c 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -126,7 +126,16 @@ static void msix_flush_writes(unsigned int irq)
126 } 126 }
127} 127}
128 128
129static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag) 129/*
130 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
131 * mask all MSI interrupts by clearing the MSI enable bit does not work
132 * reliably as devices without an INTx disable bit will then generate a
133 * level IRQ which will never be cleared.
134 *
135 * Returns 1 if it succeeded in masking the interrupt and 0 if the device
136 * doesn't support MSI masking.
137 */
138static int msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
130{ 139{
131 struct msi_desc *entry; 140 struct msi_desc *entry;
132 141
@@ -144,8 +153,7 @@ static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
144 mask_bits |= flag & mask; 153 mask_bits |= flag & mask;
145 pci_write_config_dword(entry->dev, pos, mask_bits); 154 pci_write_config_dword(entry->dev, pos, mask_bits);
146 } else { 155 } else {
147 __msi_set_enable(entry->dev, entry->msi_attrib.pos, 156 return 0;
148 !flag);
149 } 157 }
150 break; 158 break;
151 case PCI_CAP_ID_MSIX: 159 case PCI_CAP_ID_MSIX:
@@ -161,6 +169,7 @@ static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
161 break; 169 break;
162 } 170 }
163 entry->msi_attrib.masked = !!flag; 171 entry->msi_attrib.masked = !!flag;
172 return 1;
164} 173}
165 174
166void read_msi_msg(unsigned int irq, struct msi_msg *msg) 175void read_msi_msg(unsigned int irq, struct msi_msg *msg)