diff options
| author | Robert Richter <robert.richter@amd.com> | 2010-10-25 10:28:14 -0400 |
|---|---|---|
| committer | Robert Richter <robert.richter@amd.com> | 2010-10-25 10:29:12 -0400 |
| commit | dbd1e66e04558a582e673bc4a9cd933ce0228d93 (patch) | |
| tree | 85f3633276282cde0a3ac558d988704eaa3e68af /drivers/pci/intr_remapping.c | |
| parent | 328b8f1ba50b708a1b3c0acd7c41ee1b356822f6 (diff) | |
| parent | 4a60cfa9457749f7987fd4f3c956dbba5a281129 (diff) | |
Merge commit 'linux-2.6/master' (early part) into oprofile/core
This branch depends on these apic patches:
apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsets
apic, x86: Check if EILVT APIC registers are available (AMD only)
Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'drivers/pci/intr_remapping.c')
| -rw-r--r-- | drivers/pci/intr_remapping.c | 212 |
1 files changed, 27 insertions, 185 deletions
diff --git a/drivers/pci/intr_remapping.c b/drivers/pci/intr_remapping.c index fd1d2867cdcc..ec87cd66f3eb 100644 --- a/drivers/pci/intr_remapping.c +++ b/drivers/pci/intr_remapping.c | |||
| @@ -46,109 +46,24 @@ static __init int setup_intremap(char *str) | |||
| 46 | } | 46 | } |
| 47 | early_param("intremap", setup_intremap); | 47 | early_param("intremap", setup_intremap); |
| 48 | 48 | ||
| 49 | struct irq_2_iommu { | ||
| 50 | struct intel_iommu *iommu; | ||
| 51 | u16 irte_index; | ||
| 52 | u16 sub_handle; | ||
| 53 | u8 irte_mask; | ||
| 54 | }; | ||
| 55 | |||
| 56 | #ifdef CONFIG_GENERIC_HARDIRQS | ||
| 57 | static struct irq_2_iommu *get_one_free_irq_2_iommu(int node) | ||
| 58 | { | ||
| 59 | struct irq_2_iommu *iommu; | ||
| 60 | |||
| 61 | iommu = kzalloc_node(sizeof(*iommu), GFP_ATOMIC, node); | ||
| 62 | printk(KERN_DEBUG "alloc irq_2_iommu on node %d\n", node); | ||
| 63 | |||
| 64 | return iommu; | ||
| 65 | } | ||
| 66 | |||
| 67 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) | ||
| 68 | { | ||
| 69 | struct irq_desc *desc; | ||
| 70 | |||
| 71 | desc = irq_to_desc(irq); | ||
| 72 | |||
| 73 | if (WARN_ON_ONCE(!desc)) | ||
| 74 | return NULL; | ||
| 75 | |||
| 76 | return desc->irq_2_iommu; | ||
| 77 | } | ||
| 78 | |||
| 79 | static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq) | ||
| 80 | { | ||
| 81 | struct irq_desc *desc; | ||
| 82 | struct irq_2_iommu *irq_iommu; | ||
| 83 | |||
| 84 | desc = irq_to_desc(irq); | ||
| 85 | if (!desc) { | ||
| 86 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | ||
| 87 | return NULL; | ||
| 88 | } | ||
| 89 | |||
| 90 | irq_iommu = desc->irq_2_iommu; | ||
| 91 | |||
| 92 | if (!irq_iommu) | ||
| 93 | desc->irq_2_iommu = get_one_free_irq_2_iommu(irq_node(irq)); | ||
| 94 | |||
| 95 | return desc->irq_2_iommu; | ||
| 96 | } | ||
| 97 | |||
| 98 | #else /* !CONFIG_SPARSE_IRQ */ | ||
| 99 | |||
| 100 | static struct irq_2_iommu irq_2_iommuX[NR_IRQS]; | ||
| 101 | |||
| 102 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) | ||
| 103 | { | ||
| 104 | if (irq < nr_irqs) | ||
| 105 | return &irq_2_iommuX[irq]; | ||
| 106 | |||
| 107 | return NULL; | ||
| 108 | } | ||
| 109 | static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq) | ||
| 110 | { | ||
| 111 | return irq_2_iommu(irq); | ||
| 112 | } | ||
| 113 | #endif | ||
| 114 | |||
| 115 | static DEFINE_SPINLOCK(irq_2_ir_lock); | 49 | static DEFINE_SPINLOCK(irq_2_ir_lock); |
| 116 | 50 | ||
| 117 | static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq) | 51 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) |
| 118 | { | ||
| 119 | struct irq_2_iommu *irq_iommu; | ||
| 120 | |||
| 121 | irq_iommu = irq_2_iommu(irq); | ||
| 122 | |||
| 123 | if (!irq_iommu) | ||
| 124 | return NULL; | ||
| 125 | |||
| 126 | if (!irq_iommu->iommu) | ||
| 127 | return NULL; | ||
| 128 | |||
| 129 | return irq_iommu; | ||
| 130 | } | ||
| 131 | |||
| 132 | int irq_remapped(int irq) | ||
| 133 | { | 52 | { |
| 134 | return valid_irq_2_iommu(irq) != NULL; | 53 | struct irq_cfg *cfg = get_irq_chip_data(irq); |
| 54 | return cfg ? &cfg->irq_2_iommu : NULL; | ||
| 135 | } | 55 | } |
| 136 | 56 | ||
| 137 | int get_irte(int irq, struct irte *entry) | 57 | int get_irte(int irq, struct irte *entry) |
| 138 | { | 58 | { |
| 139 | int index; | 59 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
| 140 | struct irq_2_iommu *irq_iommu; | ||
| 141 | unsigned long flags; | 60 | unsigned long flags; |
| 61 | int index; | ||
| 142 | 62 | ||
| 143 | if (!entry) | 63 | if (!entry || !irq_iommu) |
| 144 | return -1; | 64 | return -1; |
| 145 | 65 | ||
| 146 | spin_lock_irqsave(&irq_2_ir_lock, flags); | 66 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
| 147 | irq_iommu = valid_irq_2_iommu(irq); | ||
| 148 | if (!irq_iommu) { | ||
| 149 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); | ||
| 150 | return -1; | ||
| 151 | } | ||
| 152 | 67 | ||
| 153 | index = irq_iommu->irte_index + irq_iommu->sub_handle; | 68 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
| 154 | *entry = *(irq_iommu->iommu->ir_table->base + index); | 69 | *entry = *(irq_iommu->iommu->ir_table->base + index); |
| @@ -160,20 +75,14 @@ int get_irte(int irq, struct irte *entry) | |||
| 160 | int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) | 75 | int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) |
| 161 | { | 76 | { |
| 162 | struct ir_table *table = iommu->ir_table; | 77 | struct ir_table *table = iommu->ir_table; |
| 163 | struct irq_2_iommu *irq_iommu; | 78 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
| 164 | u16 index, start_index; | 79 | u16 index, start_index; |
| 165 | unsigned int mask = 0; | 80 | unsigned int mask = 0; |
| 166 | unsigned long flags; | 81 | unsigned long flags; |
| 167 | int i; | 82 | int i; |
| 168 | 83 | ||
| 169 | if (!count) | 84 | if (!count || !irq_iommu) |
| 170 | return -1; | ||
| 171 | |||
| 172 | #ifndef CONFIG_SPARSE_IRQ | ||
| 173 | /* protect irq_2_iommu_alloc later */ | ||
| 174 | if (irq >= nr_irqs) | ||
| 175 | return -1; | 85 | return -1; |
| 176 | #endif | ||
| 177 | 86 | ||
| 178 | /* | 87 | /* |
| 179 | * start the IRTE search from index 0. | 88 | * start the IRTE search from index 0. |
| @@ -214,13 +123,6 @@ int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) | |||
| 214 | for (i = index; i < index + count; i++) | 123 | for (i = index; i < index + count; i++) |
| 215 | table->base[i].present = 1; | 124 | table->base[i].present = 1; |
| 216 | 125 | ||
| 217 | irq_iommu = irq_2_iommu_alloc(irq); | ||
| 218 | if (!irq_iommu) { | ||
| 219 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); | ||
| 220 | printk(KERN_ERR "can't allocate irq_2_iommu\n"); | ||
| 221 | return -1; | ||
| 222 | } | ||
| 223 | |||
| 224 | irq_iommu->iommu = iommu; | 126 | irq_iommu->iommu = iommu; |
| 225 | irq_iommu->irte_index = index; | 127 | irq_iommu->irte_index = index; |
| 226 | irq_iommu->sub_handle = 0; | 128 | irq_iommu->sub_handle = 0; |
| @@ -244,17 +146,14 @@ static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) | |||
| 244 | 146 | ||
| 245 | int map_irq_to_irte_handle(int irq, u16 *sub_handle) | 147 | int map_irq_to_irte_handle(int irq, u16 *sub_handle) |
| 246 | { | 148 | { |
| 247 | int index; | 149 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
| 248 | struct irq_2_iommu *irq_iommu; | ||
| 249 | unsigned long flags; | 150 | unsigned long flags; |
| 151 | int index; | ||
| 250 | 152 | ||
| 251 | spin_lock_irqsave(&irq_2_ir_lock, flags); | 153 | if (!irq_iommu) |
| 252 | irq_iommu = valid_irq_2_iommu(irq); | ||
| 253 | if (!irq_iommu) { | ||
| 254 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); | ||
| 255 | return -1; | 154 | return -1; |
| 256 | } | ||
| 257 | 155 | ||
| 156 | spin_lock_irqsave(&irq_2_ir_lock, flags); | ||
| 258 | *sub_handle = irq_iommu->sub_handle; | 157 | *sub_handle = irq_iommu->sub_handle; |
| 259 | index = irq_iommu->irte_index; | 158 | index = irq_iommu->irte_index; |
| 260 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); | 159 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
| @@ -263,18 +162,13 @@ int map_irq_to_irte_handle(int irq, u16 *sub_handle) | |||
| 263 | 162 | ||
| 264 | int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) | 163 | int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) |
| 265 | { | 164 | { |
| 266 | struct irq_2_iommu *irq_iommu; | 165 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
| 267 | unsigned long flags; | 166 | unsigned long flags; |
| 268 | 167 | ||
| 269 | spin_lock_irqsave(&irq_2_ir_lock, flags); | 168 | if (!irq_iommu) |
| 270 | |||
| 271 | irq_iommu = irq_2_iommu_alloc(irq); | ||
| 272 | |||
| 273 | if (!irq_iommu) { | ||
| 274 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); | ||
| 275 | printk(KERN_ERR "can't allocate irq_2_iommu\n"); | ||
| 276 | return -1; | 169 | return -1; |
| 277 | } | 170 | |
| 171 | spin_lock_irqsave(&irq_2_ir_lock, flags); | ||
| 278 | 172 | ||
| 279 | irq_iommu->iommu = iommu; | 173 | irq_iommu->iommu = iommu; |
| 280 | irq_iommu->irte_index = index; | 174 | irq_iommu->irte_index = index; |
| @@ -286,43 +180,18 @@ int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) | |||
| 286 | return 0; | 180 | return 0; |
| 287 | } | 181 | } |
| 288 | 182 | ||
| 289 | int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index) | ||
| 290 | { | ||
| 291 | struct irq_2_iommu *irq_iommu; | ||
| 292 | unsigned long flags; | ||
| 293 | |||
| 294 | spin_lock_irqsave(&irq_2_ir_lock, flags); | ||
| 295 | irq_iommu = valid_irq_2_iommu(irq); | ||
| 296 | if (!irq_iommu) { | ||
| 297 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); | ||
| 298 | return -1; | ||
| 299 | } | ||
| 300 | |||
| 301 | irq_iommu->iommu = NULL; | ||
| 302 | irq_iommu->irte_index = 0; | ||
| 303 | irq_iommu->sub_handle = 0; | ||
| 304 | irq_2_iommu(irq)->irte_mask = 0; | ||
| 305 | |||
| 306 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); | ||
| 307 | |||
| 308 | return 0; | ||
| 309 | } | ||
| 310 | |||
| 311 | int modify_irte(int irq, struct irte *irte_modified) | 183 | int modify_irte(int irq, struct irte *irte_modified) |
| 312 | { | 184 | { |
| 313 | int rc; | 185 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
| 314 | int index; | ||
| 315 | struct irte *irte; | ||
| 316 | struct intel_iommu *iommu; | 186 | struct intel_iommu *iommu; |
| 317 | struct irq_2_iommu *irq_iommu; | ||
| 318 | unsigned long flags; | 187 | unsigned long flags; |
| 188 | struct irte *irte; | ||
| 189 | int rc, index; | ||
| 319 | 190 | ||
| 320 | spin_lock_irqsave(&irq_2_ir_lock, flags); | 191 | if (!irq_iommu) |
| 321 | irq_iommu = valid_irq_2_iommu(irq); | ||
| 322 | if (!irq_iommu) { | ||
| 323 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); | ||
| 324 | return -1; | 192 | return -1; |
| 325 | } | 193 | |
| 194 | spin_lock_irqsave(&irq_2_ir_lock, flags); | ||
| 326 | 195 | ||
| 327 | iommu = irq_iommu->iommu; | 196 | iommu = irq_iommu->iommu; |
| 328 | 197 | ||
| @@ -339,31 +208,6 @@ int modify_irte(int irq, struct irte *irte_modified) | |||
| 339 | return rc; | 208 | return rc; |
| 340 | } | 209 | } |
| 341 | 210 | ||
| 342 | int flush_irte(int irq) | ||
| 343 | { | ||
| 344 | int rc; | ||
| 345 | int index; | ||
| 346 | struct intel_iommu *iommu; | ||
| 347 | struct irq_2_iommu *irq_iommu; | ||
| 348 | unsigned long flags; | ||
| 349 | |||
| 350 | spin_lock_irqsave(&irq_2_ir_lock, flags); | ||
| 351 | irq_iommu = valid_irq_2_iommu(irq); | ||
| 352 | if (!irq_iommu) { | ||
| 353 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); | ||
| 354 | return -1; | ||
| 355 | } | ||
| 356 | |||
| 357 | iommu = irq_iommu->iommu; | ||
| 358 | |||
| 359 | index = irq_iommu->irte_index + irq_iommu->sub_handle; | ||
| 360 | |||
| 361 | rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask); | ||
| 362 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); | ||
| 363 | |||
| 364 | return rc; | ||
| 365 | } | ||
| 366 | |||
| 367 | struct intel_iommu *map_hpet_to_ir(u8 hpet_id) | 211 | struct intel_iommu *map_hpet_to_ir(u8 hpet_id) |
| 368 | { | 212 | { |
| 369 | int i; | 213 | int i; |
| @@ -420,16 +264,14 @@ static int clear_entries(struct irq_2_iommu *irq_iommu) | |||
| 420 | 264 | ||
| 421 | int free_irte(int irq) | 265 | int free_irte(int irq) |
| 422 | { | 266 | { |
| 423 | int rc = 0; | 267 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
| 424 | struct irq_2_iommu *irq_iommu; | ||
| 425 | unsigned long flags; | 268 | unsigned long flags; |
| 269 | int rc; | ||
| 426 | 270 | ||
| 427 | spin_lock_irqsave(&irq_2_ir_lock, flags); | 271 | if (!irq_iommu) |
| 428 | irq_iommu = valid_irq_2_iommu(irq); | ||
| 429 | if (!irq_iommu) { | ||
| 430 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); | ||
| 431 | return -1; | 272 | return -1; |
| 432 | } | 273 | |
| 274 | spin_lock_irqsave(&irq_2_ir_lock, flags); | ||
| 433 | 275 | ||
| 434 | rc = clear_entries(irq_iommu); | 276 | rc = clear_entries(irq_iommu); |
| 435 | 277 | ||
