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authorKay, Allen M <allen.m.kay@intel.com>2008-09-09 11:37:29 -0400
committerAvi Kivity <avi@redhat.com>2008-10-15 08:24:08 -0400
commit387179464257921eb9aa3d15cc3ff194f6945a7c (patch)
treea7f06903688df8a1d3231faf1ab68bf80e032ea6 /drivers/pci/intel-iommu.h
parentaa3a816b6d0bd59e1a9c548cc7d2dd829f26534f (diff)
VT-d: Changes to support KVM
This patch extends the VT-d driver to support KVM [Ben: fixed memory pinning] [avi: move dma_remapping.h as well] Signed-off-by: Kay, Allen M <allen.m.kay@intel.com> Signed-off-by: Weidong Han <weidong.han@intel.com> Signed-off-by: Ben-Ami Yassour <benami@il.ibm.com> Signed-off-by: Amit Shah <amit.shah@qumranet.com> Acked-by: Mark Gross <mgross@linux.intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
Diffstat (limited to 'drivers/pci/intel-iommu.h')
-rw-r--r--drivers/pci/intel-iommu.h307
1 files changed, 0 insertions, 307 deletions
diff --git a/drivers/pci/intel-iommu.h b/drivers/pci/intel-iommu.h
deleted file mode 100644
index 2142c01e0143..000000000000
--- a/drivers/pci/intel-iommu.h
+++ /dev/null
@@ -1,307 +0,0 @@
1/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
20 */
21
22#ifndef _INTEL_IOMMU_H_
23#define _INTEL_IOMMU_H_
24
25#include <linux/types.h>
26#include <linux/msi.h>
27#include <linux/sysdev.h>
28#include "iova.h"
29#include <linux/io.h>
30#include <asm/cacheflush.h>
31#include "dma_remapping.h"
32
33/*
34 * Intel IOMMU register specification per version 1.0 public spec.
35 */
36
37#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
38#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
39#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
40#define DMAR_GCMD_REG 0x18 /* Global command register */
41#define DMAR_GSTS_REG 0x1c /* Global status register */
42#define DMAR_RTADDR_REG 0x20 /* Root entry table */
43#define DMAR_CCMD_REG 0x28 /* Context command reg */
44#define DMAR_FSTS_REG 0x34 /* Fault Status register */
45#define DMAR_FECTL_REG 0x38 /* Fault control register */
46#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
47#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
48#define DMAR_FEUADDR_REG 0x44 /* Upper address register */
49#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
50#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
51#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
52#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
53#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
54#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
55#define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
56#define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
57#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
58#define DMAR_ICS_REG 0x98 /* Invalidation complete status register */
59#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
60
61#define OFFSET_STRIDE (9)
62/*
63#define dmar_readl(dmar, reg) readl(dmar + reg)
64#define dmar_readq(dmar, reg) ({ \
65 u32 lo, hi; \
66 lo = readl(dmar + reg); \
67 hi = readl(dmar + reg + 4); \
68 (((u64) hi) << 32) + lo; })
69*/
70static inline u64 dmar_readq(void __iomem *addr)
71{
72 u32 lo, hi;
73 lo = readl(addr);
74 hi = readl(addr + 4);
75 return (((u64) hi) << 32) + lo;
76}
77
78static inline void dmar_writeq(void __iomem *addr, u64 val)
79{
80 writel((u32)val, addr);
81 writel((u32)(val >> 32), addr + 4);
82}
83
84#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
85#define DMAR_VER_MINOR(v) ((v) & 0x0f)
86
87/*
88 * Decoding Capability Register
89 */
90#define cap_read_drain(c) (((c) >> 55) & 1)
91#define cap_write_drain(c) (((c) >> 54) & 1)
92#define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
93#define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
94#define cap_pgsel_inv(c) (((c) >> 39) & 1)
95
96#define cap_super_page_val(c) (((c) >> 34) & 0xf)
97#define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
98 * OFFSET_STRIDE) + 21)
99
100#define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
101#define cap_max_fault_reg_offset(c) \
102 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
103
104#define cap_zlr(c) (((c) >> 22) & 1)
105#define cap_isoch(c) (((c) >> 23) & 1)
106#define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
107#define cap_sagaw(c) (((c) >> 8) & 0x1f)
108#define cap_caching_mode(c) (((c) >> 7) & 1)
109#define cap_phmr(c) (((c) >> 6) & 1)
110#define cap_plmr(c) (((c) >> 5) & 1)
111#define cap_rwbf(c) (((c) >> 4) & 1)
112#define cap_afl(c) (((c) >> 3) & 1)
113#define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
114/*
115 * Extended Capability Register
116 */
117
118#define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1)
119#define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
120#define ecap_max_iotlb_offset(e) \
121 (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)
122#define ecap_coherent(e) ((e) & 0x1)
123#define ecap_qis(e) ((e) & 0x2)
124#define ecap_eim_support(e) ((e >> 4) & 0x1)
125#define ecap_ir_support(e) ((e >> 3) & 0x1)
126#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
127
128
129/* IOTLB_REG */
130#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
131#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
132#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
133#define DMA_TLB_IIRG(type) ((type >> 60) & 7)
134#define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
135#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
136#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
137#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
138#define DMA_TLB_IVT (((u64)1) << 63)
139#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
140#define DMA_TLB_MAX_SIZE (0x3f)
141
142/* INVALID_DESC */
143#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3)
144#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3)
145#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3)
146#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
147#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
148#define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
149#define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
150#define DMA_ID_TLB_ADDR(addr) (addr)
151#define DMA_ID_TLB_ADDR_MASK(mask) (mask)
152
153/* PMEN_REG */
154#define DMA_PMEN_EPM (((u32)1)<<31)
155#define DMA_PMEN_PRS (((u32)1)<<0)
156
157/* GCMD_REG */
158#define DMA_GCMD_TE (((u32)1) << 31)
159#define DMA_GCMD_SRTP (((u32)1) << 30)
160#define DMA_GCMD_SFL (((u32)1) << 29)
161#define DMA_GCMD_EAFL (((u32)1) << 28)
162#define DMA_GCMD_WBF (((u32)1) << 27)
163#define DMA_GCMD_QIE (((u32)1) << 26)
164#define DMA_GCMD_SIRTP (((u32)1) << 24)
165#define DMA_GCMD_IRE (((u32) 1) << 25)
166
167/* GSTS_REG */
168#define DMA_GSTS_TES (((u32)1) << 31)
169#define DMA_GSTS_RTPS (((u32)1) << 30)
170#define DMA_GSTS_FLS (((u32)1) << 29)
171#define DMA_GSTS_AFLS (((u32)1) << 28)
172#define DMA_GSTS_WBFS (((u32)1) << 27)
173#define DMA_GSTS_QIES (((u32)1) << 26)
174#define DMA_GSTS_IRTPS (((u32)1) << 24)
175#define DMA_GSTS_IRES (((u32)1) << 25)
176
177/* CCMD_REG */
178#define DMA_CCMD_ICC (((u64)1) << 63)
179#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
180#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
181#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
182#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
183#define DMA_CCMD_MASK_NOBIT 0
184#define DMA_CCMD_MASK_1BIT 1
185#define DMA_CCMD_MASK_2BIT 2
186#define DMA_CCMD_MASK_3BIT 3
187#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
188#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
189
190/* FECTL_REG */
191#define DMA_FECTL_IM (((u32)1) << 31)
192
193/* FSTS_REG */
194#define DMA_FSTS_PPF ((u32)2)
195#define DMA_FSTS_PFO ((u32)1)
196#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
197
198/* FRCD_REG, 32 bits access */
199#define DMA_FRCD_F (((u32)1) << 31)
200#define dma_frcd_type(d) ((d >> 30) & 1)
201#define dma_frcd_fault_reason(c) (c & 0xff)
202#define dma_frcd_source_id(c) (c & 0xffff)
203#define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */
204
205#define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000) /* 10sec */
206
207#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
208{\
209 cycles_t start_time = get_cycles();\
210 while (1) {\
211 sts = op (iommu->reg + offset);\
212 if (cond)\
213 break;\
214 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
215 panic("DMAR hardware is malfunctioning\n");\
216 cpu_relax();\
217 }\
218}
219
220#define QI_LENGTH 256 /* queue length */
221
222enum {
223 QI_FREE,
224 QI_IN_USE,
225 QI_DONE
226};
227
228#define QI_CC_TYPE 0x1
229#define QI_IOTLB_TYPE 0x2
230#define QI_DIOTLB_TYPE 0x3
231#define QI_IEC_TYPE 0x4
232#define QI_IWD_TYPE 0x5
233
234#define QI_IEC_SELECTIVE (((u64)1) << 4)
235#define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
236#define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
237
238#define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
239#define QI_IWD_STATUS_WRITE (((u64)1) << 5)
240
241struct qi_desc {
242 u64 low, high;
243};
244
245struct q_inval {
246 spinlock_t q_lock;
247 struct qi_desc *desc; /* invalidation queue */
248 int *desc_status; /* desc status */
249 int free_head; /* first free entry */
250 int free_tail; /* last free entry */
251 int free_cnt;
252};
253
254#ifdef CONFIG_INTR_REMAP
255/* 1MB - maximum possible interrupt remapping table size */
256#define INTR_REMAP_PAGE_ORDER 8
257#define INTR_REMAP_TABLE_REG_SIZE 0xf
258
259#define INTR_REMAP_TABLE_ENTRIES 65536
260
261struct ir_table {
262 struct irte *base;
263};
264#endif
265
266struct intel_iommu {
267 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
268 u64 cap;
269 u64 ecap;
270 int seg;
271 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
272 spinlock_t register_lock; /* protect register handling */
273 int seq_id; /* sequence id of the iommu */
274
275#ifdef CONFIG_DMAR
276 unsigned long *domain_ids; /* bitmap of domains */
277 struct dmar_domain **domains; /* ptr to domains */
278 spinlock_t lock; /* protect context, domain ids */
279 struct root_entry *root_entry; /* virtual address */
280
281 unsigned int irq;
282 unsigned char name[7]; /* Device Name */
283 struct msi_msg saved_msg;
284 struct sys_device sysdev;
285#endif
286 struct q_inval *qi; /* Queued invalidation info */
287#ifdef CONFIG_INTR_REMAP
288 struct ir_table *ir_table; /* Interrupt remapping info */
289#endif
290};
291
292static inline void __iommu_flush_cache(
293 struct intel_iommu *iommu, void *addr, int size)
294{
295 if (!ecap_coherent(iommu->ecap))
296 clflush_cache_range(addr, size);
297}
298
299extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
300
301extern int alloc_iommu(struct dmar_drhd_unit *drhd);
302extern void free_iommu(struct intel_iommu *iommu);
303extern int dmar_enable_qi(struct intel_iommu *iommu);
304extern void qi_global_iec(struct intel_iommu *iommu);
305
306extern void qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
307#endif
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