diff options
author | David Woodhouse <David.Woodhouse@intel.com> | 2009-06-29 22:40:07 -0400 |
---|---|---|
committer | David Woodhouse <David.Woodhouse@intel.com> | 2009-06-29 22:58:15 -0400 |
commit | f3a0a52fff4dbfdea2dccc908d00c038481d888e (patch) | |
tree | 956261c5e5a00c115eed6741d1ae10fd71d4a411 /drivers/pci/intel-iommu.c | |
parent | 3d7b0e4154b4963d6bd39991ec8eaa09caeb3994 (diff) |
intel-iommu: Performance improvement for dma_pte_free_pagetable()
As with other functions, batch the CPU data cache flushes and don't keep
recalculating PTE addresses.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/pci/intel-iommu.c')
-rw-r--r-- | drivers/pci/intel-iommu.c | 27 |
1 files changed, 17 insertions, 10 deletions
diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index 35bdd2a06caa..ec7e032d5ab5 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c | |||
@@ -797,7 +797,7 @@ static void dma_pte_free_pagetable(struct dmar_domain *domain, | |||
797 | unsigned long last_pfn) | 797 | unsigned long last_pfn) |
798 | { | 798 | { |
799 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; | 799 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
800 | struct dma_pte *pte; | 800 | struct dma_pte *first_pte, *pte; |
801 | int total = agaw_to_level(domain->agaw); | 801 | int total = agaw_to_level(domain->agaw); |
802 | int level; | 802 | int level; |
803 | unsigned long tmp; | 803 | unsigned long tmp; |
@@ -805,25 +805,32 @@ static void dma_pte_free_pagetable(struct dmar_domain *domain, | |||
805 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); | 805 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
806 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); | 806 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); |
807 | 807 | ||
808 | /* we don't need lock here, nobody else touches the iova range */ | 808 | /* We don't need lock here; nobody else touches the iova range */ |
809 | level = 2; | 809 | level = 2; |
810 | while (level <= total) { | 810 | while (level <= total) { |
811 | tmp = align_to_level(start_pfn, level); | 811 | tmp = align_to_level(start_pfn, level); |
812 | 812 | ||
813 | /* Only clear this pte/pmd if we're asked to clear its | 813 | /* If we can't even clear one PTE at this level, we're done */ |
814 | _whole_ range */ | ||
815 | if (tmp + level_size(level) - 1 > last_pfn) | 814 | if (tmp + level_size(level) - 1 > last_pfn) |
816 | return; | 815 | return; |
817 | 816 | ||
818 | while (tmp + level_size(level) - 1 <= last_pfn) { | 817 | while (tmp + level_size(level) - 1 <= last_pfn) { |
819 | pte = dma_pfn_level_pte(domain, tmp, level); | 818 | first_pte = pte = dma_pfn_level_pte(domain, tmp, level); |
820 | if (pte) { | 819 | if (!pte) { |
821 | free_pgtable_page( | 820 | tmp = align_to_level(tmp + 1, level + 1); |
822 | phys_to_virt(dma_pte_addr(pte))); | 821 | continue; |
822 | } | ||
823 | while (tmp + level_size(level) - 1 <= last_pfn && | ||
824 | (unsigned long)pte >> VTD_PAGE_SHIFT == | ||
825 | (unsigned long)first_pte >> VTD_PAGE_SHIFT) { | ||
826 | free_pgtable_page(phys_to_virt(dma_pte_addr(pte))); | ||
823 | dma_clear_pte(pte); | 827 | dma_clear_pte(pte); |
824 | domain_flush_cache(domain, pte, sizeof(*pte)); | 828 | pte++; |
829 | tmp += level_size(level); | ||
825 | } | 830 | } |
826 | tmp += level_size(level); | 831 | domain_flush_cache(domain, first_pte, |
832 | (void *)pte - (void *)first_pte); | ||
833 | |||
827 | } | 834 | } |
828 | level++; | 835 | level++; |
829 | } | 836 | } |