Merge commit 'linux-2.6/master' (early part) into oprofile/core

This branch depends on these apic patches:

      apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsets
      apic, x86: Check if EILVT APIC registers are available (AMD only)

Signed-off-by: Robert Richter <robert.richter@amd.com>

1 files changed, 8 insertions, 14 deletions

diff --git a/drivers/pci/htirq.c b/drivers/pci/htirq.c
index 98abf8b91294..834842aa5bbf 100644
--- a/drivers/pci/htirq.c
+++ b/drivers/pci/htirq.c
@@ -57,28 +57,22 @@ void fetch_ht_irq_msg(unsigned int irq, struct ht_irq_msg *msg)
         *msg = cfg->msg;
 }
 
-void mask_ht_irq(unsigned int irq)
+void mask_ht_irq(struct irq_data *data)
 {
-        struct ht_irq_cfg *cfg;
-        struct ht_irq_msg msg;
-
-        cfg = get_irq_data(irq);
+        struct ht_irq_cfg *cfg = irq_data_get_irq_data(data);
+        struct ht_irq_msg msg = cfg->msg;
 
-        msg = cfg->msg;
         msg.address_lo |= 1;
-        write_ht_irq_msg(irq, &msg);
+        write_ht_irq_msg(data->irq, &msg);
 }
 
-void unmask_ht_irq(unsigned int irq)
+void unmask_ht_irq(struct irq_data *data)
 {
-        struct ht_irq_cfg *cfg;
-        struct ht_irq_msg msg;
-
-        cfg = get_irq_data(irq);
+        struct ht_irq_cfg *cfg = irq_data_get_irq_data(data);
+        struct ht_irq_msg msg = cfg->msg;
 
-        msg = cfg->msg;
         msg.address_lo &= ~1;
-        write_ht_irq_msg(irq, &msg);
+        write_ht_irq_msg(data->irq, &msg);
 }
 
 /**