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authorrajesh.shah@intel.com <rajesh.shah@intel.com>2005-10-13 15:05:38 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2005-10-28 18:37:00 -0400
commit424600f9706b20a8a33ad928d3d0326bd88679bc (patch)
tree364509b512ff4f522b38329df582553a9c8fb6ff /drivers/pci/hotplug/shpchprm_nonacpi.c
parent7e88ed199689f333668b62348051202706b6a74a (diff)
[PATCH] shpchp: reduce dependence on ACPI
Reduce the SHPC hotplug driver's dependence on ACPI. We don't walk the acpi namespace anymore to build a list of bridges and devices. The remaining interaction with ACPI is to run the _OSHP method to transition control of hotplug hardware from system BIOS to the shpc hotplug driver, and to run the _HPP method to get hotplug device parameters like cache line size, latency timer and SERR/PERR enable from BIOS. Note that one of the side effects of this patch is that shpchp does not enable the hot-added device or its DMA bus mastering automatically now. It expects the device driver to do that. This may break some drivers and we will have to fix them as they are reported. Signed-off-by: Rajesh Shah <rajesh.shah@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/pci/hotplug/shpchprm_nonacpi.c')
-rw-r--r--drivers/pci/hotplug/shpchprm_nonacpi.c108
1 files changed, 5 insertions, 103 deletions
diff --git a/drivers/pci/hotplug/shpchprm_nonacpi.c b/drivers/pci/hotplug/shpchprm_nonacpi.c
index 9d4ccae5f78e..f36c188c23eb 100644
--- a/drivers/pci/hotplug/shpchprm_nonacpi.c
+++ b/drivers/pci/hotplug/shpchprm_nonacpi.c
@@ -37,11 +37,6 @@
37#include "shpchp.h" 37#include "shpchp.h"
38#include "shpchprm.h" 38#include "shpchprm.h"
39 39
40void shpchprm_cleanup(void)
41{
42 return;
43}
44
45int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum) 40int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum)
46{ 41{
47 int offset = devnum - ctrl->slot_device_offset; 42 int offset = devnum - ctrl->slot_device_offset;
@@ -51,106 +46,13 @@ int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busn
51 return 0; 46 return 0;
52} 47}
53 48
54int shpchprm_set_hpp( 49void get_hp_params_from_firmware(struct pci_dev *dev,
55 struct controller *ctrl, 50 struct hotplug_params *hpp)
56 struct pci_func *func,
57 u8 card_type)
58{
59 u32 rc;
60 u8 temp_byte;
61 struct pci_bus lpci_bus, *pci_bus;
62 unsigned int devfn;
63 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
64 pci_bus = &lpci_bus;
65 pci_bus->number = func->bus;
66 devfn = PCI_DEVFN(func->device, func->function);
67
68 temp_byte = 0x40; /* hard coded value for LT */
69 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
70 /* set subordinate Latency Timer */
71 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, temp_byte);
72
73 if (rc) {
74 dbg("%s: set secondary LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus,
75 func->device, func->function);
76 return rc;
77 }
78 }
79
80 /* set base Latency Timer */
81 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, temp_byte);
82
83 if (rc) {
84 dbg("%s: set LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
85 return rc;
86 }
87
88 /* set Cache Line size */
89 temp_byte = 0x08; /* hard coded value for CLS */
90
91 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, temp_byte);
92
93 if (rc) {
94 dbg("%s: set CLS error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
95 }
96
97 /* set enable_perr */
98 /* set enable_serr */
99
100 return rc;
101}
102
103void shpchprm_enable_card(
104 struct controller *ctrl,
105 struct pci_func *func,
106 u8 card_type)
107{ 51{
108 u16 command, bcommand; 52 return;
109 struct pci_bus lpci_bus, *pci_bus;
110 unsigned int devfn;
111 int rc;
112
113 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
114 pci_bus = &lpci_bus;
115 pci_bus->number = func->bus;
116 devfn = PCI_DEVFN(func->device, func->function);
117
118 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &command);
119
120 command |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR
121 | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
122 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
123
124 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
125
126 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
127
128 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, &bcommand);
129
130 bcommand |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR
131 | PCI_BRIDGE_CTL_NO_ISA;
132
133 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, bcommand);
134 }
135}
136
137static int legacy_shpchprm_init_pci(void)
138{
139 return 0;
140} 53}
141 54
142int shpchprm_init(enum php_ctlr_type ctrl_type) 55void get_hp_hw_control_from_firmware(struct pci_dev *dev)
143{ 56{
144 int retval; 57 return;
145
146 switch (ctrl_type) {
147 case PCI:
148 retval = legacy_shpchprm_init_pci();
149 break;
150 default:
151 retval = -ENODEV;
152 break;
153 }
154
155 return retval;
156} 58}