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authorrajesh.shah@intel.com <rajesh.shah@intel.com>2005-10-13 15:05:38 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2005-10-28 18:37:00 -0400
commit424600f9706b20a8a33ad928d3d0326bd88679bc (patch)
tree364509b512ff4f522b38329df582553a9c8fb6ff /drivers/pci/hotplug/shpchprm_legacy.c
parent7e88ed199689f333668b62348051202706b6a74a (diff)
[PATCH] shpchp: reduce dependence on ACPI
Reduce the SHPC hotplug driver's dependence on ACPI. We don't walk the acpi namespace anymore to build a list of bridges and devices. The remaining interaction with ACPI is to run the _OSHP method to transition control of hotplug hardware from system BIOS to the shpc hotplug driver, and to run the _HPP method to get hotplug device parameters like cache line size, latency timer and SERR/PERR enable from BIOS. Note that one of the side effects of this patch is that shpchp does not enable the hot-added device or its DMA bus mastering automatically now. It expects the device driver to do that. This may break some drivers and we will have to fix them as they are reported. Signed-off-by: Rajesh Shah <rajesh.shah@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/pci/hotplug/shpchprm_legacy.c')
-rw-r--r--drivers/pci/hotplug/shpchprm_legacy.c97
1 files changed, 5 insertions, 92 deletions
diff --git a/drivers/pci/hotplug/shpchprm_legacy.c b/drivers/pci/hotplug/shpchprm_legacy.c
index 6c27debe9522..cfc6092e2afd 100644
--- a/drivers/pci/hotplug/shpchprm_legacy.c
+++ b/drivers/pci/hotplug/shpchprm_legacy.c
@@ -37,10 +37,6 @@
37#include "shpchp.h" 37#include "shpchp.h"
38#include "shpchprm.h" 38#include "shpchprm.h"
39 39
40void shpchprm_cleanup(void)
41{
42}
43
44int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum) 40int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum)
45{ 41{
46 int offset = devnum - ctrl->slot_device_offset; 42 int offset = devnum - ctrl->slot_device_offset;
@@ -49,97 +45,14 @@ int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busn
49 return 0; 45 return 0;
50} 46}
51 47
52int shpchprm_set_hpp( 48void get_hp_params_from_firmware(struct pci_dev *dev,
53 struct controller *ctrl, 49 struct hotplug_params *hpp)
54 struct pci_func *func,
55 u8 card_type)
56{ 50{
57 u32 rc; 51 return;
58 u8 temp_byte;
59 struct pci_bus lpci_bus, *pci_bus;
60 unsigned int devfn;
61 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
62 pci_bus = &lpci_bus;
63 pci_bus->number = func->bus;
64 devfn = PCI_DEVFN(func->device, func->function);
65
66 temp_byte = 0x40; /* hard coded value for LT */
67 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
68 /* set subordinate Latency Timer */
69 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, temp_byte);
70 if (rc) {
71 dbg("%s: set secondary LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus,
72 func->device, func->function);
73 return rc;
74 }
75 }
76
77 /* set base Latency Timer */
78 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, temp_byte);
79 if (rc) {
80 dbg("%s: set LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
81 return rc;
82 }
83
84 /* set Cache Line size */
85 temp_byte = 0x08; /* hard coded value for CLS */
86 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, temp_byte);
87 if (rc) {
88 dbg("%s: set CLS error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
89 }
90
91 /* set enable_perr */
92 /* set enable_serr */
93
94 return rc;
95} 52}
96 53
97void shpchprm_enable_card( 54void get_hp_hw_control_from_firmware(struct pci_dev *dev)
98 struct controller *ctrl,
99 struct pci_func *func,
100 u8 card_type)
101{ 55{
102 u16 command, bcommand; 56 return;
103 struct pci_bus lpci_bus, *pci_bus;
104 unsigned int devfn;
105 int rc;
106
107 memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
108 pci_bus = &lpci_bus;
109 pci_bus->number = func->bus;
110 devfn = PCI_DEVFN(func->device, func->function);
111
112 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &command);
113 command |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR
114 | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
115 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
116 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
117
118 if (card_type == PCI_HEADER_TYPE_BRIDGE) {
119 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, &bcommand);
120 bcommand |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR
121 | PCI_BRIDGE_CTL_NO_ISA;
122 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, bcommand);
123 }
124}
125
126static int legacy_shpchprm_init_pci(void)
127{
128 return 0;
129} 57}
130 58
131int shpchprm_init(enum php_ctlr_type ctrl_type)
132{
133 int retval;
134
135 switch (ctrl_type) {
136 case PCI:
137 retval = legacy_shpchprm_init_pci();
138 break;
139 default:
140 retval = -ENODEV;
141 break;
142 }
143
144 return retval;
145}