diff options
author | Taku Izumi <izumi.taku@jp.fujitsu.com> | 2008-10-22 22:54:39 -0400 |
---|---|---|
committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2008-10-23 19:14:00 -0400 |
commit | be7bce250a88fbbb5a67204eb148bce8b798780a (patch) | |
tree | c30a5f7f145e4b4ab59f139b529eb170fa00f682 /drivers/pci/hotplug/shpchp_hpc.c | |
parent | f98ca311f3a32e2adc229fecd6bf732db07fcca3 (diff) |
PCI hotplug: shpchp: message refinement
This patch refines messages in shpchp module. The main changes are as
follows:
- remove the trailing "."
- remove __func__ as much as possible
- capitalize the first letter of messages
- show PCI device address including its domain
Signed-off-by: Taku Izumi <izumi.taku@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci/hotplug/shpchp_hpc.c')
-rw-r--r-- | drivers/pci/hotplug/shpchp_hpc.c | 73 |
1 files changed, 33 insertions, 40 deletions
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c index 2b69a08326b7..86dc39847769 100644 --- a/drivers/pci/hotplug/shpchp_hpc.c +++ b/drivers/pci/hotplug/shpchp_hpc.c | |||
@@ -320,8 +320,7 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) | |||
320 | 320 | ||
321 | if (!shpc_poll_ctrl_busy(ctrl)) { | 321 | if (!shpc_poll_ctrl_busy(ctrl)) { |
322 | /* After 1 sec and and the controller is still busy */ | 322 | /* After 1 sec and and the controller is still busy */ |
323 | ctrl_err(ctrl, "%s : Controller is still busy after 1 sec.\n", | 323 | ctrl_err(ctrl, "Controller is still busy after 1 sec\n"); |
324 | __func__); | ||
325 | retval = -EBUSY; | 324 | retval = -EBUSY; |
326 | goto out; | 325 | goto out; |
327 | } | 326 | } |
@@ -344,8 +343,9 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) | |||
344 | 343 | ||
345 | cmd_status = hpc_check_cmd_status(slot->ctrl); | 344 | cmd_status = hpc_check_cmd_status(slot->ctrl); |
346 | if (cmd_status) { | 345 | if (cmd_status) { |
347 | ctrl_err(ctrl, "%s: Failed to issued command 0x%x " | 346 | ctrl_err(ctrl, |
348 | "(error code = %d)\n", __func__, cmd, cmd_status); | 347 | "Failed to issued command 0x%x (error code = %d)\n", |
348 | cmd, cmd_status); | ||
349 | retval = -EIO; | 349 | retval = -EIO; |
350 | } | 350 | } |
351 | out: | 351 | out: |
@@ -364,15 +364,15 @@ static int hpc_check_cmd_status(struct controller *ctrl) | |||
364 | break; | 364 | break; |
365 | case 1: | 365 | case 1: |
366 | retval = SWITCH_OPEN; | 366 | retval = SWITCH_OPEN; |
367 | ctrl_err(ctrl, "%s: Switch opened!\n", __func__); | 367 | ctrl_err(ctrl, "Switch opened!\n"); |
368 | break; | 368 | break; |
369 | case 2: | 369 | case 2: |
370 | retval = INVALID_CMD; | 370 | retval = INVALID_CMD; |
371 | ctrl_err(ctrl, "%s: Invalid HPC command!\n", __func__); | 371 | ctrl_err(ctrl, "Invalid HPC command!\n"); |
372 | break; | 372 | break; |
373 | case 4: | 373 | case 4: |
374 | retval = INVALID_SPEED_MODE; | 374 | retval = INVALID_SPEED_MODE; |
375 | ctrl_err(ctrl, "%s: Invalid bus speed/mode!\n", __func__); | 375 | ctrl_err(ctrl, "Invalid bus speed/mode!\n"); |
376 | break; | 376 | break; |
377 | default: | 377 | default: |
378 | retval = cmd_status; | 378 | retval = cmd_status; |
@@ -773,8 +773,8 @@ static irqreturn_t shpc_isr(int irq, void *dev_id) | |||
773 | continue; | 773 | continue; |
774 | 774 | ||
775 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); | 775 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
776 | ctrl_dbg(ctrl, "%s: Slot %x with intr, slot register = %x\n", | 776 | ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n", |
777 | __func__, hp_slot, slot_reg); | 777 | hp_slot, slot_reg); |
778 | 778 | ||
779 | if (slot_reg & MRL_CHANGE_DETECTED) | 779 | if (slot_reg & MRL_CHANGE_DETECTED) |
780 | shpchp_handle_switch_change(hp_slot, ctrl); | 780 | shpchp_handle_switch_change(hp_slot, ctrl); |
@@ -949,6 +949,7 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev) | |||
949 | u8 i; | 949 | u8 i; |
950 | 950 | ||
951 | ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ | 951 | ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ |
952 | ctrl_dbg(ctrl, "Hotplug Controller:\n"); | ||
952 | 953 | ||
953 | if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == | 954 | if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == |
954 | PCI_DEVICE_ID_AMD_GOLAM_7450)) { | 955 | PCI_DEVICE_ID_AMD_GOLAM_7450)) { |
@@ -958,38 +959,33 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev) | |||
958 | } else { | 959 | } else { |
959 | ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); | 960 | ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); |
960 | if (!ctrl->cap_offset) { | 961 | if (!ctrl->cap_offset) { |
961 | ctrl_err(ctrl, "%s : cap_offset == 0\n", __func__); | 962 | ctrl_err(ctrl, "Cannot find PCI capability\n"); |
962 | goto abort; | 963 | goto abort; |
963 | } | 964 | } |
964 | ctrl_dbg(ctrl, "%s: cap_offset = %x\n", __func__, | 965 | ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset); |
965 | ctrl->cap_offset); | ||
966 | 966 | ||
967 | rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); | 967 | rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); |
968 | if (rc) { | 968 | if (rc) { |
969 | ctrl_err(ctrl, "%s: cannot read base_offset\n", | 969 | ctrl_err(ctrl, "Cannot read base_offset\n"); |
970 | __func__); | ||
971 | goto abort; | 970 | goto abort; |
972 | } | 971 | } |
973 | 972 | ||
974 | rc = shpc_indirect_read(ctrl, 3, &tempdword); | 973 | rc = shpc_indirect_read(ctrl, 3, &tempdword); |
975 | if (rc) { | 974 | if (rc) { |
976 | ctrl_err(ctrl, "%s: cannot read slot config\n", | 975 | ctrl_err(ctrl, "Cannot read slot config\n"); |
977 | __func__); | ||
978 | goto abort; | 976 | goto abort; |
979 | } | 977 | } |
980 | num_slots = tempdword & SLOT_NUM; | 978 | num_slots = tempdword & SLOT_NUM; |
981 | ctrl_dbg(ctrl, "%s: num_slots (indirect) %x\n", | 979 | ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots); |
982 | __func__, num_slots); | ||
983 | 980 | ||
984 | for (i = 0; i < 9 + num_slots; i++) { | 981 | for (i = 0; i < 9 + num_slots; i++) { |
985 | rc = shpc_indirect_read(ctrl, i, &tempdword); | 982 | rc = shpc_indirect_read(ctrl, i, &tempdword); |
986 | if (rc) { | 983 | if (rc) { |
987 | ctrl_err(ctrl, "%s: cannot read creg " | 984 | ctrl_err(ctrl, |
988 | "(index = %d)\n", __func__, i); | 985 | "Cannot read creg (index = %d)\n", i); |
989 | goto abort; | 986 | goto abort; |
990 | } | 987 | } |
991 | ctrl_dbg(ctrl, "%s: offset %d: value %x\n", | 988 | ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword); |
992 | __func__, i, tempdword); | ||
993 | } | 989 | } |
994 | 990 | ||
995 | ctrl->mmio_base = | 991 | ctrl->mmio_base = |
@@ -1003,25 +999,25 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev) | |||
1003 | 999 | ||
1004 | rc = pci_enable_device(pdev); | 1000 | rc = pci_enable_device(pdev); |
1005 | if (rc) { | 1001 | if (rc) { |
1006 | ctrl_err(ctrl, "%s: pci_enable_device failed\n", __func__); | 1002 | ctrl_err(ctrl, "pci_enable_device failed\n"); |
1007 | goto abort; | 1003 | goto abort; |
1008 | } | 1004 | } |
1009 | 1005 | ||
1010 | if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { | 1006 | if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { |
1011 | ctrl_err(ctrl, "%s: cannot reserve MMIO region\n", __func__); | 1007 | ctrl_err(ctrl, "Cannot reserve MMIO region\n"); |
1012 | rc = -1; | 1008 | rc = -1; |
1013 | goto abort; | 1009 | goto abort; |
1014 | } | 1010 | } |
1015 | 1011 | ||
1016 | ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); | 1012 | ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); |
1017 | if (!ctrl->creg) { | 1013 | if (!ctrl->creg) { |
1018 | ctrl_err(ctrl, "%s: cannot remap MMIO region %lx @ %lx\n", | 1014 | ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n", |
1019 | __func__, ctrl->mmio_size, ctrl->mmio_base); | 1015 | ctrl->mmio_size, ctrl->mmio_base); |
1020 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); | 1016 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); |
1021 | rc = -1; | 1017 | rc = -1; |
1022 | goto abort; | 1018 | goto abort; |
1023 | } | 1019 | } |
1024 | ctrl_dbg(ctrl, "%s: ctrl->creg %p\n", __func__, ctrl->creg); | 1020 | ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg); |
1025 | 1021 | ||
1026 | mutex_init(&ctrl->crit_sect); | 1022 | mutex_init(&ctrl->crit_sect); |
1027 | mutex_init(&ctrl->cmd_lock); | 1023 | mutex_init(&ctrl->cmd_lock); |
@@ -1040,21 +1036,21 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev) | |||
1040 | 1036 | ||
1041 | /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ | 1037 | /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ |
1042 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); | 1038 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
1043 | ctrl_dbg(ctrl, "%s: SERR_INTR_ENABLE = %x\n", __func__, tempdword); | 1039 | ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
1044 | tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | | 1040 | tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | |
1045 | COMMAND_INTR_MASK | ARBITER_SERR_MASK); | 1041 | COMMAND_INTR_MASK | ARBITER_SERR_MASK); |
1046 | tempdword &= ~SERR_INTR_RSVDZ_MASK; | 1042 | tempdword &= ~SERR_INTR_RSVDZ_MASK; |
1047 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); | 1043 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
1048 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); | 1044 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
1049 | ctrl_dbg(ctrl, "%s: SERR_INTR_ENABLE = %x\n", __func__, tempdword); | 1045 | ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
1050 | 1046 | ||
1051 | /* Mask the MRL sensor SERR Mask of individual slot in | 1047 | /* Mask the MRL sensor SERR Mask of individual slot in |
1052 | * Slot SERR-INT Mask & clear all the existing event if any | 1048 | * Slot SERR-INT Mask & clear all the existing event if any |
1053 | */ | 1049 | */ |
1054 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { | 1050 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
1055 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); | 1051 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
1056 | ctrl_dbg(ctrl, "%s: Default Logical Slot Register %d " | 1052 | ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", |
1057 | "value %x\n", __func__, hp_slot, slot_reg); | 1053 | hp_slot, slot_reg); |
1058 | slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | | 1054 | slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
1059 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | | 1055 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | |
1060 | CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | | 1056 | CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | |
@@ -1079,8 +1075,8 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev) | |||
1079 | 1075 | ||
1080 | rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, | 1076 | rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, |
1081 | MY_NAME, (void *)ctrl); | 1077 | MY_NAME, (void *)ctrl); |
1082 | ctrl_dbg(ctrl, "%s: request_irq %d for hpc%d (returns %d)\n", | 1078 | ctrl_dbg(ctrl, "request_irq %d for hpc%d (returns %d)\n", |
1083 | __func__, ctrl->pci_dev->irq, | 1079 | ctrl->pci_dev->irq, |
1084 | atomic_read(&shpchp_num_controllers), rc); | 1080 | atomic_read(&shpchp_num_controllers), rc); |
1085 | if (rc) { | 1081 | if (rc) { |
1086 | ctrl_err(ctrl, "Can't get irq %d for the hotplug " | 1082 | ctrl_err(ctrl, "Can't get irq %d for the hotplug " |
@@ -1088,9 +1084,7 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev) | |||
1088 | goto abort_iounmap; | 1084 | goto abort_iounmap; |
1089 | } | 1085 | } |
1090 | } | 1086 | } |
1091 | ctrl_dbg(ctrl, "%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", | 1087 | ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq); |
1092 | __func__, pdev->bus->number, PCI_SLOT(pdev->devfn), | ||
1093 | PCI_FUNC(pdev->devfn), pdev->irq); | ||
1094 | 1088 | ||
1095 | /* | 1089 | /* |
1096 | * If this is the first controller to be initialized, | 1090 | * If this is the first controller to be initialized, |
@@ -1109,8 +1103,8 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev) | |||
1109 | */ | 1103 | */ |
1110 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { | 1104 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
1111 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); | 1105 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
1112 | ctrl_dbg(ctrl, "%s: Default Logical Slot Register %d " | 1106 | ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", |
1113 | "value %x\n", __func__, hp_slot, slot_reg); | 1107 | hp_slot, slot_reg); |
1114 | slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | | 1108 | slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
1115 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | | 1109 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | |
1116 | CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); | 1110 | CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); |
@@ -1123,8 +1117,7 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev) | |||
1123 | SERR_INTR_RSVDZ_MASK); | 1117 | SERR_INTR_RSVDZ_MASK); |
1124 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); | 1118 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
1125 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); | 1119 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
1126 | ctrl_dbg(ctrl, "%s: SERR_INTR_ENABLE = %x\n", | 1120 | ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
1127 | __func__, tempdword); | ||
1128 | } | 1121 | } |
1129 | 1122 | ||
1130 | return 0; | 1123 | return 0; |