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authorKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>2006-05-01 22:09:42 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2006-06-19 17:13:23 -0400
commit2b34da7e61383b4b7773d2d4e776e58725794347 (patch)
tree9f350ae052288ed099332f148f0b234330bb6e16 /drivers/pci/hotplug/shpchp_hpc.c
parent75d97c59a192ca0fe2577974dac0c16a73a377eb (diff)
[PATCH] SHPC: Cleanup SHPC Logical Slot Register access
This patch cleans up the code to access slot logical registers. This patch has no functional changes. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Cc: Kristen Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/pci/hotplug/shpchp_hpc.c')
-rw-r--r--drivers/pci/hotplug/shpchp_hpc.c31
1 files changed, 18 insertions, 13 deletions
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c
index 3abeb54964ae..a5337cf1436d 100644
--- a/drivers/pci/hotplug/shpchp_hpc.c
+++ b/drivers/pci/hotplug/shpchp_hpc.c
@@ -90,6 +90,11 @@
90#define MRLSENSOR 0x40000000 90#define MRLSENSOR 0x40000000
91#define ATTN_BUTTON 0x80000000 91#define ATTN_BUTTON 0x80000000
92 92
93/*
94 * Logical Slot Register definitions
95 */
96#define SLOT_REG(i) (SLOT1 + (4 * i))
97
93/* Slot Status Field Definitions */ 98/* Slot Status Field Definitions */
94/* Slot State */ 99/* Slot State */
95#define PWR_ONLY 0x0001 100#define PWR_ONLY 0x0001
@@ -433,7 +438,7 @@ static int hpc_get_attention_status(struct slot *slot, u8 *status)
433 return -1; 438 return -1;
434 } 439 }
435 440
436 slot_reg = shpc_readl(ctrl, SLOT1 + 4*(slot->hp_slot)); 441 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
437 slot_status = (u16) slot_reg; 442 slot_status = (u16) slot_reg;
438 atten_led_state = (slot_status & 0x0030) >> 4; 443 atten_led_state = (slot_status & 0x0030) >> 4;
439 444
@@ -474,7 +479,7 @@ static int hpc_get_power_status(struct slot * slot, u8 *status)
474 return -1; 479 return -1;
475 } 480 }
476 481
477 slot_reg = shpc_readl(ctrl, SLOT1 + 4*(slot->hp_slot)); 482 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
478 slot_status = (u16) slot_reg; 483 slot_status = (u16) slot_reg;
479 slot_state = (slot_status & 0x0003); 484 slot_state = (slot_status & 0x0003);
480 485
@@ -514,7 +519,7 @@ static int hpc_get_latch_status(struct slot *slot, u8 *status)
514 return -1; 519 return -1;
515 } 520 }
516 521
517 slot_reg = shpc_readl(ctrl, SLOT1 + 4*(slot->hp_slot)); 522 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
518 slot_status = (u16)slot_reg; 523 slot_status = (u16)slot_reg;
519 524
520 *status = ((slot_status & 0x0100) == 0) ? 0 : 1; /* 0 -> close; 1 -> open */ 525 *status = ((slot_status & 0x0100) == 0) ? 0 : 1; /* 0 -> close; 1 -> open */
@@ -538,7 +543,7 @@ static int hpc_get_adapter_status(struct slot *slot, u8 *status)
538 return -1; 543 return -1;
539 } 544 }
540 545
541 slot_reg = shpc_readl(ctrl, SLOT1 + 4*(slot->hp_slot)); 546 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
542 slot_status = (u16)slot_reg; 547 slot_status = (u16)slot_reg;
543 card_state = (u8)((slot_status & 0x0C00) >> 10); 548 card_state = (u8)((slot_status & 0x0C00) >> 10);
544 *status = (card_state != 0x3) ? 1 : 0; 549 *status = (card_state != 0x3) ? 1 : 0;
@@ -568,7 +573,7 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
568{ 573{
569 int retval = 0; 574 int retval = 0;
570 struct controller *ctrl = slot->ctrl; 575 struct controller *ctrl = slot->ctrl;
571 u32 slot_reg = shpc_readl(ctrl, SLOT1 + 4 * slot->hp_slot); 576 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
572 u8 pcix_cap = (slot_reg >> 12) & 7; 577 u8 pcix_cap = (slot_reg >> 12) & 7;
573 u8 m66_cap = (slot_reg >> 9) & 1; 578 u8 m66_cap = (slot_reg >> 9) & 1;
574 579
@@ -648,7 +653,7 @@ static int hpc_query_power_fault(struct slot * slot)
648 return -1; 653 return -1;
649 } 654 }
650 655
651 slot_reg = shpc_readl(ctrl, SLOT1 + 4*(slot->hp_slot)); 656 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
652 slot_status = (u16) slot_reg; 657 slot_status = (u16) slot_reg;
653 pwr_fault_state = (slot_status & 0x0040) >> 7; 658 pwr_fault_state = (slot_status & 0x0040) >> 7;
654 status = (pwr_fault_state == 1) ? 0 : 1; 659 status = (pwr_fault_state == 1) ? 0 : 1;
@@ -805,7 +810,7 @@ static void hpc_release_ctlr(struct controller *ctrl)
805 * Mask all slot event interrupts 810 * Mask all slot event interrupts
806 */ 811 */
807 for (i = 0; i < ctrl->num_slots; i++) 812 for (i = 0; i < ctrl->num_slots; i++)
808 shpc_writel(ctrl, SLOT1 + (4 * i), 0xffff3fff); 813 shpc_writel(ctrl, SLOT_REG(i), 0xffff3fff);
809 814
810 cleanup_slots(ctrl); 815 cleanup_slots(ctrl);
811 816
@@ -1072,7 +1077,7 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1072 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 1077 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1073 /* To find out which slot has interrupt pending */ 1078 /* To find out which slot has interrupt pending */
1074 if ((intr_loc >> hp_slot) & 0x01) { 1079 if ((intr_loc >> hp_slot) & 0x01) {
1075 temp_dword = shpc_readl(ctrl, SLOT1 + (4*hp_slot)); 1080 temp_dword = shpc_readl(ctrl, SLOT_REG(hp_slot));
1076 dbg("%s: Slot %x with intr, slot register = %x\n", 1081 dbg("%s: Slot %x with intr, slot register = %x\n",
1077 __FUNCTION__, hp_slot, temp_dword); 1082 __FUNCTION__, hp_slot, temp_dword);
1078 temp_byte = (temp_dword >> 16) & 0xFF; 1083 temp_byte = (temp_dword >> 16) & 0xFF;
@@ -1091,7 +1096,7 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1091 1096
1092 /* Clear all slot events */ 1097 /* Clear all slot events */
1093 temp_dword = 0xe01f3fff; 1098 temp_dword = 0xe01f3fff;
1094 shpc_writel(ctrl, SLOT1 + (4*hp_slot), temp_dword); 1099 shpc_writel(ctrl, SLOT_REG(hp_slot), temp_dword);
1095 1100
1096 intr_loc2 = shpc_readl(ctrl, INTR_LOC); 1101 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
1097 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2); 1102 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
@@ -1379,11 +1384,11 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
1379 * Slot SERR-INT Mask & clear all the existing event if any 1384 * Slot SERR-INT Mask & clear all the existing event if any
1380 */ 1385 */
1381 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { 1386 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1382 slot_reg = shpc_readl(ctrl, SLOT1 + 4*hp_slot ); 1387 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1383 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, 1388 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1384 hp_slot, slot_reg); 1389 hp_slot, slot_reg);
1385 tempdword = 0xffff3fff; 1390 tempdword = 0xffff3fff;
1386 shpc_writel(ctrl, SLOT1 + (4*hp_slot), tempdword); 1391 shpc_writel(ctrl, SLOT_REG(hp_slot), tempdword);
1387 } 1392 }
1388 1393
1389 if (shpchp_poll_mode) {/* Install interrupt polling code */ 1394 if (shpchp_poll_mode) {/* Install interrupt polling code */
@@ -1430,11 +1435,11 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
1430 ctlr_seq_num++; 1435 ctlr_seq_num++;
1431 1436
1432 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { 1437 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1433 slot_reg = shpc_readl(ctrl, SLOT1 + 4*hp_slot ); 1438 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1434 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, 1439 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1435 hp_slot, slot_reg); 1440 hp_slot, slot_reg);
1436 tempdword = 0xe01f3fff; 1441 tempdword = 0xe01f3fff;
1437 shpc_writel(ctrl, SLOT1 + (4*hp_slot), tempdword); 1442 shpc_writel(ctrl, SLOT_REG(hp_slot), tempdword);
1438 } 1443 }
1439 if (!shpchp_poll_mode) { 1444 if (!shpchp_poll_mode) {
1440 /* Unmask all general input interrupts and SERR */ 1445 /* Unmask all general input interrupts and SERR */