diff options
author | Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> | 2006-12-16 18:25:34 -0500 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2006-12-20 13:54:44 -0500 |
commit | 0abe68ce24973a23fcc6cbce80343f68656de7b6 (patch) | |
tree | 695eba97613f0e0c1e7749d6144ec04879527548 /drivers/pci/hotplug/shpchp_hpc.c | |
parent | ab17443a3df35abe4b7529e83511a591aa7384f3 (diff) |
shpchp: remove unnecessary struct php_ctlr
The struct php_ctlr seems to be only for complicating codes. This
patch removes struct php_ctlr and related codes.
Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/pci/hotplug/shpchp_hpc.c')
-rw-r--r-- | drivers/pci/hotplug/shpchp_hpc.c | 223 |
1 files changed, 62 insertions, 161 deletions
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c index 83a5226ba9ed..b7bede4b7c27 100644 --- a/drivers/pci/hotplug/shpchp_hpc.c +++ b/drivers/pci/hotplug/shpchp_hpc.c | |||
@@ -212,44 +212,40 @@ | |||
212 | #define SLOT_SERR_INT_MASK 0x3 | 212 | #define SLOT_SERR_INT_MASK 0x3 |
213 | 213 | ||
214 | DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ | 214 | DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ |
215 | static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */ | ||
216 | static int ctlr_seq_num = 0; /* Controller sequenc # */ | ||
217 | static spinlock_t list_lock; | ||
218 | |||
219 | static atomic_t shpchp_num_controllers = ATOMIC_INIT(0); | 215 | static atomic_t shpchp_num_controllers = ATOMIC_INIT(0); |
220 | 216 | ||
221 | static irqreturn_t shpc_isr(int irq, void *dev_id); | 217 | static irqreturn_t shpc_isr(int irq, void *dev_id); |
222 | static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec); | 218 | static void start_int_poll_timer(struct controller *ctrl, int sec); |
223 | static int hpc_check_cmd_status(struct controller *ctrl); | 219 | static int hpc_check_cmd_status(struct controller *ctrl); |
224 | 220 | ||
225 | static inline u8 shpc_readb(struct controller *ctrl, int reg) | 221 | static inline u8 shpc_readb(struct controller *ctrl, int reg) |
226 | { | 222 | { |
227 | return readb(ctrl->hpc_ctlr_handle->creg + reg); | 223 | return readb(ctrl->creg + reg); |
228 | } | 224 | } |
229 | 225 | ||
230 | static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) | 226 | static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) |
231 | { | 227 | { |
232 | writeb(val, ctrl->hpc_ctlr_handle->creg + reg); | 228 | writeb(val, ctrl->creg + reg); |
233 | } | 229 | } |
234 | 230 | ||
235 | static inline u16 shpc_readw(struct controller *ctrl, int reg) | 231 | static inline u16 shpc_readw(struct controller *ctrl, int reg) |
236 | { | 232 | { |
237 | return readw(ctrl->hpc_ctlr_handle->creg + reg); | 233 | return readw(ctrl->creg + reg); |
238 | } | 234 | } |
239 | 235 | ||
240 | static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) | 236 | static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) |
241 | { | 237 | { |
242 | writew(val, ctrl->hpc_ctlr_handle->creg + reg); | 238 | writew(val, ctrl->creg + reg); |
243 | } | 239 | } |
244 | 240 | ||
245 | static inline u32 shpc_readl(struct controller *ctrl, int reg) | 241 | static inline u32 shpc_readl(struct controller *ctrl, int reg) |
246 | { | 242 | { |
247 | return readl(ctrl->hpc_ctlr_handle->creg + reg); | 243 | return readl(ctrl->creg + reg); |
248 | } | 244 | } |
249 | 245 | ||
250 | static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) | 246 | static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) |
251 | { | 247 | { |
252 | writel(val, ctrl->hpc_ctlr_handle->creg + reg); | 248 | writel(val, ctrl->creg + reg); |
253 | } | 249 | } |
254 | 250 | ||
255 | static inline int shpc_indirect_read(struct controller *ctrl, int index, | 251 | static inline int shpc_indirect_read(struct controller *ctrl, int index, |
@@ -268,21 +264,20 @@ static inline int shpc_indirect_read(struct controller *ctrl, int index, | |||
268 | /* | 264 | /* |
269 | * This is the interrupt polling timeout function. | 265 | * This is the interrupt polling timeout function. |
270 | */ | 266 | */ |
271 | static void int_poll_timeout(unsigned long lphp_ctlr) | 267 | static void int_poll_timeout(unsigned long data) |
272 | { | 268 | { |
273 | struct php_ctlr_state_s *php_ctlr = | 269 | struct controller *ctrl = (struct controller *)data; |
274 | (struct php_ctlr_state_s *)lphp_ctlr; | ||
275 | 270 | ||
276 | DBG_ENTER_ROUTINE | 271 | DBG_ENTER_ROUTINE |
277 | 272 | ||
278 | /* Poll for interrupt events. regs == NULL => polling */ | 273 | /* Poll for interrupt events. regs == NULL => polling */ |
279 | shpc_isr(0, php_ctlr->callback_instance_id); | 274 | shpc_isr(0, ctrl); |
280 | 275 | ||
281 | init_timer(&php_ctlr->int_poll_timer); | 276 | init_timer(&ctrl->poll_timer); |
282 | if (!shpchp_poll_time) | 277 | if (!shpchp_poll_time) |
283 | shpchp_poll_time = 2; /* default polling interval is 2 sec */ | 278 | shpchp_poll_time = 2; /* default polling interval is 2 sec */ |
284 | 279 | ||
285 | start_int_poll_timer(php_ctlr, shpchp_poll_time); | 280 | start_int_poll_timer(ctrl, shpchp_poll_time); |
286 | 281 | ||
287 | DBG_LEAVE_ROUTINE | 282 | DBG_LEAVE_ROUTINE |
288 | } | 283 | } |
@@ -290,16 +285,16 @@ static void int_poll_timeout(unsigned long lphp_ctlr) | |||
290 | /* | 285 | /* |
291 | * This function starts the interrupt polling timer. | 286 | * This function starts the interrupt polling timer. |
292 | */ | 287 | */ |
293 | static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec) | 288 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
294 | { | 289 | { |
295 | /* Clamp to sane value */ | 290 | /* Clamp to sane value */ |
296 | if ((sec <= 0) || (sec > 60)) | 291 | if ((sec <= 0) || (sec > 60)) |
297 | sec = 2; | 292 | sec = 2; |
298 | 293 | ||
299 | php_ctlr->int_poll_timer.function = &int_poll_timeout; | 294 | ctrl->poll_timer.function = &int_poll_timeout; |
300 | php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; | 295 | ctrl->poll_timer.data = (unsigned long)ctrl; |
301 | php_ctlr->int_poll_timer.expires = jiffies + sec * HZ; | 296 | ctrl->poll_timer.expires = jiffies + sec * HZ; |
302 | add_timer(&php_ctlr->int_poll_timer); | 297 | add_timer(&ctrl->poll_timer); |
303 | } | 298 | } |
304 | 299 | ||
305 | static inline int is_ctrl_busy(struct controller *ctrl) | 300 | static inline int is_ctrl_busy(struct controller *ctrl) |
@@ -666,33 +661,8 @@ static void hpc_set_green_led_blink(struct slot *slot) | |||
666 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); | 661 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); |
667 | } | 662 | } |
668 | 663 | ||
669 | int shpc_get_ctlr_slot_config(struct controller *ctrl, | ||
670 | int *num_ctlr_slots, /* number of slots in this HPC */ | ||
671 | int *first_device_num, /* PCI dev num of the first slot in this SHPC */ | ||
672 | int *physical_slot_num, /* phy slot num of the first slot in this SHPC */ | ||
673 | int *updown, /* physical_slot_num increament: 1 or -1 */ | ||
674 | int *flags) | ||
675 | { | ||
676 | u32 slot_config; | ||
677 | |||
678 | DBG_ENTER_ROUTINE | ||
679 | |||
680 | slot_config = shpc_readl(ctrl, SLOT_CONFIG); | ||
681 | *first_device_num = (slot_config & FIRST_DEV_NUM) >> 8; | ||
682 | *num_ctlr_slots = slot_config & SLOT_NUM; | ||
683 | *physical_slot_num = (slot_config & PSN) >> 16; | ||
684 | *updown = ((slot_config & UPDOWN) >> 29) ? 1 : -1; | ||
685 | |||
686 | dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num); | ||
687 | |||
688 | DBG_LEAVE_ROUTINE | ||
689 | return 0; | ||
690 | } | ||
691 | |||
692 | static void hpc_release_ctlr(struct controller *ctrl) | 664 | static void hpc_release_ctlr(struct controller *ctrl) |
693 | { | 665 | { |
694 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; | ||
695 | struct php_ctlr_state_s *p, *p_prev; | ||
696 | int i; | 666 | int i; |
697 | u32 slot_reg, serr_int; | 667 | u32 slot_reg, serr_int; |
698 | 668 | ||
@@ -722,40 +692,15 @@ static void hpc_release_ctlr(struct controller *ctrl) | |||
722 | serr_int &= ~SERR_INTR_RSVDZ_MASK; | 692 | serr_int &= ~SERR_INTR_RSVDZ_MASK; |
723 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); | 693 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); |
724 | 694 | ||
725 | if (shpchp_poll_mode) { | 695 | if (shpchp_poll_mode) |
726 | del_timer(&php_ctlr->int_poll_timer); | 696 | del_timer(&ctrl->poll_timer); |
727 | } else { | 697 | else { |
728 | if (php_ctlr->irq) { | 698 | free_irq(ctrl->pci_dev->irq, ctrl); |
729 | free_irq(php_ctlr->irq, ctrl); | 699 | pci_disable_msi(ctrl->pci_dev); |
730 | php_ctlr->irq = 0; | ||
731 | pci_disable_msi(php_ctlr->pci_dev); | ||
732 | } | ||
733 | } | ||
734 | |||
735 | if (php_ctlr->pci_dev) { | ||
736 | iounmap(php_ctlr->creg); | ||
737 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); | ||
738 | php_ctlr->pci_dev = NULL; | ||
739 | } | ||
740 | |||
741 | spin_lock(&list_lock); | ||
742 | p = php_ctlr_list_head; | ||
743 | p_prev = NULL; | ||
744 | while (p) { | ||
745 | if (p == php_ctlr) { | ||
746 | if (p_prev) | ||
747 | p_prev->pnext = p->pnext; | ||
748 | else | ||
749 | php_ctlr_list_head = p->pnext; | ||
750 | break; | ||
751 | } else { | ||
752 | p_prev = p; | ||
753 | p = p->pnext; | ||
754 | } | ||
755 | } | 700 | } |
756 | spin_unlock(&list_lock); | ||
757 | 701 | ||
758 | kfree(php_ctlr); | 702 | iounmap(ctrl->creg); |
703 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); | ||
759 | 704 | ||
760 | /* | 705 | /* |
761 | * If this is the last controller to be released, destroy the | 706 | * If this is the last controller to be released, destroy the |
@@ -764,8 +709,7 @@ static void hpc_release_ctlr(struct controller *ctrl) | |||
764 | if (atomic_dec_and_test(&shpchp_num_controllers)) | 709 | if (atomic_dec_and_test(&shpchp_num_controllers)) |
765 | destroy_workqueue(shpchp_wq); | 710 | destroy_workqueue(shpchp_wq); |
766 | 711 | ||
767 | DBG_LEAVE_ROUTINE | 712 | DBG_LEAVE_ROUTINE |
768 | |||
769 | } | 713 | } |
770 | 714 | ||
771 | static int hpc_power_on_slot(struct slot * slot) | 715 | static int hpc_power_on_slot(struct slot * slot) |
@@ -891,7 +835,6 @@ static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) | |||
891 | static irqreturn_t shpc_isr(int irq, void *dev_id) | 835 | static irqreturn_t shpc_isr(int irq, void *dev_id) |
892 | { | 836 | { |
893 | struct controller *ctrl = (struct controller *)dev_id; | 837 | struct controller *ctrl = (struct controller *)dev_id; |
894 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; | ||
895 | u32 serr_int, slot_reg, intr_loc, intr_loc2; | 838 | u32 serr_int, slot_reg, intr_loc, intr_loc2; |
896 | int hp_slot; | 839 | int hp_slot; |
897 | 840 | ||
@@ -942,20 +885,16 @@ static irqreturn_t shpc_isr(int irq, void *dev_id) | |||
942 | __FUNCTION__, hp_slot, slot_reg); | 885 | __FUNCTION__, hp_slot, slot_reg); |
943 | 886 | ||
944 | if (slot_reg & MRL_CHANGE_DETECTED) | 887 | if (slot_reg & MRL_CHANGE_DETECTED) |
945 | php_ctlr->switch_change_callback( | 888 | shpchp_handle_switch_change(hp_slot, ctrl); |
946 | hp_slot, php_ctlr->callback_instance_id); | ||
947 | 889 | ||
948 | if (slot_reg & BUTTON_PRESS_DETECTED) | 890 | if (slot_reg & BUTTON_PRESS_DETECTED) |
949 | php_ctlr->attention_button_callback( | 891 | shpchp_handle_attention_button(hp_slot, ctrl); |
950 | hp_slot, php_ctlr->callback_instance_id); | ||
951 | 892 | ||
952 | if (slot_reg & PRSNT_CHANGE_DETECTED) | 893 | if (slot_reg & PRSNT_CHANGE_DETECTED) |
953 | php_ctlr->presence_change_callback( | 894 | shpchp_handle_presence_change(hp_slot, ctrl); |
954 | hp_slot , php_ctlr->callback_instance_id); | ||
955 | 895 | ||
956 | if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) | 896 | if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) |
957 | php_ctlr->power_fault_callback( | 897 | shpchp_handle_power_fault(hp_slot, ctrl); |
958 | hp_slot, php_ctlr->callback_instance_id); | ||
959 | 898 | ||
960 | /* Clear all slot events */ | 899 | /* Clear all slot events */ |
961 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; | 900 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; |
@@ -1114,10 +1053,8 @@ static struct hpc_ops shpchp_hpc_ops = { | |||
1114 | .release_ctlr = hpc_release_ctlr, | 1053 | .release_ctlr = hpc_release_ctlr, |
1115 | }; | 1054 | }; |
1116 | 1055 | ||
1117 | int shpc_init(struct controller * ctrl, struct pci_dev * pdev) | 1056 | int shpc_init(struct controller *ctrl, struct pci_dev *pdev) |
1118 | { | 1057 | { |
1119 | struct php_ctlr_state_s *php_ctlr, *p; | ||
1120 | void *instance_id = ctrl; | ||
1121 | int rc = -1, num_slots = 0; | 1058 | int rc = -1, num_slots = 0; |
1122 | u8 hp_slot; | 1059 | u8 hp_slot; |
1123 | u32 shpc_base_offset; | 1060 | u32 shpc_base_offset; |
@@ -1128,16 +1065,6 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev) | |||
1128 | 1065 | ||
1129 | ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ | 1066 | ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ |
1130 | 1067 | ||
1131 | spin_lock_init(&list_lock); | ||
1132 | php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL); | ||
1133 | |||
1134 | if (!php_ctlr) { /* allocate controller state data */ | ||
1135 | err("%s: HPC controller memory allocation error!\n", __FUNCTION__); | ||
1136 | goto abort; | ||
1137 | } | ||
1138 | |||
1139 | php_ctlr->pci_dev = pdev; /* save pci_dev in context */ | ||
1140 | |||
1141 | if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == | 1068 | if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == |
1142 | PCI_DEVICE_ID_AMD_GOLAM_7450)) { | 1069 | PCI_DEVICE_ID_AMD_GOLAM_7450)) { |
1143 | /* amd shpc driver doesn't use Base Offset; assume 0 */ | 1070 | /* amd shpc driver doesn't use Base Offset; assume 0 */ |
@@ -1147,20 +1074,20 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev) | |||
1147 | ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); | 1074 | ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); |
1148 | if (!ctrl->cap_offset) { | 1075 | if (!ctrl->cap_offset) { |
1149 | err("%s : cap_offset == 0\n", __FUNCTION__); | 1076 | err("%s : cap_offset == 0\n", __FUNCTION__); |
1150 | goto abort_free_ctlr; | 1077 | goto abort; |
1151 | } | 1078 | } |
1152 | dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset); | 1079 | dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset); |
1153 | 1080 | ||
1154 | rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); | 1081 | rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); |
1155 | if (rc) { | 1082 | if (rc) { |
1156 | err("%s: cannot read base_offset\n", __FUNCTION__); | 1083 | err("%s: cannot read base_offset\n", __FUNCTION__); |
1157 | goto abort_free_ctlr; | 1084 | goto abort; |
1158 | } | 1085 | } |
1159 | 1086 | ||
1160 | rc = shpc_indirect_read(ctrl, 3, &tempdword); | 1087 | rc = shpc_indirect_read(ctrl, 3, &tempdword); |
1161 | if (rc) { | 1088 | if (rc) { |
1162 | err("%s: cannot read slot config\n", __FUNCTION__); | 1089 | err("%s: cannot read slot config\n", __FUNCTION__); |
1163 | goto abort_free_ctlr; | 1090 | goto abort; |
1164 | } | 1091 | } |
1165 | num_slots = tempdword & SLOT_NUM; | 1092 | num_slots = tempdword & SLOT_NUM; |
1166 | dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots); | 1093 | dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots); |
@@ -1170,7 +1097,7 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev) | |||
1170 | if (rc) { | 1097 | if (rc) { |
1171 | err("%s: cannot read creg (index = %d)\n", | 1098 | err("%s: cannot read creg (index = %d)\n", |
1172 | __FUNCTION__, i); | 1099 | __FUNCTION__, i); |
1173 | goto abort_free_ctlr; | 1100 | goto abort; |
1174 | } | 1101 | } |
1175 | dbg("%s: offset %d: value %x\n", __FUNCTION__,i, | 1102 | dbg("%s: offset %d: value %x\n", __FUNCTION__,i, |
1176 | tempdword); | 1103 | tempdword); |
@@ -1187,24 +1114,24 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev) | |||
1187 | rc = pci_enable_device(pdev); | 1114 | rc = pci_enable_device(pdev); |
1188 | if (rc) { | 1115 | if (rc) { |
1189 | err("%s: pci_enable_device failed\n", __FUNCTION__); | 1116 | err("%s: pci_enable_device failed\n", __FUNCTION__); |
1190 | goto abort_free_ctlr; | 1117 | goto abort; |
1191 | } | 1118 | } |
1192 | 1119 | ||
1193 | if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { | 1120 | if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { |
1194 | err("%s: cannot reserve MMIO region\n", __FUNCTION__); | 1121 | err("%s: cannot reserve MMIO region\n", __FUNCTION__); |
1195 | rc = -1; | 1122 | rc = -1; |
1196 | goto abort_free_ctlr; | 1123 | goto abort; |
1197 | } | 1124 | } |
1198 | 1125 | ||
1199 | php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); | 1126 | ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); |
1200 | if (!php_ctlr->creg) { | 1127 | if (!ctrl->creg) { |
1201 | err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__, | 1128 | err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__, |
1202 | ctrl->mmio_size, ctrl->mmio_base); | 1129 | ctrl->mmio_size, ctrl->mmio_base); |
1203 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); | 1130 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); |
1204 | rc = -1; | 1131 | rc = -1; |
1205 | goto abort_free_ctlr; | 1132 | goto abort; |
1206 | } | 1133 | } |
1207 | dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg); | 1134 | dbg("%s: ctrl->creg %p\n", __FUNCTION__, ctrl->creg); |
1208 | 1135 | ||
1209 | mutex_init(&ctrl->crit_sect); | 1136 | mutex_init(&ctrl->crit_sect); |
1210 | mutex_init(&ctrl->cmd_lock); | 1137 | mutex_init(&ctrl->cmd_lock); |
@@ -1212,23 +1139,14 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev) | |||
1212 | /* Setup wait queue */ | 1139 | /* Setup wait queue */ |
1213 | init_waitqueue_head(&ctrl->queue); | 1140 | init_waitqueue_head(&ctrl->queue); |
1214 | 1141 | ||
1215 | /* Find the IRQ */ | ||
1216 | php_ctlr->irq = pdev->irq; | ||
1217 | php_ctlr->attention_button_callback = shpchp_handle_attention_button, | ||
1218 | php_ctlr->switch_change_callback = shpchp_handle_switch_change; | ||
1219 | php_ctlr->presence_change_callback = shpchp_handle_presence_change; | ||
1220 | php_ctlr->power_fault_callback = shpchp_handle_power_fault; | ||
1221 | php_ctlr->callback_instance_id = instance_id; | ||
1222 | |||
1223 | ctrl->hpc_ctlr_handle = php_ctlr; | ||
1224 | ctrl->hpc_ops = &shpchp_hpc_ops; | 1142 | ctrl->hpc_ops = &shpchp_hpc_ops; |
1225 | 1143 | ||
1226 | /* Return PCI Controller Info */ | 1144 | /* Return PCI Controller Info */ |
1227 | slot_config = shpc_readl(ctrl, SLOT_CONFIG); | 1145 | slot_config = shpc_readl(ctrl, SLOT_CONFIG); |
1228 | php_ctlr->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; | 1146 | ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; |
1229 | php_ctlr->num_slots = slot_config & SLOT_NUM; | 1147 | ctrl->num_slots = slot_config & SLOT_NUM; |
1230 | dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset); | 1148 | ctrl->first_slot = (slot_config & PSN) >> 16; |
1231 | dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots); | 1149 | ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1; |
1232 | 1150 | ||
1233 | /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ | 1151 | /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ |
1234 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); | 1152 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
@@ -1243,7 +1161,7 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev) | |||
1243 | /* Mask the MRL sensor SERR Mask of individual slot in | 1161 | /* Mask the MRL sensor SERR Mask of individual slot in |
1244 | * Slot SERR-INT Mask & clear all the existing event if any | 1162 | * Slot SERR-INT Mask & clear all the existing event if any |
1245 | */ | 1163 | */ |
1246 | for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { | 1164 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
1247 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); | 1165 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
1248 | dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, | 1166 | dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, |
1249 | hp_slot, slot_reg); | 1167 | hp_slot, slot_reg); |
@@ -1255,24 +1173,27 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev) | |||
1255 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); | 1173 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); |
1256 | } | 1174 | } |
1257 | 1175 | ||
1258 | if (shpchp_poll_mode) {/* Install interrupt polling code */ | 1176 | if (shpchp_poll_mode) { |
1259 | /* Install and start the interrupt polling timer */ | 1177 | /* Install interrupt polling timer. Start with 10 sec delay */ |
1260 | init_timer(&php_ctlr->int_poll_timer); | 1178 | init_timer(&ctrl->poll_timer); |
1261 | start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */ | 1179 | start_int_poll_timer(ctrl, 10); |
1262 | } else { | 1180 | } else { |
1263 | /* Installs the interrupt handler */ | 1181 | /* Installs the interrupt handler */ |
1264 | rc = pci_enable_msi(pdev); | 1182 | rc = pci_enable_msi(pdev); |
1265 | if (rc) { | 1183 | if (rc) { |
1266 | info("Can't get msi for the hotplug controller\n"); | 1184 | info("Can't get msi for the hotplug controller\n"); |
1267 | info("Use INTx for the hotplug controller\n"); | 1185 | info("Use INTx for the hotplug controller\n"); |
1268 | } else | 1186 | } |
1269 | php_ctlr->irq = pdev->irq; | ||
1270 | 1187 | ||
1271 | rc = request_irq(php_ctlr->irq, shpc_isr, IRQF_SHARED, MY_NAME, (void *) ctrl); | 1188 | rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, |
1272 | dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc); | 1189 | MY_NAME, (void *)ctrl); |
1190 | dbg("%s: request_irq %d for hpc%d (returns %d)\n", | ||
1191 | __FUNCTION__, ctrl->pci_dev->irq, | ||
1192 | atomic_read(&shpchp_num_controllers), rc); | ||
1273 | if (rc) { | 1193 | if (rc) { |
1274 | err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq); | 1194 | err("Can't get irq %d for the hotplug controller\n", |
1275 | goto abort_free_ctlr; | 1195 | ctrl->pci_dev->irq); |
1196 | goto abort_iounmap; | ||
1276 | } | 1197 | } |
1277 | } | 1198 | } |
1278 | dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__, | 1199 | dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__, |
@@ -1280,24 +1201,6 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev) | |||
1280 | PCI_FUNC(pdev->devfn), pdev->irq); | 1201 | PCI_FUNC(pdev->devfn), pdev->irq); |
1281 | get_hp_hw_control_from_firmware(pdev); | 1202 | get_hp_hw_control_from_firmware(pdev); |
1282 | 1203 | ||
1283 | /* Add this HPC instance into the HPC list */ | ||
1284 | spin_lock(&list_lock); | ||
1285 | if (php_ctlr_list_head == 0) { | ||
1286 | php_ctlr_list_head = php_ctlr; | ||
1287 | p = php_ctlr_list_head; | ||
1288 | p->pnext = NULL; | ||
1289 | } else { | ||
1290 | p = php_ctlr_list_head; | ||
1291 | |||
1292 | while (p->pnext) | ||
1293 | p = p->pnext; | ||
1294 | |||
1295 | p->pnext = php_ctlr; | ||
1296 | } | ||
1297 | spin_unlock(&list_lock); | ||
1298 | |||
1299 | ctlr_seq_num++; | ||
1300 | |||
1301 | /* | 1204 | /* |
1302 | * If this is the first controller to be initialized, | 1205 | * If this is the first controller to be initialized, |
1303 | * initialize the shpchpd work queue | 1206 | * initialize the shpchpd work queue |
@@ -1306,14 +1209,14 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev) | |||
1306 | shpchp_wq = create_singlethread_workqueue("shpchpd"); | 1209 | shpchp_wq = create_singlethread_workqueue("shpchpd"); |
1307 | if (!shpchp_wq) { | 1210 | if (!shpchp_wq) { |
1308 | rc = -ENOMEM; | 1211 | rc = -ENOMEM; |
1309 | goto abort_free_ctlr; | 1212 | goto abort_iounmap; |
1310 | } | 1213 | } |
1311 | } | 1214 | } |
1312 | 1215 | ||
1313 | /* | 1216 | /* |
1314 | * Unmask all event interrupts of all slots | 1217 | * Unmask all event interrupts of all slots |
1315 | */ | 1218 | */ |
1316 | for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { | 1219 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
1317 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); | 1220 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
1318 | dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, | 1221 | dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, |
1319 | hp_slot, slot_reg); | 1222 | hp_slot, slot_reg); |
@@ -1336,10 +1239,8 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev) | |||
1336 | return 0; | 1239 | return 0; |
1337 | 1240 | ||
1338 | /* We end up here for the many possible ways to fail this API. */ | 1241 | /* We end up here for the many possible ways to fail this API. */ |
1339 | abort_free_ctlr: | 1242 | abort_iounmap: |
1340 | if (php_ctlr->creg) | 1243 | iounmap(ctrl->creg); |
1341 | iounmap(php_ctlr->creg); | ||
1342 | kfree(php_ctlr); | ||
1343 | abort: | 1244 | abort: |
1344 | DBG_LEAVE_ROUTINE | 1245 | DBG_LEAVE_ROUTINE |
1345 | return rc; | 1246 | return rc; |