aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pci/hotplug/shpchp_hpc.c
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2008-04-21 18:58:35 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-04-21 18:58:35 -0400
commitbda0c0afa7a694bb1459fd023515aca681e4d79a (patch)
treecd8b9d9811463de2065cbe79d59689082d6c53cf /drivers/pci/hotplug/shpchp_hpc.c
parent904e0ab54b7591b9cb01cfc0dbbedcc8bc0d949b (diff)
parentaf40b485ea2d957ae2f237ab0e33539ae8f29562 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6: (42 commits) PCI: Change PCI subsystem MAINTAINER PCI: pci-iommu-iotlb-flushing-speedup PCI: pci_setup_bridge() mustn't be __devinit PCI: pci_bus_size_cardbus() mustn't be __devinit PCI: pci_scan_device() mustn't be __devinit PCI: pci_alloc_child_bus() mustn't be __devinit PCI: replace remaining __FUNCTION__ occurrences PCI: Hotplug: fakephp: Return success, not ENODEV, when bus rescan is triggered PCI: Hotplug: Fix leaks in IBM Hot Plug Controller Driver - ibmphp_init_devno() PCI: clean up resource alignment management PCI: aerdrv_acpi.c: remove unneeded NULL check PCI: Update VIA CX700 quirk PCI: Expose PCI VPD through sysfs PCI: iommu: iotlb flushing PCI: simplify quirk debug output PCI: iova RB tree setup tweak PCI: parisc: use generic pci_enable_resources() PCI: ppc: use generic pci_enable_resources() PCI: powerpc: use generic pci_enable_resources() PCI: ia64: use generic pci_enable_resources() ...
Diffstat (limited to 'drivers/pci/hotplug/shpchp_hpc.c')
-rw-r--r--drivers/pci/hotplug/shpchp_hpc.c64
1 files changed, 32 insertions, 32 deletions
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c
index e8aa138128ce..7d770b2cd889 100644
--- a/drivers/pci/hotplug/shpchp_hpc.c
+++ b/drivers/pci/hotplug/shpchp_hpc.c
@@ -321,14 +321,14 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
321 if (!shpc_poll_ctrl_busy(ctrl)) { 321 if (!shpc_poll_ctrl_busy(ctrl)) {
322 /* After 1 sec and and the controller is still busy */ 322 /* After 1 sec and and the controller is still busy */
323 err("%s : Controller is still busy after 1 sec.\n", 323 err("%s : Controller is still busy after 1 sec.\n",
324 __FUNCTION__); 324 __func__);
325 retval = -EBUSY; 325 retval = -EBUSY;
326 goto out; 326 goto out;
327 } 327 }
328 328
329 ++t_slot; 329 ++t_slot;
330 temp_word = (t_slot << 8) | (cmd & 0xFF); 330 temp_word = (t_slot << 8) | (cmd & 0xFF);
331 dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd); 331 dbg("%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
332 332
333 /* To make sure the Controller Busy bit is 0 before we send out the 333 /* To make sure the Controller Busy bit is 0 before we send out the
334 * command. 334 * command.
@@ -345,7 +345,7 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
345 cmd_status = hpc_check_cmd_status(slot->ctrl); 345 cmd_status = hpc_check_cmd_status(slot->ctrl);
346 if (cmd_status) { 346 if (cmd_status) {
347 err("%s: Failed to issued command 0x%x (error code = %d)\n", 347 err("%s: Failed to issued command 0x%x (error code = %d)\n",
348 __FUNCTION__, cmd, cmd_status); 348 __func__, cmd, cmd_status);
349 retval = -EIO; 349 retval = -EIO;
350 } 350 }
351 out: 351 out:
@@ -364,15 +364,15 @@ static int hpc_check_cmd_status(struct controller *ctrl)
364 break; 364 break;
365 case 1: 365 case 1:
366 retval = SWITCH_OPEN; 366 retval = SWITCH_OPEN;
367 err("%s: Switch opened!\n", __FUNCTION__); 367 err("%s: Switch opened!\n", __func__);
368 break; 368 break;
369 case 2: 369 case 2:
370 retval = INVALID_CMD; 370 retval = INVALID_CMD;
371 err("%s: Invalid HPC command!\n", __FUNCTION__); 371 err("%s: Invalid HPC command!\n", __func__);
372 break; 372 break;
373 case 4: 373 case 4:
374 retval = INVALID_SPEED_MODE; 374 retval = INVALID_SPEED_MODE;
375 err("%s: Invalid bus speed/mode!\n", __FUNCTION__); 375 err("%s: Invalid bus speed/mode!\n", __func__);
376 break; 376 break;
377 default: 377 default:
378 retval = cmd_status; 378 retval = cmd_status;
@@ -484,7 +484,7 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
484 } 484 }
485 485
486 dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", 486 dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
487 __FUNCTION__, slot_reg, pcix_cap, m66_cap); 487 __func__, slot_reg, pcix_cap, m66_cap);
488 488
489 switch (pcix_cap) { 489 switch (pcix_cap) {
490 case 0x0: 490 case 0x0:
@@ -629,7 +629,7 @@ static int hpc_power_on_slot(struct slot * slot)
629 629
630 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); 630 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
631 if (retval) 631 if (retval)
632 err("%s: Write command failed!\n", __FUNCTION__); 632 err("%s: Write command failed!\n", __func__);
633 633
634 return retval; 634 return retval;
635} 635}
@@ -642,7 +642,7 @@ static int hpc_slot_enable(struct slot * slot)
642 retval = shpc_write_cmd(slot, slot->hp_slot, 642 retval = shpc_write_cmd(slot, slot->hp_slot,
643 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); 643 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
644 if (retval) 644 if (retval)
645 err("%s: Write command failed!\n", __FUNCTION__); 645 err("%s: Write command failed!\n", __func__);
646 646
647 return retval; 647 return retval;
648} 648}
@@ -655,7 +655,7 @@ static int hpc_slot_disable(struct slot * slot)
655 retval = shpc_write_cmd(slot, slot->hp_slot, 655 retval = shpc_write_cmd(slot, slot->hp_slot,
656 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); 656 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
657 if (retval) 657 if (retval)
658 err("%s: Write command failed!\n", __FUNCTION__); 658 err("%s: Write command failed!\n", __func__);
659 659
660 return retval; 660 return retval;
661} 661}
@@ -719,7 +719,7 @@ static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
719 719
720 retval = shpc_write_cmd(slot, 0, cmd); 720 retval = shpc_write_cmd(slot, 0, cmd);
721 if (retval) 721 if (retval)
722 err("%s: Write command failed!\n", __FUNCTION__); 722 err("%s: Write command failed!\n", __func__);
723 723
724 return retval; 724 return retval;
725} 725}
@@ -735,7 +735,7 @@ static irqreturn_t shpc_isr(int irq, void *dev_id)
735 if (!intr_loc) 735 if (!intr_loc)
736 return IRQ_NONE; 736 return IRQ_NONE;
737 737
738 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc); 738 dbg("%s: intr_loc = %x\n",__func__, intr_loc);
739 739
740 if(!shpchp_poll_mode) { 740 if(!shpchp_poll_mode) {
741 /* 741 /*
@@ -748,7 +748,7 @@ static irqreturn_t shpc_isr(int irq, void *dev_id)
748 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 748 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
749 749
750 intr_loc2 = shpc_readl(ctrl, INTR_LOC); 750 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
751 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2); 751 dbg("%s: intr_loc2 = %x\n",__func__, intr_loc2);
752 } 752 }
753 753
754 if (intr_loc & CMD_INTR_PENDING) { 754 if (intr_loc & CMD_INTR_PENDING) {
@@ -774,7 +774,7 @@ static irqreturn_t shpc_isr(int irq, void *dev_id)
774 774
775 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 775 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
776 dbg("%s: Slot %x with intr, slot register = %x\n", 776 dbg("%s: Slot %x with intr, slot register = %x\n",
777 __FUNCTION__, hp_slot, slot_reg); 777 __func__, hp_slot, slot_reg);
778 778
779 if (slot_reg & MRL_CHANGE_DETECTED) 779 if (slot_reg & MRL_CHANGE_DETECTED)
780 shpchp_handle_switch_change(hp_slot, ctrl); 780 shpchp_handle_switch_change(hp_slot, ctrl);
@@ -958,33 +958,33 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
958 } else { 958 } else {
959 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); 959 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
960 if (!ctrl->cap_offset) { 960 if (!ctrl->cap_offset) {
961 err("%s : cap_offset == 0\n", __FUNCTION__); 961 err("%s : cap_offset == 0\n", __func__);
962 goto abort; 962 goto abort;
963 } 963 }
964 dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset); 964 dbg("%s: cap_offset = %x\n", __func__, ctrl->cap_offset);
965 965
966 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); 966 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
967 if (rc) { 967 if (rc) {
968 err("%s: cannot read base_offset\n", __FUNCTION__); 968 err("%s: cannot read base_offset\n", __func__);
969 goto abort; 969 goto abort;
970 } 970 }
971 971
972 rc = shpc_indirect_read(ctrl, 3, &tempdword); 972 rc = shpc_indirect_read(ctrl, 3, &tempdword);
973 if (rc) { 973 if (rc) {
974 err("%s: cannot read slot config\n", __FUNCTION__); 974 err("%s: cannot read slot config\n", __func__);
975 goto abort; 975 goto abort;
976 } 976 }
977 num_slots = tempdword & SLOT_NUM; 977 num_slots = tempdword & SLOT_NUM;
978 dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots); 978 dbg("%s: num_slots (indirect) %x\n", __func__, num_slots);
979 979
980 for (i = 0; i < 9 + num_slots; i++) { 980 for (i = 0; i < 9 + num_slots; i++) {
981 rc = shpc_indirect_read(ctrl, i, &tempdword); 981 rc = shpc_indirect_read(ctrl, i, &tempdword);
982 if (rc) { 982 if (rc) {
983 err("%s: cannot read creg (index = %d)\n", 983 err("%s: cannot read creg (index = %d)\n",
984 __FUNCTION__, i); 984 __func__, i);
985 goto abort; 985 goto abort;
986 } 986 }
987 dbg("%s: offset %d: value %x\n", __FUNCTION__,i, 987 dbg("%s: offset %d: value %x\n", __func__,i,
988 tempdword); 988 tempdword);
989 } 989 }
990 990
@@ -998,25 +998,25 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
998 998
999 rc = pci_enable_device(pdev); 999 rc = pci_enable_device(pdev);
1000 if (rc) { 1000 if (rc) {
1001 err("%s: pci_enable_device failed\n", __FUNCTION__); 1001 err("%s: pci_enable_device failed\n", __func__);
1002 goto abort; 1002 goto abort;
1003 } 1003 }
1004 1004
1005 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { 1005 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
1006 err("%s: cannot reserve MMIO region\n", __FUNCTION__); 1006 err("%s: cannot reserve MMIO region\n", __func__);
1007 rc = -1; 1007 rc = -1;
1008 goto abort; 1008 goto abort;
1009 } 1009 }
1010 1010
1011 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); 1011 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1012 if (!ctrl->creg) { 1012 if (!ctrl->creg) {
1013 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__, 1013 err("%s: cannot remap MMIO region %lx @ %lx\n", __func__,
1014 ctrl->mmio_size, ctrl->mmio_base); 1014 ctrl->mmio_size, ctrl->mmio_base);
1015 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 1015 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1016 rc = -1; 1016 rc = -1;
1017 goto abort; 1017 goto abort;
1018 } 1018 }
1019 dbg("%s: ctrl->creg %p\n", __FUNCTION__, ctrl->creg); 1019 dbg("%s: ctrl->creg %p\n", __func__, ctrl->creg);
1020 1020
1021 mutex_init(&ctrl->crit_sect); 1021 mutex_init(&ctrl->crit_sect);
1022 mutex_init(&ctrl->cmd_lock); 1022 mutex_init(&ctrl->cmd_lock);
@@ -1035,20 +1035,20 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
1035 1035
1036 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ 1036 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1037 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1037 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1038 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 1038 dbg("%s: SERR_INTR_ENABLE = %x\n", __func__, tempdword);
1039 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 1039 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
1040 COMMAND_INTR_MASK | ARBITER_SERR_MASK); 1040 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1041 tempdword &= ~SERR_INTR_RSVDZ_MASK; 1041 tempdword &= ~SERR_INTR_RSVDZ_MASK;
1042 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 1042 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1043 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1043 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1044 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 1044 dbg("%s: SERR_INTR_ENABLE = %x\n", __func__, tempdword);
1045 1045
1046 /* Mask the MRL sensor SERR Mask of individual slot in 1046 /* Mask the MRL sensor SERR Mask of individual slot in
1047 * Slot SERR-INT Mask & clear all the existing event if any 1047 * Slot SERR-INT Mask & clear all the existing event if any
1048 */ 1048 */
1049 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 1049 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1050 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1050 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1051 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, 1051 dbg("%s: Default Logical Slot Register %d value %x\n", __func__,
1052 hp_slot, slot_reg); 1052 hp_slot, slot_reg);
1053 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1053 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1054 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1054 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
@@ -1073,7 +1073,7 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
1073 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, 1073 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
1074 MY_NAME, (void *)ctrl); 1074 MY_NAME, (void *)ctrl);
1075 dbg("%s: request_irq %d for hpc%d (returns %d)\n", 1075 dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1076 __FUNCTION__, ctrl->pci_dev->irq, 1076 __func__, ctrl->pci_dev->irq,
1077 atomic_read(&shpchp_num_controllers), rc); 1077 atomic_read(&shpchp_num_controllers), rc);
1078 if (rc) { 1078 if (rc) {
1079 err("Can't get irq %d for the hotplug controller\n", 1079 err("Can't get irq %d for the hotplug controller\n",
@@ -1081,7 +1081,7 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
1081 goto abort_iounmap; 1081 goto abort_iounmap;
1082 } 1082 }
1083 } 1083 }
1084 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__, 1084 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __func__,
1085 pdev->bus->number, PCI_SLOT(pdev->devfn), 1085 pdev->bus->number, PCI_SLOT(pdev->devfn),
1086 PCI_FUNC(pdev->devfn), pdev->irq); 1086 PCI_FUNC(pdev->devfn), pdev->irq);
1087 get_hp_hw_control_from_firmware(pdev); 1087 get_hp_hw_control_from_firmware(pdev);
@@ -1103,7 +1103,7 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
1103 */ 1103 */
1104 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 1104 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1105 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1105 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1106 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, 1106 dbg("%s: Default Logical Slot Register %d value %x\n", __func__,
1107 hp_slot, slot_reg); 1107 hp_slot, slot_reg);
1108 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1108 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1109 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1109 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
@@ -1117,7 +1117,7 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
1117 SERR_INTR_RSVDZ_MASK); 1117 SERR_INTR_RSVDZ_MASK);
1118 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 1118 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1119 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1119 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1120 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 1120 dbg("%s: SERR_INTR_ENABLE = %x\n", __func__, tempdword);
1121 } 1121 }
1122 1122
1123 return 0; 1123 return 0;