[PATCH] pciehp: reduce dependence on ACPI

Reduce the PCI Express hotplug driver's dependence on ACPI.
We don't walk the acpi namespace anymore to build a list of
bridges and devices. We go to ACPI only to run the _OSC or
_OSHP methods to transition control of hotplug hardware from
system BIOS to the hotplug driver, and to run the _HPP
method to get hotplug device parameters like cache line size,
latency timer and SERR/PERR enable from BIOS.

Note that one of the side effects of this patch is that pciehp
does not automatically enable the hot-added device or its DMA
bus mastering capability now. It expects the device driver to
do that. This may break some drivers and we will have to fix
them as they are reported.

Signed-off-by: Rajesh Shah <rajesh.shah@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 4 insertions, 103 deletions

diff --git a/drivers/pci/hotplug/pciehprm_nonacpi.c b/drivers/pci/hotplug/pciehprm_nonacpi.c
index ed68c3dd0f08..32371cd19e34 100644
--- a/drivers/pci/hotplug/pciehprm_nonacpi.c
+++ b/drivers/pci/hotplug/pciehprm_nonacpi.c
@@ -37,15 +37,9 @@
 #include <linux/slab.h>
 #include <asm/uaccess.h>
 #include "pciehp.h"
-#include "pciehprm.h"
 #include "pciehprm_nonacpi.h"
 
 
-void pciehprm_cleanup(void)
-{
-        return;
-}
-
 int pciehprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum)
 {
 
@@ -53,106 +47,13 @@ int pciehprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busn
         return 0;
 }
 
-int pciehprm_set_hpp(
-        struct controller *ctrl,
-        struct pci_func *func,
-        u8      card_type)
-{
-        u32 rc;
-        u8 temp_byte;
-        struct pci_bus lpci_bus, *pci_bus;
-        unsigned int    devfn;
-        memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
-        pci_bus = &lpci_bus;
-        pci_bus->number = func->bus;
-        devfn = PCI_DEVFN(func->device, func->function);
-
-        temp_byte = 0x40;       /* hard coded value for LT */
-        if (card_type == PCI_HEADER_TYPE_BRIDGE) {
-                /* set subordinate Latency Timer */
-                rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, temp_byte);
-
-                if (rc) {
-                        dbg("%s: set secondary LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, 
-                                func->bus, func->device, func->function);
-                        return rc;
-                }
-        }
-
-        /* set base Latency Timer */
-        rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, temp_byte);
-
-        if (rc) {
-                dbg("%s: set LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
-                return rc;
-        }
-
-        /* set Cache Line size */
-        temp_byte = 0x08;       /* hard coded value for CLS */
-
-        rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, temp_byte);
-
-        if (rc) {
-                dbg("%s: set CLS error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
-        }
-
-        /* set enable_perr */
-        /* set enable_serr */
-
-        return rc;
-}
-
-void pciehprm_enable_card(
-        struct controller *ctrl,
-        struct pci_func *func,
-        u8 card_type)
+void get_hp_params_from_firmware(struct pci_dev *dev,
+                struct hotplug_params *hpp)
 {
-        u16 command, bcommand;
-        struct pci_bus lpci_bus, *pci_bus;
-        unsigned int devfn;
-        int rc;
-
-        memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
-        pci_bus = &lpci_bus;
-        pci_bus->number = func->bus;
-        devfn = PCI_DEVFN(func->device, func->function);
-
-        rc = pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &command);
-
-        command |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR
-                | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
-                | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-
-        rc = pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
-
-        if (card_type == PCI_HEADER_TYPE_BRIDGE) {
-
-                rc = pci_bus_read_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, &bcommand);
-
-                bcommand |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR
-                        | PCI_BRIDGE_CTL_NO_ISA;
-
-                rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, bcommand);
-        }
+        return;
 }
 
-static int legacy_pciehprm_init_pci(void)
+int get_hp_hw_control_from_firmware(struct pci_dev *dev)
 {
         return 0;
 }
-
-int pciehprm_init(enum php_ctlr_type ctrl_type)
-{
-        int retval;
-
-        switch (ctrl_type) {
-        case PCI:
-                retval = legacy_pciehprm_init_pci();
-                break;
-        default:
-                retval = -ENODEV;
-                break;
-        }
-
-        return retval;
-}