Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6

* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (75 commits)
  PCI hotplug: clean up acpi_run_hpp()
  PCI hotplug: acpiphp: use generic pci_configure_slot()
  PCI hotplug: shpchp: use generic pci_configure_slot()
  PCI hotplug: pciehp: use generic pci_configure_slot()
  PCI hotplug: add pci_configure_slot()
  PCI hotplug: clean up acpi_get_hp_params_from_firmware() interface
  PCI hotplug: acpiphp: don't cache hotplug_params in acpiphp_bridge
  PCI hotplug: acpiphp: remove superfluous _HPP/_HPX evaluation
  PCI: Clear saved_state after the state has been restored
  PCI PM: Return error codes from pci_pm_resume()
  PCI: use dev_printk in quirk messages
  PCI / PCIe portdrv: Fix pcie_portdrv_slot_reset()
  PCI Hotplug: convert acpi_pci_detect_ejectable() to take an acpi_handle
  PCI Hotplug: acpiphp: find bridges the easy way
  PCI: pcie portdrv: remove unused variable
  PCI / ACPI PM: Propagate wake-up enable for devices w/o ACPI support
  ACPI PM: Replace wakeup.prepared with reference counter
  PCI PM: Introduce device flag wakeup_prepared
  PCI / ACPI PM: Rework some debug messages
  PCI PM: Simplify PCI wake-up code
  ...

Fixed up conflict in arch/powerpc/kernel/pci_64.c due to OF device tree
scanning having been moved and merged for the 32- and 64-bit cases.  The
'needs_freset' initialization added in 6e19314cc ("PCI/powerpc: support
PCIe fundamental reset") is now in arch/powerpc/kernel/pci_of_scan.c.

1 files changed, 1 insertions, 136 deletions

diff --git a/drivers/pci/hotplug/pciehp_pci.c b/drivers/pci/hotplug/pciehp_pci.c
index 10f9566cceeb..02e24d63b3ee 100644
--- a/drivers/pci/hotplug/pciehp_pci.c
+++ b/drivers/pci/hotplug/pciehp_pci.c
@@ -34,136 +34,6 @@
 #include "../pci.h"
 #include "pciehp.h"
 
-static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
-{
-        u16 pci_cmd, pci_bctl;
-
-        if (hpp->revision > 1) {
-                warn("Rev.%d type0 record not supported\n", hpp->revision);
-                return;
-        }
-
-        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
-        pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
-        pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
-        if (hpp->enable_serr)
-                pci_cmd |= PCI_COMMAND_SERR;
-        else
-                pci_cmd &= ~PCI_COMMAND_SERR;
-        if (hpp->enable_perr)
-                pci_cmd |= PCI_COMMAND_PARITY;
-        else
-                pci_cmd &= ~PCI_COMMAND_PARITY;
-        pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
-
-        /* Program bridge control value */
-        if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
-                pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
-                                      hpp->latency_timer);
-                pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
-                if (hpp->enable_serr)
-                        pci_bctl |= PCI_BRIDGE_CTL_SERR;
-                else
-                        pci_bctl &= ~PCI_BRIDGE_CTL_SERR;
-                if (hpp->enable_perr)
-                        pci_bctl |= PCI_BRIDGE_CTL_PARITY;
-                else
-                        pci_bctl &= ~PCI_BRIDGE_CTL_PARITY;
-                pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
-        }
-}
-
-static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
-{
-        int pos;
-        u16 reg16;
-        u32 reg32;
-
-        if (hpp->revision > 1) {
-                warn("Rev.%d type2 record not supported\n", hpp->revision);
-                return;
-        }
-
-        /* Find PCI Express capability */
-        pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
-        if (!pos)
-                return;
-
-        /* Initialize Device Control Register */
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16);
-        reg16 = (reg16 & hpp->pci_exp_devctl_and) | hpp->pci_exp_devctl_or;
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
-
-        /* Initialize Link Control Register */
-        if (dev->subordinate) {
-                pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &reg16);
-                reg16 = (reg16 & hpp->pci_exp_lnkctl_and)
-                        | hpp->pci_exp_lnkctl_or;
-                pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, reg16);
-        }
-
-        /* Find Advanced Error Reporting Enhanced Capability */
-        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
-        if (!pos)
-                return;
-
-        /* Initialize Uncorrectable Error Mask Register */
-        pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
-        reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
-        pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
-
-        /* Initialize Uncorrectable Error Severity Register */
-        pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
-        reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
-        pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
-
-        /* Initialize Correctable Error Mask Register */
-        pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
-        reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
-        pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
-
-        /* Initialize Advanced Error Capabilities and Control Register */
-        pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
-        reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
-        pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
-
-        /*
-         * FIXME: The following two registers are not supported yet.
-         *
-         *   o Secondary Uncorrectable Error Severity Register
-         *   o Secondary Uncorrectable Error Mask Register
-         */
-}
-
-static void program_fw_provided_values(struct pci_dev *dev)
-{
-        struct pci_dev *cdev;
-        struct hotplug_params hpp;
-
-        /* Program hpp values for this device */
-        if (!(dev->hdr_type == PCI_HEADER_TYPE_NORMAL ||
-                        (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
-                        (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
-                return;
-
-        if (pciehp_get_hp_params_from_firmware(dev, &hpp)) {
-                warn("Could not get hotplug parameters\n");
-                return;
-        }
-
-        if (hpp.t2)
-                program_hpp_type2(dev, hpp.t2);
-        if (hpp.t0)
-                program_hpp_type0(dev, hpp.t0);
-
-        /* Program child devices */
-        if (dev->subordinate) {
-                list_for_each_entry(cdev, &dev->subordinate->devices,
-                                    bus_list)
-                        program_fw_provided_values(cdev);
-        }
-}
-
 static int __ref pciehp_add_bridge(struct pci_dev *dev)
 {
         struct pci_bus *parent = dev->bus;
@@ -226,7 +96,7 @@ int pciehp_configure_device(struct slot *p_slot)
                                 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) {
                         pciehp_add_bridge(dev);
                 }
-                program_fw_provided_values(dev);
+                pci_configure_slot(dev);
                 pci_dev_put(dev);
         }
 
@@ -285,11 +155,6 @@ int pciehp_unconfigure_device(struct slot *p_slot)
                 }
                 pci_dev_put(temp);
         }
-        /*
-         * Some PCI Express root ports require fixup after hot-plug operation.
-         */
-        if (pcie_mch_quirk)
-                pci_fixup_device(pci_fixup_final, p_slot->ctrl->pci_dev);
 
         return rc;
 }