diff options
author | Taku Izumi <izumi.taku@jp.fujitsu.com> | 2008-09-04 23:11:26 -0400 |
---|---|---|
committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2008-10-20 13:53:49 -0400 |
commit | 7f2feec140f1f1e4f701e013a2bf8284a9ec2a3c (patch) | |
tree | 50a0323a4c3b74c8a428470e6b086ed8bc0b19dd /drivers/pci/hotplug/pciehp_hpc.c | |
parent | 83e9ad540b9ee23919961f9500ca254220b78d09 (diff) |
PCI: pciehp: replace printk with dev_printk
This patch replaces printks within pciehp module with dev_printks.
Signed-off-by: Taku Izumi <izumi.taku@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci/hotplug/pciehp_hpc.c')
-rw-r--r-- | drivers/pci/hotplug/pciehp_hpc.c | 197 |
1 files changed, 113 insertions, 84 deletions
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 5a5c08f12af2..8e9530c4c36d 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c | |||
@@ -235,7 +235,8 @@ static inline int pciehp_request_irq(struct controller *ctrl) | |||
235 | /* Installs the interrupt handler */ | 235 | /* Installs the interrupt handler */ |
236 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | 236 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); |
237 | if (retval) | 237 | if (retval) |
238 | err("Cannot get irq %d for the hotplug controller\n", irq); | 238 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
239 | irq); | ||
239 | return retval; | 240 | return retval; |
240 | } | 241 | } |
241 | 242 | ||
@@ -282,7 +283,7 @@ static void pcie_wait_cmd(struct controller *ctrl, int poll) | |||
282 | else | 283 | else |
283 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); | 284 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
284 | if (!rc) | 285 | if (!rc) |
285 | dbg("Command not completed in 1000 msec\n"); | 286 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
286 | } | 287 | } |
287 | 288 | ||
288 | /** | 289 | /** |
@@ -301,7 +302,8 @@ static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) | |||
301 | 302 | ||
302 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | 303 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
303 | if (retval) { | 304 | if (retval) { |
304 | err("%s: Cannot read SLOTSTATUS register\n", __func__); | 305 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
306 | __func__); | ||
305 | goto out; | 307 | goto out; |
306 | } | 308 | } |
307 | 309 | ||
@@ -312,26 +314,28 @@ static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) | |||
312 | * proceed forward to issue the next command according | 314 | * proceed forward to issue the next command according |
313 | * to spec. Just print out the error message. | 315 | * to spec. Just print out the error message. |
314 | */ | 316 | */ |
315 | dbg("%s: CMD_COMPLETED not clear after 1 sec.\n", | 317 | ctrl_dbg(ctrl, |
316 | __func__); | 318 | "%s: CMD_COMPLETED not clear after 1 sec.\n", |
319 | __func__); | ||
317 | } else if (!NO_CMD_CMPL(ctrl)) { | 320 | } else if (!NO_CMD_CMPL(ctrl)) { |
318 | /* | 321 | /* |
319 | * This controller semms to notify of command completed | 322 | * This controller semms to notify of command completed |
320 | * event even though it supports none of power | 323 | * event even though it supports none of power |
321 | * controller, attention led, power led and EMI. | 324 | * controller, attention led, power led and EMI. |
322 | */ | 325 | */ |
323 | dbg("%s: Unexpected CMD_COMPLETED. Need to wait for " | 326 | ctrl_dbg(ctrl, "%s: Unexpected CMD_COMPLETED. Need to " |
324 | "command completed event.\n", __func__); | 327 | "wait for command completed event.\n", |
328 | __func__); | ||
325 | ctrl->no_cmd_complete = 0; | 329 | ctrl->no_cmd_complete = 0; |
326 | } else { | 330 | } else { |
327 | dbg("%s: Unexpected CMD_COMPLETED. Maybe the " | 331 | ctrl_dbg(ctrl, "%s: Unexpected CMD_COMPLETED. Maybe " |
328 | "controller is broken.\n", __func__); | 332 | "the controller is broken.\n", __func__); |
329 | } | 333 | } |
330 | } | 334 | } |
331 | 335 | ||
332 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); | 336 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
333 | if (retval) { | 337 | if (retval) { |
334 | err("%s: Cannot read SLOTCTRL register\n", __func__); | 338 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
335 | goto out; | 339 | goto out; |
336 | } | 340 | } |
337 | 341 | ||
@@ -341,7 +345,8 @@ static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) | |||
341 | smp_mb(); | 345 | smp_mb(); |
342 | retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); | 346 | retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); |
343 | if (retval) | 347 | if (retval) |
344 | err("%s: Cannot write to SLOTCTRL register\n", __func__); | 348 | ctrl_err(ctrl, "%s: Cannot write to SLOTCTRL register\n", |
349 | __func__); | ||
345 | 350 | ||
346 | /* | 351 | /* |
347 | * Wait for command completion. | 352 | * Wait for command completion. |
@@ -370,14 +375,15 @@ static int hpc_check_lnk_status(struct controller *ctrl) | |||
370 | 375 | ||
371 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); | 376 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
372 | if (retval) { | 377 | if (retval) { |
373 | err("%s: Cannot read LNKSTATUS register\n", __func__); | 378 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", |
379 | __func__); | ||
374 | return retval; | 380 | return retval; |
375 | } | 381 | } |
376 | 382 | ||
377 | dbg("%s: lnk_status = %x\n", __func__, lnk_status); | 383 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
378 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || | 384 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || |
379 | !(lnk_status & NEG_LINK_WD)) { | 385 | !(lnk_status & NEG_LINK_WD)) { |
380 | err("%s : Link Training Error occurs \n", __func__); | 386 | ctrl_err(ctrl, "%s : Link Training Error occurs \n", __func__); |
381 | retval = -1; | 387 | retval = -1; |
382 | return retval; | 388 | return retval; |
383 | } | 389 | } |
@@ -394,12 +400,12 @@ static int hpc_get_attention_status(struct slot *slot, u8 *status) | |||
394 | 400 | ||
395 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); | 401 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
396 | if (retval) { | 402 | if (retval) { |
397 | err("%s: Cannot read SLOTCTRL register\n", __func__); | 403 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
398 | return retval; | 404 | return retval; |
399 | } | 405 | } |
400 | 406 | ||
401 | dbg("%s: SLOTCTRL %x, value read %x\n", | 407 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", |
402 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); | 408 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); |
403 | 409 | ||
404 | atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; | 410 | atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; |
405 | 411 | ||
@@ -433,11 +439,11 @@ static int hpc_get_power_status(struct slot *slot, u8 *status) | |||
433 | 439 | ||
434 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); | 440 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
435 | if (retval) { | 441 | if (retval) { |
436 | err("%s: Cannot read SLOTCTRL register\n", __func__); | 442 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
437 | return retval; | 443 | return retval; |
438 | } | 444 | } |
439 | dbg("%s: SLOTCTRL %x value read %x\n", | 445 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", |
440 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); | 446 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); |
441 | 447 | ||
442 | pwr_state = (slot_ctrl & PWR_CTRL) >> 10; | 448 | pwr_state = (slot_ctrl & PWR_CTRL) >> 10; |
443 | 449 | ||
@@ -464,7 +470,8 @@ static int hpc_get_latch_status(struct slot *slot, u8 *status) | |||
464 | 470 | ||
465 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | 471 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
466 | if (retval) { | 472 | if (retval) { |
467 | err("%s: Cannot read SLOTSTATUS register\n", __func__); | 473 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
474 | __func__); | ||
468 | return retval; | 475 | return retval; |
469 | } | 476 | } |
470 | 477 | ||
@@ -482,7 +489,8 @@ static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |||
482 | 489 | ||
483 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | 490 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
484 | if (retval) { | 491 | if (retval) { |
485 | err("%s: Cannot read SLOTSTATUS register\n", __func__); | 492 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
493 | __func__); | ||
486 | return retval; | 494 | return retval; |
487 | } | 495 | } |
488 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); | 496 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); |
@@ -500,7 +508,7 @@ static int hpc_query_power_fault(struct slot *slot) | |||
500 | 508 | ||
501 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | 509 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
502 | if (retval) { | 510 | if (retval) { |
503 | err("%s: Cannot check for power fault\n", __func__); | 511 | ctrl_err(ctrl, "%s: Cannot check for power fault\n", __func__); |
504 | return retval; | 512 | return retval; |
505 | } | 513 | } |
506 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); | 514 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); |
@@ -516,7 +524,7 @@ static int hpc_get_emi_status(struct slot *slot, u8 *status) | |||
516 | 524 | ||
517 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | 525 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
518 | if (retval) { | 526 | if (retval) { |
519 | err("%s : Cannot check EMI status\n", __func__); | 527 | ctrl_err(ctrl, "%s : Cannot check EMI status\n", __func__); |
520 | return retval; | 528 | return retval; |
521 | } | 529 | } |
522 | *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; | 530 | *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; |
@@ -560,8 +568,8 @@ static int hpc_set_attention_status(struct slot *slot, u8 value) | |||
560 | return -1; | 568 | return -1; |
561 | } | 569 | } |
562 | rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); | 570 | rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
563 | dbg("%s: SLOTCTRL %x write cmd %x\n", | 571 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
564 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); | 572 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
565 | 573 | ||
566 | return rc; | 574 | return rc; |
567 | } | 575 | } |
@@ -575,8 +583,8 @@ static void hpc_set_green_led_on(struct slot *slot) | |||
575 | slot_cmd = 0x0100; | 583 | slot_cmd = 0x0100; |
576 | cmd_mask = PWR_LED_CTRL; | 584 | cmd_mask = PWR_LED_CTRL; |
577 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); | 585 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
578 | dbg("%s: SLOTCTRL %x write cmd %x\n", | 586 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
579 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); | 587 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
580 | } | 588 | } |
581 | 589 | ||
582 | static void hpc_set_green_led_off(struct slot *slot) | 590 | static void hpc_set_green_led_off(struct slot *slot) |
@@ -588,8 +596,8 @@ static void hpc_set_green_led_off(struct slot *slot) | |||
588 | slot_cmd = 0x0300; | 596 | slot_cmd = 0x0300; |
589 | cmd_mask = PWR_LED_CTRL; | 597 | cmd_mask = PWR_LED_CTRL; |
590 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); | 598 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
591 | dbg("%s: SLOTCTRL %x write cmd %x\n", | 599 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
592 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); | 600 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
593 | } | 601 | } |
594 | 602 | ||
595 | static void hpc_set_green_led_blink(struct slot *slot) | 603 | static void hpc_set_green_led_blink(struct slot *slot) |
@@ -601,8 +609,8 @@ static void hpc_set_green_led_blink(struct slot *slot) | |||
601 | slot_cmd = 0x0200; | 609 | slot_cmd = 0x0200; |
602 | cmd_mask = PWR_LED_CTRL; | 610 | cmd_mask = PWR_LED_CTRL; |
603 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); | 611 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
604 | dbg("%s: SLOTCTRL %x write cmd %x\n", | 612 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
605 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); | 613 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
606 | } | 614 | } |
607 | 615 | ||
608 | static int hpc_power_on_slot(struct slot * slot) | 616 | static int hpc_power_on_slot(struct slot * slot) |
@@ -613,20 +621,22 @@ static int hpc_power_on_slot(struct slot * slot) | |||
613 | u16 slot_status; | 621 | u16 slot_status; |
614 | int retval = 0; | 622 | int retval = 0; |
615 | 623 | ||
616 | dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot); | 624 | ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot); |
617 | 625 | ||
618 | /* Clear sticky power-fault bit from previous power failures */ | 626 | /* Clear sticky power-fault bit from previous power failures */ |
619 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | 627 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
620 | if (retval) { | 628 | if (retval) { |
621 | err("%s: Cannot read SLOTSTATUS register\n", __func__); | 629 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
630 | __func__); | ||
622 | return retval; | 631 | return retval; |
623 | } | 632 | } |
624 | slot_status &= PWR_FAULT_DETECTED; | 633 | slot_status &= PWR_FAULT_DETECTED; |
625 | if (slot_status) { | 634 | if (slot_status) { |
626 | retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status); | 635 | retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status); |
627 | if (retval) { | 636 | if (retval) { |
628 | err("%s: Cannot write to SLOTSTATUS register\n", | 637 | ctrl_err(ctrl, |
629 | __func__); | 638 | "%s: Cannot write to SLOTSTATUS register\n", |
639 | __func__); | ||
630 | return retval; | 640 | return retval; |
631 | } | 641 | } |
632 | } | 642 | } |
@@ -644,11 +654,12 @@ static int hpc_power_on_slot(struct slot * slot) | |||
644 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); | 654 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
645 | 655 | ||
646 | if (retval) { | 656 | if (retval) { |
647 | err("%s: Write %x command failed!\n", __func__, slot_cmd); | 657 | ctrl_err(ctrl, "%s: Write %x command failed!\n", |
658 | __func__, slot_cmd); | ||
648 | return -1; | 659 | return -1; |
649 | } | 660 | } |
650 | dbg("%s: SLOTCTRL %x write cmd %x\n", | 661 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
651 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); | 662 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
652 | 663 | ||
653 | return retval; | 664 | return retval; |
654 | } | 665 | } |
@@ -694,7 +705,7 @@ static int hpc_power_off_slot(struct slot * slot) | |||
694 | int retval = 0; | 705 | int retval = 0; |
695 | int changed; | 706 | int changed; |
696 | 707 | ||
697 | dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot); | 708 | ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot); |
698 | 709 | ||
699 | /* | 710 | /* |
700 | * Set Bad DLLP Mask bit in Correctable Error Mask | 711 | * Set Bad DLLP Mask bit in Correctable Error Mask |
@@ -722,12 +733,12 @@ static int hpc_power_off_slot(struct slot * slot) | |||
722 | 733 | ||
723 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); | 734 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
724 | if (retval) { | 735 | if (retval) { |
725 | err("%s: Write command failed!\n", __func__); | 736 | ctrl_err(ctrl, "%s: Write command failed!\n", __func__); |
726 | retval = -1; | 737 | retval = -1; |
727 | goto out; | 738 | goto out; |
728 | } | 739 | } |
729 | dbg("%s: SLOTCTRL %x write cmd %x\n", | 740 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
730 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); | 741 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
731 | out: | 742 | out: |
732 | if (changed) | 743 | if (changed) |
733 | pcie_unmask_bad_dllp(ctrl); | 744 | pcie_unmask_bad_dllp(ctrl); |
@@ -749,7 +760,8 @@ static irqreturn_t pcie_isr(int irq, void *dev_id) | |||
749 | intr_loc = 0; | 760 | intr_loc = 0; |
750 | do { | 761 | do { |
751 | if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) { | 762 | if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) { |
752 | err("%s: Cannot read SLOTSTATUS\n", __func__); | 763 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", |
764 | __func__); | ||
753 | return IRQ_NONE; | 765 | return IRQ_NONE; |
754 | } | 766 | } |
755 | 767 | ||
@@ -760,12 +772,13 @@ static irqreturn_t pcie_isr(int irq, void *dev_id) | |||
760 | if (!intr_loc) | 772 | if (!intr_loc) |
761 | return IRQ_NONE; | 773 | return IRQ_NONE; |
762 | if (detected && pciehp_writew(ctrl, SLOTSTATUS, detected)) { | 774 | if (detected && pciehp_writew(ctrl, SLOTSTATUS, detected)) { |
763 | err("%s: Cannot write to SLOTSTATUS\n", __func__); | 775 | ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", |
776 | __func__); | ||
764 | return IRQ_NONE; | 777 | return IRQ_NONE; |
765 | } | 778 | } |
766 | } while (detected); | 779 | } while (detected); |
767 | 780 | ||
768 | dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc); | 781 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
769 | 782 | ||
770 | /* Check Command Complete Interrupt Pending */ | 783 | /* Check Command Complete Interrupt Pending */ |
771 | if (intr_loc & CMD_COMPLETED) { | 784 | if (intr_loc & CMD_COMPLETED) { |
@@ -807,7 +820,7 @@ static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value) | |||
807 | 820 | ||
808 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); | 821 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
809 | if (retval) { | 822 | if (retval) { |
810 | err("%s: Cannot read LNKCAP register\n", __func__); | 823 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
811 | return retval; | 824 | return retval; |
812 | } | 825 | } |
813 | 826 | ||
@@ -821,7 +834,7 @@ static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value) | |||
821 | } | 834 | } |
822 | 835 | ||
823 | *value = lnk_speed; | 836 | *value = lnk_speed; |
824 | dbg("Max link speed = %d\n", lnk_speed); | 837 | ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed); |
825 | 838 | ||
826 | return retval; | 839 | return retval; |
827 | } | 840 | } |
@@ -836,7 +849,7 @@ static int hpc_get_max_lnk_width(struct slot *slot, | |||
836 | 849 | ||
837 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); | 850 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
838 | if (retval) { | 851 | if (retval) { |
839 | err("%s: Cannot read LNKCAP register\n", __func__); | 852 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
840 | return retval; | 853 | return retval; |
841 | } | 854 | } |
842 | 855 | ||
@@ -871,7 +884,7 @@ static int hpc_get_max_lnk_width(struct slot *slot, | |||
871 | } | 884 | } |
872 | 885 | ||
873 | *value = lnk_wdth; | 886 | *value = lnk_wdth; |
874 | dbg("Max link width = %d\n", lnk_wdth); | 887 | ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); |
875 | 888 | ||
876 | return retval; | 889 | return retval; |
877 | } | 890 | } |
@@ -885,7 +898,8 @@ static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value) | |||
885 | 898 | ||
886 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); | 899 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
887 | if (retval) { | 900 | if (retval) { |
888 | err("%s: Cannot read LNKSTATUS register\n", __func__); | 901 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", |
902 | __func__); | ||
889 | return retval; | 903 | return retval; |
890 | } | 904 | } |
891 | 905 | ||
@@ -899,7 +913,7 @@ static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value) | |||
899 | } | 913 | } |
900 | 914 | ||
901 | *value = lnk_speed; | 915 | *value = lnk_speed; |
902 | dbg("Current link speed = %d\n", lnk_speed); | 916 | ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed); |
903 | 917 | ||
904 | return retval; | 918 | return retval; |
905 | } | 919 | } |
@@ -914,7 +928,8 @@ static int hpc_get_cur_lnk_width(struct slot *slot, | |||
914 | 928 | ||
915 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); | 929 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
916 | if (retval) { | 930 | if (retval) { |
917 | err("%s: Cannot read LNKSTATUS register\n", __func__); | 931 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", |
932 | __func__); | ||
918 | return retval; | 933 | return retval; |
919 | } | 934 | } |
920 | 935 | ||
@@ -949,7 +964,7 @@ static int hpc_get_cur_lnk_width(struct slot *slot, | |||
949 | } | 964 | } |
950 | 965 | ||
951 | *value = lnk_wdth; | 966 | *value = lnk_wdth; |
952 | dbg("Current link width = %d\n", lnk_wdth); | 967 | ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); |
953 | 968 | ||
954 | return retval; | 969 | return retval; |
955 | } | 970 | } |
@@ -998,7 +1013,8 @@ int pcie_enable_notification(struct controller *ctrl) | |||
998 | PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; | 1013 | PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; |
999 | 1014 | ||
1000 | if (pcie_write_cmd(ctrl, cmd, mask)) { | 1015 | if (pcie_write_cmd(ctrl, cmd, mask)) { |
1001 | err("%s: Cannot enable software notification\n", __func__); | 1016 | ctrl_err(ctrl, "%s: Cannot enable software notification\n", |
1017 | __func__); | ||
1002 | return -1; | 1018 | return -1; |
1003 | } | 1019 | } |
1004 | return 0; | 1020 | return 0; |
@@ -1010,7 +1026,8 @@ static void pcie_disable_notification(struct controller *ctrl) | |||
1010 | mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE | | 1026 | mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE | |
1011 | PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; | 1027 | PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; |
1012 | if (pcie_write_cmd(ctrl, 0, mask)) | 1028 | if (pcie_write_cmd(ctrl, 0, mask)) |
1013 | warn("%s: Cannot disable software notification\n", __func__); | 1029 | ctrl_warn(ctrl, "%s: Cannot disable software notification\n", |
1030 | __func__); | ||
1014 | } | 1031 | } |
1015 | 1032 | ||
1016 | static int pcie_init_notification(struct controller *ctrl) | 1033 | static int pcie_init_notification(struct controller *ctrl) |
@@ -1071,34 +1088,45 @@ static inline void dbg_ctrl(struct controller *ctrl) | |||
1071 | if (!pciehp_debug) | 1088 | if (!pciehp_debug) |
1072 | return; | 1089 | return; |
1073 | 1090 | ||
1074 | dbg("Hotplug Controller:\n"); | 1091 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
1075 | dbg(" Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", pci_name(pdev), pdev->irq); | 1092 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", |
1076 | dbg(" Vendor ID : 0x%04x\n", pdev->vendor); | 1093 | pci_name(pdev), pdev->irq); |
1077 | dbg(" Device ID : 0x%04x\n", pdev->device); | 1094 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); |
1078 | dbg(" Subsystem ID : 0x%04x\n", pdev->subsystem_device); | 1095 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); |
1079 | dbg(" Subsystem Vendor ID : 0x%04x\n", pdev->subsystem_vendor); | 1096 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", |
1080 | dbg(" PCIe Cap offset : 0x%02x\n", ctrl->cap_base); | 1097 | pdev->subsystem_device); |
1098 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", | ||
1099 | pdev->subsystem_vendor); | ||
1100 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", ctrl->cap_base); | ||
1081 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | 1101 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
1082 | if (!pci_resource_len(pdev, i)) | 1102 | if (!pci_resource_len(pdev, i)) |
1083 | continue; | 1103 | continue; |
1084 | dbg(" PCI resource [%d] : 0x%llx@0x%llx\n", i, | 1104 | ctrl_info(ctrl, " PCI resource [%d] : 0x%llx@0x%llx\n", |
1085 | (unsigned long long)pci_resource_len(pdev, i), | 1105 | i, (unsigned long long)pci_resource_len(pdev, i), |
1086 | (unsigned long long)pci_resource_start(pdev, i)); | 1106 | (unsigned long long)pci_resource_start(pdev, i)); |
1087 | } | 1107 | } |
1088 | dbg("Slot Capabilities : 0x%08x\n", ctrl->slot_cap); | 1108 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
1089 | dbg(" Physical Slot Number : %d\n", ctrl->first_slot); | 1109 | ctrl_info(ctrl, " Physical Slot Number : %d\n", ctrl->first_slot); |
1090 | dbg(" Attention Button : %3s\n", ATTN_BUTTN(ctrl) ? "yes" : "no"); | 1110 | ctrl_info(ctrl, " Attention Button : %3s\n", |
1091 | dbg(" Power Controller : %3s\n", POWER_CTRL(ctrl) ? "yes" : "no"); | 1111 | ATTN_BUTTN(ctrl) ? "yes" : "no"); |
1092 | dbg(" MRL Sensor : %3s\n", MRL_SENS(ctrl) ? "yes" : "no"); | 1112 | ctrl_info(ctrl, " Power Controller : %3s\n", |
1093 | dbg(" Attention Indicator : %3s\n", ATTN_LED(ctrl) ? "yes" : "no"); | 1113 | POWER_CTRL(ctrl) ? "yes" : "no"); |
1094 | dbg(" Power Indicator : %3s\n", PWR_LED(ctrl) ? "yes" : "no"); | 1114 | ctrl_info(ctrl, " MRL Sensor : %3s\n", |
1095 | dbg(" Hot-Plug Surprise : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no"); | 1115 | MRL_SENS(ctrl) ? "yes" : "no"); |
1096 | dbg(" EMI Present : %3s\n", EMI(ctrl) ? "yes" : "no"); | 1116 | ctrl_info(ctrl, " Attention Indicator : %3s\n", |
1097 | dbg(" Command Completed : %3s\n", NO_CMD_CMPL(ctrl)? "no" : "yes"); | 1117 | ATTN_LED(ctrl) ? "yes" : "no"); |
1118 | ctrl_info(ctrl, " Power Indicator : %3s\n", | ||
1119 | PWR_LED(ctrl) ? "yes" : "no"); | ||
1120 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", | ||
1121 | HP_SUPR_RM(ctrl) ? "yes" : "no"); | ||
1122 | ctrl_info(ctrl, " EMI Present : %3s\n", | ||
1123 | EMI(ctrl) ? "yes" : "no"); | ||
1124 | ctrl_info(ctrl, " Command Completed : %3s\n", | ||
1125 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | ||
1098 | pciehp_readw(ctrl, SLOTSTATUS, ®16); | 1126 | pciehp_readw(ctrl, SLOTSTATUS, ®16); |
1099 | dbg("Slot Status : 0x%04x\n", reg16); | 1127 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
1100 | pciehp_readw(ctrl, SLOTCTRL, ®16); | 1128 | pciehp_readw(ctrl, SLOTCTRL, ®16); |
1101 | dbg("Slot Control : 0x%04x\n", reg16); | 1129 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
1102 | } | 1130 | } |
1103 | 1131 | ||
1104 | struct controller *pcie_init(struct pcie_device *dev) | 1132 | struct controller *pcie_init(struct pcie_device *dev) |
@@ -1109,7 +1137,7 @@ struct controller *pcie_init(struct pcie_device *dev) | |||
1109 | 1137 | ||
1110 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); | 1138 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
1111 | if (!ctrl) { | 1139 | if (!ctrl) { |
1112 | err("%s : out of memory\n", __func__); | 1140 | dev_err(&dev->device, "%s : out of memory\n", __func__); |
1113 | goto abort; | 1141 | goto abort; |
1114 | } | 1142 | } |
1115 | INIT_LIST_HEAD(&ctrl->slot_list); | 1143 | INIT_LIST_HEAD(&ctrl->slot_list); |
@@ -1118,11 +1146,12 @@ struct controller *pcie_init(struct pcie_device *dev) | |||
1118 | ctrl->pci_dev = pdev; | 1146 | ctrl->pci_dev = pdev; |
1119 | ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); | 1147 | ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
1120 | if (!ctrl->cap_base) { | 1148 | if (!ctrl->cap_base) { |
1121 | err("%s: Cannot find PCI Express capability\n", __func__); | 1149 | ctrl_err(ctrl, "%s: Cannot find PCI Express capability\n", |
1150 | __func__); | ||
1122 | goto abort; | 1151 | goto abort; |
1123 | } | 1152 | } |
1124 | if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) { | 1153 | if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) { |
1125 | err("%s: Cannot read SLOTCAP register\n", __func__); | 1154 | ctrl_err(ctrl, "%s: Cannot read SLOTCAP register\n", __func__); |
1126 | goto abort; | 1155 | goto abort; |
1127 | } | 1156 | } |
1128 | 1157 | ||
@@ -1162,9 +1191,9 @@ struct controller *pcie_init(struct pcie_device *dev) | |||
1162 | goto abort_ctrl; | 1191 | goto abort_ctrl; |
1163 | } | 1192 | } |
1164 | 1193 | ||
1165 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", | 1194 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
1166 | pdev->vendor, pdev->device, | 1195 | pdev->vendor, pdev->device, pdev->subsystem_vendor, |
1167 | pdev->subsystem_vendor, pdev->subsystem_device); | 1196 | pdev->subsystem_device); |
1168 | 1197 | ||
1169 | if (pcie_init_slot(ctrl)) | 1198 | if (pcie_init_slot(ctrl)) |
1170 | goto abort_ctrl; | 1199 | goto abort_ctrl; |