diff options
author | Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> | 2008-04-25 17:39:06 -0400 |
---|---|---|
committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2008-04-25 17:39:06 -0400 |
commit | ae416e6b2936fdb70aeee6eb9066115d4521daa6 (patch) | |
tree | 697673ed483f1d39e654b54081eb5306df41e91a /drivers/pci/hotplug/pciehp.h | |
parent | c27fb883dffe11aa4cb35ecea1fa1832ba45d4da (diff) |
pciehp: Fix wrong slot capability check
Current pciehp saves only 8bits of Slot Capability registers in
ctrl->ctrlcap. But it refers more than 8bit for checking EMI capability.
It is clearly a bug and EMI would never work. To fix this problem,
this patch saves full Slot Capability contens in ctrl->slot_cap. It also
reduce the redundant reads of Slot Capability register. And this pach
also cleans up the macros to check the slot capabilitys (e.g. MRL_SENS(),
and so on).
Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci/hotplug/pciehp.h')
-rw-r--r-- | drivers/pci/hotplug/pciehp.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h index 9dd132925ffa..8264a7680435 100644 --- a/drivers/pci/hotplug/pciehp.h +++ b/drivers/pci/hotplug/pciehp.h | |||
@@ -93,7 +93,7 @@ struct controller { | |||
93 | u8 slot_device_offset; | 93 | u8 slot_device_offset; |
94 | u32 first_slot; /* First physical slot number */ /* PCIE only has 1 slot */ | 94 | u32 first_slot; /* First physical slot number */ /* PCIE only has 1 slot */ |
95 | u8 slot_bus; /* Bus where the slots handled by this controller sit */ | 95 | u8 slot_bus; /* Bus where the slots handled by this controller sit */ |
96 | u8 ctrlcap; | 96 | u32 slot_cap; |
97 | u8 cap_base; | 97 | u8 cap_base; |
98 | struct timer_list poll_timer; | 98 | struct timer_list poll_timer; |
99 | volatile int cmd_busy; | 99 | volatile int cmd_busy; |
@@ -136,13 +136,13 @@ struct controller { | |||
136 | #define HP_SUPR_RM_SUP 0x00000020 | 136 | #define HP_SUPR_RM_SUP 0x00000020 |
137 | #define EMI_PRSN 0x00020000 | 137 | #define EMI_PRSN 0x00020000 |
138 | 138 | ||
139 | #define ATTN_BUTTN(cap) (cap & ATTN_BUTTN_PRSN) | 139 | #define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & ATTN_BUTTN_PRSN) |
140 | #define POWER_CTRL(cap) (cap & PWR_CTRL_PRSN) | 140 | #define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PWR_CTRL_PRSN) |
141 | #define MRL_SENS(cap) (cap & MRL_SENS_PRSN) | 141 | #define MRL_SENS(ctrl) ((ctrl)->slot_cap & MRL_SENS_PRSN) |
142 | #define ATTN_LED(cap) (cap & ATTN_LED_PRSN) | 142 | #define ATTN_LED(ctrl) ((ctrl)->slot_cap & ATTN_LED_PRSN) |
143 | #define PWR_LED(cap) (cap & PWR_LED_PRSN) | 143 | #define PWR_LED(ctrl) ((ctrl)->slot_cap & PWR_LED_PRSN) |
144 | #define HP_SUPR_RM(cap) (cap & HP_SUPR_RM_SUP) | 144 | #define HP_SUPR_RM(ctrl) ((ctrl)->slot_cap & HP_SUPR_RM_SUP) |
145 | #define EMI(cap) (cap & EMI_PRSN) | 145 | #define EMI(ctrl) ((ctrl)->slot_cap & EMI_PRSN) |
146 | 146 | ||
147 | extern int pciehp_sysfs_enable_slot(struct slot *slot); | 147 | extern int pciehp_sysfs_enable_slot(struct slot *slot); |
148 | extern int pciehp_sysfs_disable_slot(struct slot *slot); | 148 | extern int pciehp_sysfs_disable_slot(struct slot *slot); |