diff options
author | Alex Chiang <achiang@hp.com> | 2009-03-31 11:23:16 -0400 |
---|---|---|
committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2009-06-11 15:04:08 -0400 |
commit | 427438c61b0083a60bb953cb36cfdc5841f0bb03 (patch) | |
tree | 4583b0f23eed091006324bc1f3f61ed7fcd8a7ac /drivers/pci/hotplug/cpqphp_pci.c | |
parent | 861fefbf550d41e7a4f44584f3ec35977fa08bf1 (diff) |
PCI Hotplug: cpqphp: fix comment style
Fix up comments from C++ to C-style, wrapping if necessary, etc.
Signed-off-by: Alex Chiang <achiang@hp.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci/hotplug/cpqphp_pci.c')
-rw-r--r-- | drivers/pci/hotplug/cpqphp_pci.c | 313 |
1 files changed, 173 insertions, 140 deletions
diff --git a/drivers/pci/hotplug/cpqphp_pci.c b/drivers/pci/hotplug/cpqphp_pci.c index 573a2702fb6a..2e96bae3c82a 100644 --- a/drivers/pci/hotplug/cpqphp_pci.c +++ b/drivers/pci/hotplug/cpqphp_pci.c | |||
@@ -178,17 +178,17 @@ int cpqhp_set_irq (u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num) | |||
178 | if (!rc) | 178 | if (!rc) |
179 | return !rc; | 179 | return !rc; |
180 | 180 | ||
181 | // set the Edge Level Control Register (ELCR) | 181 | /* set the Edge Level Control Register (ELCR) */ |
182 | temp_word = inb(0x4d0); | 182 | temp_word = inb(0x4d0); |
183 | temp_word |= inb(0x4d1) << 8; | 183 | temp_word |= inb(0x4d1) << 8; |
184 | 184 | ||
185 | temp_word |= 0x01 << irq_num; | 185 | temp_word |= 0x01 << irq_num; |
186 | 186 | ||
187 | // This should only be for x86 as it sets the Edge Level Control Register | 187 | /* This should only be for x86 as it sets the Edge Level |
188 | outb((u8) (temp_word & 0xFF), 0x4d0); | 188 | * Control Register |
189 | outb((u8) ((temp_word & 0xFF00) >> 8), 0x4d1); | 189 | */ |
190 | rc = 0; | 190 | outb((u8) (temp_word & 0xFF), 0x4d0); outb((u8) ((temp_word & |
191 | } | 191 | 0xFF00) >> 8), 0x4d1); rc = 0; } |
192 | 192 | ||
193 | return rc; | 193 | return rc; |
194 | } | 194 | } |
@@ -213,11 +213,11 @@ static int PCI_ScanBusForNonBridge(struct controller *ctrl, u8 bus_num, u8 * dev | |||
213 | ctrl->pci_bus->number = bus_num; | 213 | ctrl->pci_bus->number = bus_num; |
214 | 214 | ||
215 | for (tdevice = 0; tdevice < 0xFF; tdevice++) { | 215 | for (tdevice = 0; tdevice < 0xFF; tdevice++) { |
216 | //Scan for access first | 216 | /* Scan for access first */ |
217 | if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1) | 217 | if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1) |
218 | continue; | 218 | continue; |
219 | dbg("Looking for nonbridge bus_num %d dev_num %d\n", bus_num, tdevice); | 219 | dbg("Looking for nonbridge bus_num %d dev_num %d\n", bus_num, tdevice); |
220 | //Yep we got one. Not a bridge ? | 220 | /* Yep we got one. Not a bridge ? */ |
221 | if ((work >> 8) != PCI_TO_PCI_BRIDGE_CLASS) { | 221 | if ((work >> 8) != PCI_TO_PCI_BRIDGE_CLASS) { |
222 | *dev_num = tdevice; | 222 | *dev_num = tdevice; |
223 | dbg("found it !\n"); | 223 | dbg("found it !\n"); |
@@ -225,11 +225,11 @@ static int PCI_ScanBusForNonBridge(struct controller *ctrl, u8 bus_num, u8 * dev | |||
225 | } | 225 | } |
226 | } | 226 | } |
227 | for (tdevice = 0; tdevice < 0xFF; tdevice++) { | 227 | for (tdevice = 0; tdevice < 0xFF; tdevice++) { |
228 | //Scan for access first | 228 | /* Scan for access first */ |
229 | if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1) | 229 | if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1) |
230 | continue; | 230 | continue; |
231 | dbg("Looking for bridge bus_num %d dev_num %d\n", bus_num, tdevice); | 231 | dbg("Looking for bridge bus_num %d dev_num %d\n", bus_num, tdevice); |
232 | //Yep we got one. bridge ? | 232 | /* Yep we got one. bridge ? */ |
233 | if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) { | 233 | if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) { |
234 | pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus); | 234 | pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus); |
235 | dbg("Recurse on bus_num %d tdevice %d\n", tbus, tdevice); | 235 | dbg("Recurse on bus_num %d tdevice %d\n", tbus, tdevice); |
@@ -257,7 +257,7 @@ static int PCI_GetBusDevHelper(struct controller *ctrl, u8 *bus_num, u8 *dev_num | |||
257 | 257 | ||
258 | len = (PCIIRQRoutingInfoLength->size - | 258 | len = (PCIIRQRoutingInfoLength->size - |
259 | sizeof(struct irq_routing_table)) / sizeof(struct irq_info); | 259 | sizeof(struct irq_routing_table)) / sizeof(struct irq_info); |
260 | // Make sure I got at least one entry | 260 | /* Make sure I got at least one entry */ |
261 | if (len == 0) { | 261 | if (len == 0) { |
262 | kfree(PCIIRQRoutingInfoLength ); | 262 | kfree(PCIIRQRoutingInfoLength ); |
263 | return -1; | 263 | return -1; |
@@ -304,11 +304,14 @@ static int PCI_GetBusDevHelper(struct controller *ctrl, u8 *bus_num, u8 *dev_num | |||
304 | 304 | ||
305 | int cpqhp_get_bus_dev (struct controller *ctrl, u8 * bus_num, u8 * dev_num, u8 slot) | 305 | int cpqhp_get_bus_dev (struct controller *ctrl, u8 * bus_num, u8 * dev_num, u8 slot) |
306 | { | 306 | { |
307 | return PCI_GetBusDevHelper(ctrl, bus_num, dev_num, slot, 0); //plain (bridges allowed) | 307 | /* plain (bridges allowed) */ |
308 | return PCI_GetBusDevHelper(ctrl, bus_num, dev_num, slot, 0); | ||
308 | } | 309 | } |
309 | 310 | ||
310 | 311 | ||
311 | /* More PCI configuration routines; this time centered around hotplug controller */ | 312 | /* More PCI configuration routines; this time centered around hotplug |
313 | * controller | ||
314 | */ | ||
312 | 315 | ||
313 | 316 | ||
314 | /* | 317 | /* |
@@ -339,12 +342,12 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) | |||
339 | int stop_it; | 342 | int stop_it; |
340 | int index; | 343 | int index; |
341 | 344 | ||
342 | // Decide which slots are supported | 345 | /* Decide which slots are supported */ |
343 | 346 | ||
344 | if (is_hot_plug) { | 347 | if (is_hot_plug) { |
345 | //********************************* | 348 | /* |
346 | // is_hot_plug is the slot mask | 349 | * is_hot_plug is the slot mask |
347 | //********************************* | 350 | */ |
348 | FirstSupported = is_hot_plug >> 4; | 351 | FirstSupported = is_hot_plug >> 4; |
349 | LastSupported = FirstSupported + (is_hot_plug & 0x0F) - 1; | 352 | LastSupported = FirstSupported + (is_hot_plug & 0x0F) - 1; |
350 | } else { | 353 | } else { |
@@ -352,13 +355,13 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) | |||
352 | LastSupported = 0x1F; | 355 | LastSupported = 0x1F; |
353 | } | 356 | } |
354 | 357 | ||
355 | // Save PCI configuration space for all devices in supported slots | 358 | /* Save PCI configuration space for all devices in supported slots */ |
356 | ctrl->pci_bus->number = busnumber; | 359 | ctrl->pci_bus->number = busnumber; |
357 | for (device = FirstSupported; device <= LastSupported; device++) { | 360 | for (device = FirstSupported; device <= LastSupported; device++) { |
358 | ID = 0xFFFFFFFF; | 361 | ID = 0xFFFFFFFF; |
359 | rc = pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID); | 362 | rc = pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID); |
360 | 363 | ||
361 | if (ID != 0xFFFFFFFF) { // device in slot | 364 | if (ID != 0xFFFFFFFF) { /* device in slot */ |
362 | rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(device, 0), 0x0B, &class_code); | 365 | rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(device, 0), 0x0B, &class_code); |
363 | if (rc) | 366 | if (rc) |
364 | return rc; | 367 | return rc; |
@@ -367,7 +370,7 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) | |||
367 | if (rc) | 370 | if (rc) |
368 | return rc; | 371 | return rc; |
369 | 372 | ||
370 | // If multi-function device, set max_functions to 8 | 373 | /* If multi-function device, set max_functions to 8 */ |
371 | if (header_type & 0x80) | 374 | if (header_type & 0x80) |
372 | max_functions = 8; | 375 | max_functions = 8; |
373 | else | 376 | else |
@@ -377,18 +380,19 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) | |||
377 | 380 | ||
378 | do { | 381 | do { |
379 | DevError = 0; | 382 | DevError = 0; |
380 | 383 | if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { | |
381 | if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { // P-P Bridge | 384 | /* Recurse the subordinate bus |
382 | // Recurse the subordinate bus | 385 | * get the subordinate bus number |
383 | // get the subordinate bus number | 386 | */ |
384 | rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(device, function), PCI_SECONDARY_BUS, &secondary_bus); | 387 | rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(device, function), PCI_SECONDARY_BUS, &secondary_bus); |
385 | if (rc) { | 388 | if (rc) { |
386 | return rc; | 389 | return rc; |
387 | } else { | 390 | } else { |
388 | sub_bus = (int) secondary_bus; | 391 | sub_bus = (int) secondary_bus; |
389 | 392 | ||
390 | // Save secondary bus cfg spc | 393 | /* Save secondary bus cfg spc |
391 | // with this recursive call. | 394 | * with this recursive call. |
395 | */ | ||
392 | rc = cpqhp_save_config(ctrl, sub_bus, 0); | 396 | rc = cpqhp_save_config(ctrl, sub_bus, 0); |
393 | if (rc) | 397 | if (rc) |
394 | return rc; | 398 | return rc; |
@@ -403,7 +407,7 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) | |||
403 | new_slot = cpqhp_slot_find(busnumber, device, index++); | 407 | new_slot = cpqhp_slot_find(busnumber, device, index++); |
404 | 408 | ||
405 | if (!new_slot) { | 409 | if (!new_slot) { |
406 | // Setup slot structure. | 410 | /* Setup slot structure. */ |
407 | new_slot = cpqhp_slot_create(busnumber); | 411 | new_slot = cpqhp_slot_create(busnumber); |
408 | 412 | ||
409 | if (new_slot == NULL) | 413 | if (new_slot == NULL) |
@@ -415,7 +419,7 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) | |||
415 | new_slot->function = (u8) function; | 419 | new_slot->function = (u8) function; |
416 | new_slot->is_a_board = 1; | 420 | new_slot->is_a_board = 1; |
417 | new_slot->switch_save = 0x10; | 421 | new_slot->switch_save = 0x10; |
418 | // In case of unsupported board | 422 | /* In case of unsupported board */ |
419 | new_slot->status = DevError; | 423 | new_slot->status = DevError; |
420 | new_slot->pci_dev = pci_find_slot(new_slot->bus, (new_slot->device << 3) | new_slot->function); | 424 | new_slot->pci_dev = pci_find_slot(new_slot->bus, (new_slot->device << 3) | new_slot->function); |
421 | 425 | ||
@@ -429,14 +433,15 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) | |||
429 | 433 | ||
430 | stop_it = 0; | 434 | stop_it = 0; |
431 | 435 | ||
432 | // this loop skips to the next present function | 436 | /* this loop skips to the next present function |
433 | // reading in Class Code and Header type. | 437 | * reading in Class Code and Header type. |
438 | */ | ||
434 | 439 | ||
435 | while ((function < max_functions)&&(!stop_it)) { | 440 | while ((function < max_functions)&&(!stop_it)) { |
436 | rc = pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(device, function), PCI_VENDOR_ID, &ID); | 441 | rc = pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(device, function), PCI_VENDOR_ID, &ID); |
437 | if (ID == 0xFFFFFFFF) { // nothing there. | 442 | if (ID == 0xFFFFFFFF) { /* nothing there. */ |
438 | function++; | 443 | function++; |
439 | } else { // Something there | 444 | } else { /* Something there */ |
440 | rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(device, function), 0x0B, &class_code); | 445 | rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(device, function), 0x0B, &class_code); |
441 | if (rc) | 446 | if (rc) |
442 | return rc; | 447 | return rc; |
@@ -450,9 +455,9 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) | |||
450 | } | 455 | } |
451 | 456 | ||
452 | } while (function < max_functions); | 457 | } while (function < max_functions); |
453 | } // End of IF (device in slot?) | 458 | } /* End of IF (device in slot?) */ |
454 | else if (is_hot_plug) { | 459 | else if (is_hot_plug) { |
455 | // Setup slot structure with entry for empty slot | 460 | /* Setup slot structure with entry for empty slot */ |
456 | new_slot = cpqhp_slot_create(busnumber); | 461 | new_slot = cpqhp_slot_create(busnumber); |
457 | 462 | ||
458 | if (new_slot == NULL) { | 463 | if (new_slot == NULL) { |
@@ -466,7 +471,7 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) | |||
466 | new_slot->presence_save = 0; | 471 | new_slot->presence_save = 0; |
467 | new_slot->switch_save = 0; | 472 | new_slot->switch_save = 0; |
468 | } | 473 | } |
469 | } // End of FOR loop | 474 | } /* End of FOR loop */ |
470 | 475 | ||
471 | return(0); | 476 | return(0); |
472 | } | 477 | } |
@@ -498,11 +503,11 @@ int cpqhp_save_slot_config (struct controller *ctrl, struct pci_func * new_slot) | |||
498 | ctrl->pci_bus->number = new_slot->bus; | 503 | ctrl->pci_bus->number = new_slot->bus; |
499 | pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID); | 504 | pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID); |
500 | 505 | ||
501 | if (ID != 0xFFFFFFFF) { // device in slot | 506 | if (ID != 0xFFFFFFFF) { /* device in slot */ |
502 | pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code); | 507 | pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code); |
503 | pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type); | 508 | pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type); |
504 | 509 | ||
505 | if (header_type & 0x80) // Multi-function device | 510 | if (header_type & 0x80) /* Multi-function device */ |
506 | max_functions = 8; | 511 | max_functions = 8; |
507 | else | 512 | else |
508 | max_functions = 1; | 513 | max_functions = 1; |
@@ -510,19 +515,21 @@ int cpqhp_save_slot_config (struct controller *ctrl, struct pci_func * new_slot) | |||
510 | function = 0; | 515 | function = 0; |
511 | 516 | ||
512 | do { | 517 | do { |
513 | if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { // PCI-PCI Bridge | 518 | if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { |
514 | // Recurse the subordinate bus | 519 | /* Recurse the subordinate bus */ |
515 | pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus); | 520 | pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus); |
516 | 521 | ||
517 | sub_bus = (int) secondary_bus; | 522 | sub_bus = (int) secondary_bus; |
518 | 523 | ||
519 | // Save the config headers for the secondary bus. | 524 | /* Save the config headers for the secondary |
525 | * bus. | ||
526 | */ | ||
520 | rc = cpqhp_save_config(ctrl, sub_bus, 0); | 527 | rc = cpqhp_save_config(ctrl, sub_bus, 0); |
521 | if (rc) | 528 | if (rc) |
522 | return(rc); | 529 | return(rc); |
523 | ctrl->pci_bus->number = new_slot->bus; | 530 | ctrl->pci_bus->number = new_slot->bus; |
524 | 531 | ||
525 | } // End of IF | 532 | } /* End of IF */ |
526 | 533 | ||
527 | new_slot->status = 0; | 534 | new_slot->status = 0; |
528 | 535 | ||
@@ -534,15 +541,15 @@ int cpqhp_save_slot_config (struct controller *ctrl, struct pci_func * new_slot) | |||
534 | 541 | ||
535 | stop_it = 0; | 542 | stop_it = 0; |
536 | 543 | ||
537 | // this loop skips to the next present function | 544 | /* this loop skips to the next present function |
538 | // reading in the Class Code and the Header type. | 545 | * reading in the Class Code and the Header type. |
539 | 546 | */ | |
540 | while ((function < max_functions) && (!stop_it)) { | 547 | while ((function < max_functions) && (!stop_it)) { |
541 | pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_VENDOR_ID, &ID); | 548 | pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_VENDOR_ID, &ID); |
542 | 549 | ||
543 | if (ID == 0xFFFFFFFF) { // nothing there. | 550 | if (ID == 0xFFFFFFFF) { /* nothing there. */ |
544 | function++; | 551 | function++; |
545 | } else { // Something there | 552 | } else { /* Something there */ |
546 | pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), 0x0B, &class_code); | 553 | pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), 0x0B, &class_code); |
547 | 554 | ||
548 | pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_HEADER_TYPE, &header_type); | 555 | pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_HEADER_TYPE, &header_type); |
@@ -552,7 +559,7 @@ int cpqhp_save_slot_config (struct controller *ctrl, struct pci_func * new_slot) | |||
552 | } | 559 | } |
553 | 560 | ||
554 | } while (function < max_functions); | 561 | } while (function < max_functions); |
555 | } // End of IF (device in slot?) | 562 | } /* End of IF (device in slot?) */ |
556 | else { | 563 | else { |
557 | return 2; | 564 | return 2; |
558 | } | 565 | } |
@@ -590,11 +597,10 @@ int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func * func) | |||
590 | pci_bus->number = func->bus; | 597 | pci_bus->number = func->bus; |
591 | devfn = PCI_DEVFN(func->device, func->function); | 598 | devfn = PCI_DEVFN(func->device, func->function); |
592 | 599 | ||
593 | // Check for Bridge | 600 | /* Check for Bridge */ |
594 | pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type); | 601 | pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type); |
595 | 602 | ||
596 | if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { | 603 | if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { |
597 | // PCI-PCI Bridge | ||
598 | pci_bus_read_config_byte (pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); | 604 | pci_bus_read_config_byte (pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); |
599 | 605 | ||
600 | sub_bus = (int) secondary_bus; | 606 | sub_bus = (int) secondary_bus; |
@@ -610,23 +616,27 @@ int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func * func) | |||
610 | } | 616 | } |
611 | pci_bus->number = func->bus; | 617 | pci_bus->number = func->bus; |
612 | 618 | ||
613 | //FIXME: this loop is duplicated in the non-bridge case. The two could be rolled together | 619 | /* FIXME: this loop is duplicated in the non-bridge |
614 | // Figure out IO and memory base lengths | 620 | * case. The two could be rolled together Figure out |
621 | * IO and memory base lengths | ||
622 | */ | ||
615 | for (cloop = 0x10; cloop <= 0x14; cloop += 4) { | 623 | for (cloop = 0x10; cloop <= 0x14; cloop += 4) { |
616 | temp_register = 0xFFFFFFFF; | 624 | temp_register = 0xFFFFFFFF; |
617 | pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register); | 625 | pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register); |
618 | pci_bus_read_config_dword (pci_bus, devfn, cloop, &base); | 626 | pci_bus_read_config_dword (pci_bus, devfn, cloop, &base); |
619 | 627 | /* If this register is implemented */ | |
620 | if (base) { // If this register is implemented | 628 | if (base) { |
621 | if (base & 0x01L) { | 629 | if (base & 0x01L) { |
622 | // IO base | 630 | /* IO base |
623 | // set base = amount of IO space requested | 631 | * set base = amount of IO space |
632 | * requested | ||
633 | */ | ||
624 | base = base & 0xFFFFFFFE; | 634 | base = base & 0xFFFFFFFE; |
625 | base = (~base) + 1; | 635 | base = (~base) + 1; |
626 | 636 | ||
627 | type = 1; | 637 | type = 1; |
628 | } else { | 638 | } else { |
629 | // memory base | 639 | /* memory base */ |
630 | base = base & 0xFFFFFFF0; | 640 | base = base & 0xFFFFFFF0; |
631 | base = (~base) + 1; | 641 | base = (~base) + 1; |
632 | 642 | ||
@@ -637,32 +647,36 @@ int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func * func) | |||
637 | type = 0; | 647 | type = 0; |
638 | } | 648 | } |
639 | 649 | ||
640 | // Save information in slot structure | 650 | /* Save information in slot structure */ |
641 | func->base_length[(cloop - 0x10) >> 2] = | 651 | func->base_length[(cloop - 0x10) >> 2] = |
642 | base; | 652 | base; |
643 | func->base_type[(cloop - 0x10) >> 2] = type; | 653 | func->base_type[(cloop - 0x10) >> 2] = type; |
644 | 654 | ||
645 | } // End of base register loop | 655 | } /* End of base register loop */ |
646 | |||
647 | 656 | ||
648 | } else if ((header_type & 0x7F) == 0x00) { // PCI-PCI Bridge | 657 | } else if ((header_type & 0x7F) == 0x00) { |
649 | // Figure out IO and memory base lengths | 658 | /* Figure out IO and memory base lengths */ |
650 | for (cloop = 0x10; cloop <= 0x24; cloop += 4) { | 659 | for (cloop = 0x10; cloop <= 0x24; cloop += 4) { |
651 | temp_register = 0xFFFFFFFF; | 660 | temp_register = 0xFFFFFFFF; |
652 | pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register); | 661 | pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register); |
653 | pci_bus_read_config_dword (pci_bus, devfn, cloop, &base); | 662 | pci_bus_read_config_dword (pci_bus, devfn, cloop, &base); |
654 | 663 | ||
655 | if (base) { // If this register is implemented | 664 | /* If this register is implemented */ |
665 | if (base) { | ||
656 | if (base & 0x01L) { | 666 | if (base & 0x01L) { |
657 | // IO base | 667 | /* IO base |
658 | // base = amount of IO space requested | 668 | * base = amount of IO space |
669 | * requested | ||
670 | */ | ||
659 | base = base & 0xFFFFFFFE; | 671 | base = base & 0xFFFFFFFE; |
660 | base = (~base) + 1; | 672 | base = (~base) + 1; |
661 | 673 | ||
662 | type = 1; | 674 | type = 1; |
663 | } else { | 675 | } else { |
664 | // memory base | 676 | /* memory base |
665 | // base = amount of memory space requested | 677 | * base = amount of memory |
678 | * space requested | ||
679 | */ | ||
666 | base = base & 0xFFFFFFF0; | 680 | base = base & 0xFFFFFFF0; |
667 | base = (~base) + 1; | 681 | base = (~base) + 1; |
668 | 682 | ||
@@ -673,16 +687,16 @@ int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func * func) | |||
673 | type = 0; | 687 | type = 0; |
674 | } | 688 | } |
675 | 689 | ||
676 | // Save information in slot structure | 690 | /* Save information in slot structure */ |
677 | func->base_length[(cloop - 0x10) >> 2] = base; | 691 | func->base_length[(cloop - 0x10) >> 2] = base; |
678 | func->base_type[(cloop - 0x10) >> 2] = type; | 692 | func->base_type[(cloop - 0x10) >> 2] = type; |
679 | 693 | ||
680 | } // End of base register loop | 694 | } /* End of base register loop */ |
681 | 695 | ||
682 | } else { // Some other unknown header type | 696 | } else { /* Some other unknown header type */ |
683 | } | 697 | } |
684 | 698 | ||
685 | // find the next device in this slot | 699 | /* find the next device in this slot */ |
686 | func = cpqhp_slot_find(func->bus, func->device, index++); | 700 | func = cpqhp_slot_find(func->bus, func->device, index++); |
687 | } | 701 | } |
688 | 702 | ||
@@ -728,18 +742,18 @@ int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func) | |||
728 | pci_bus->number = func->bus; | 742 | pci_bus->number = func->bus; |
729 | devfn = PCI_DEVFN(func->device, func->function); | 743 | devfn = PCI_DEVFN(func->device, func->function); |
730 | 744 | ||
731 | // Save the command register | 745 | /* Save the command register */ |
732 | pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command); | 746 | pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command); |
733 | 747 | ||
734 | // disable card | 748 | /* disable card */ |
735 | command = 0x00; | 749 | command = 0x00; |
736 | pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command); | 750 | pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command); |
737 | 751 | ||
738 | // Check for Bridge | 752 | /* Check for Bridge */ |
739 | pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); | 753 | pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); |
740 | 754 | ||
741 | if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { // PCI-PCI Bridge | 755 | if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { |
742 | // Clear Bridge Control Register | 756 | /* Clear Bridge Control Register */ |
743 | command = 0x00; | 757 | command = 0x00; |
744 | pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command); | 758 | pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command); |
745 | pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); | 759 | pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); |
@@ -755,7 +769,7 @@ int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func) | |||
755 | bus_node->next = func->bus_head; | 769 | bus_node->next = func->bus_head; |
756 | func->bus_head = bus_node; | 770 | func->bus_head = bus_node; |
757 | 771 | ||
758 | // Save IO base and Limit registers | 772 | /* Save IO base and Limit registers */ |
759 | pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &b_base); | 773 | pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &b_base); |
760 | pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &b_length); | 774 | pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &b_length); |
761 | 775 | ||
@@ -771,7 +785,7 @@ int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func) | |||
771 | func->io_head = io_node; | 785 | func->io_head = io_node; |
772 | } | 786 | } |
773 | 787 | ||
774 | // Save memory base and Limit registers | 788 | /* Save memory base and Limit registers */ |
775 | pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base); | 789 | pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base); |
776 | pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length); | 790 | pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length); |
777 | 791 | ||
@@ -787,7 +801,7 @@ int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func) | |||
787 | func->mem_head = mem_node; | 801 | func->mem_head = mem_node; |
788 | } | 802 | } |
789 | 803 | ||
790 | // Save prefetchable memory base and Limit registers | 804 | /* Save prefetchable memory base and Limit registers */ |
791 | pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base); | 805 | pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base); |
792 | pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length); | 806 | pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length); |
793 | 807 | ||
@@ -802,7 +816,7 @@ int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func) | |||
802 | p_mem_node->next = func->p_mem_head; | 816 | p_mem_node->next = func->p_mem_head; |
803 | func->p_mem_head = p_mem_node; | 817 | func->p_mem_head = p_mem_node; |
804 | } | 818 | } |
805 | // Figure out IO and memory base lengths | 819 | /* Figure out IO and memory base lengths */ |
806 | for (cloop = 0x10; cloop <= 0x14; cloop += 4) { | 820 | for (cloop = 0x10; cloop <= 0x14; cloop += 4) { |
807 | pci_bus_read_config_dword (pci_bus, devfn, cloop, &save_base); | 821 | pci_bus_read_config_dword (pci_bus, devfn, cloop, &save_base); |
808 | 822 | ||
@@ -812,11 +826,14 @@ int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func) | |||
812 | 826 | ||
813 | temp_register = base; | 827 | temp_register = base; |
814 | 828 | ||
815 | if (base) { // If this register is implemented | 829 | /* If this register is implemented */ |
830 | if (base) { | ||
816 | if (((base & 0x03L) == 0x01) | 831 | if (((base & 0x03L) == 0x01) |
817 | && (save_command & 0x01)) { | 832 | && (save_command & 0x01)) { |
818 | // IO base | 833 | /* IO base |
819 | // set temp_register = amount of IO space requested | 834 | * set temp_register = amount |
835 | * of IO space requested | ||
836 | */ | ||
820 | temp_register = base & 0xFFFFFFFE; | 837 | temp_register = base & 0xFFFFFFFE; |
821 | temp_register = (~temp_register) + 1; | 838 | temp_register = (~temp_register) + 1; |
822 | 839 | ||
@@ -834,7 +851,7 @@ int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func) | |||
834 | } else | 851 | } else |
835 | if (((base & 0x0BL) == 0x08) | 852 | if (((base & 0x0BL) == 0x08) |
836 | && (save_command & 0x02)) { | 853 | && (save_command & 0x02)) { |
837 | // prefetchable memory base | 854 | /* prefetchable memory base */ |
838 | temp_register = base & 0xFFFFFFF0; | 855 | temp_register = base & 0xFFFFFFF0; |
839 | temp_register = (~temp_register) + 1; | 856 | temp_register = (~temp_register) + 1; |
840 | 857 | ||
@@ -851,7 +868,7 @@ int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func) | |||
851 | } else | 868 | } else |
852 | if (((base & 0x0BL) == 0x00) | 869 | if (((base & 0x0BL) == 0x00) |
853 | && (save_command & 0x02)) { | 870 | && (save_command & 0x02)) { |
854 | // prefetchable memory base | 871 | /* prefetchable memory base */ |
855 | temp_register = base & 0xFFFFFFF0; | 872 | temp_register = base & 0xFFFFFFF0; |
856 | temp_register = (~temp_register) + 1; | 873 | temp_register = (~temp_register) + 1; |
857 | 874 | ||
@@ -868,9 +885,10 @@ int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func) | |||
868 | } else | 885 | } else |
869 | return(1); | 886 | return(1); |
870 | } | 887 | } |
871 | } // End of base register loop | 888 | } /* End of base register loop */ |
872 | } else if ((header_type & 0x7F) == 0x00) { // Standard header | 889 | /* Standard header */ |
873 | // Figure out IO and memory base lengths | 890 | } else if ((header_type & 0x7F) == 0x00) { |
891 | /* Figure out IO and memory base lengths */ | ||
874 | for (cloop = 0x10; cloop <= 0x24; cloop += 4) { | 892 | for (cloop = 0x10; cloop <= 0x24; cloop += 4) { |
875 | pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base); | 893 | pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base); |
876 | 894 | ||
@@ -880,11 +898,14 @@ int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func) | |||
880 | 898 | ||
881 | temp_register = base; | 899 | temp_register = base; |
882 | 900 | ||
883 | if (base) { // If this register is implemented | 901 | /* If this register is implemented */ |
902 | if (base) { | ||
884 | if (((base & 0x03L) == 0x01) | 903 | if (((base & 0x03L) == 0x01) |
885 | && (save_command & 0x01)) { | 904 | && (save_command & 0x01)) { |
886 | // IO base | 905 | /* IO base |
887 | // set temp_register = amount of IO space requested | 906 | * set temp_register = amount |
907 | * of IO space requested | ||
908 | */ | ||
888 | temp_register = base & 0xFFFFFFFE; | 909 | temp_register = base & 0xFFFFFFFE; |
889 | temp_register = (~temp_register) + 1; | 910 | temp_register = (~temp_register) + 1; |
890 | 911 | ||
@@ -901,7 +922,7 @@ int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func) | |||
901 | } else | 922 | } else |
902 | if (((base & 0x0BL) == 0x08) | 923 | if (((base & 0x0BL) == 0x08) |
903 | && (save_command & 0x02)) { | 924 | && (save_command & 0x02)) { |
904 | // prefetchable memory base | 925 | /* prefetchable memory base */ |
905 | temp_register = base & 0xFFFFFFF0; | 926 | temp_register = base & 0xFFFFFFF0; |
906 | temp_register = (~temp_register) + 1; | 927 | temp_register = (~temp_register) + 1; |
907 | 928 | ||
@@ -918,7 +939,7 @@ int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func) | |||
918 | } else | 939 | } else |
919 | if (((base & 0x0BL) == 0x00) | 940 | if (((base & 0x0BL) == 0x00) |
920 | && (save_command & 0x02)) { | 941 | && (save_command & 0x02)) { |
921 | // prefetchable memory base | 942 | /* prefetchable memory base */ |
922 | temp_register = base & 0xFFFFFFF0; | 943 | temp_register = base & 0xFFFFFFF0; |
923 | temp_register = (~temp_register) + 1; | 944 | temp_register = (~temp_register) + 1; |
924 | 945 | ||
@@ -935,11 +956,12 @@ int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func) | |||
935 | } else | 956 | } else |
936 | return(1); | 957 | return(1); |
937 | } | 958 | } |
938 | } // End of base register loop | 959 | } /* End of base register loop */ |
939 | } else { // Some other unknown header type | 960 | /* Some other unknown header type */ |
961 | } else { | ||
940 | } | 962 | } |
941 | 963 | ||
942 | // find the next device in this slot | 964 | /* find the next device in this slot */ |
943 | func = cpqhp_slot_find(func->bus, func->device, index++); | 965 | func = cpqhp_slot_find(func->bus, func->device, index++); |
944 | } | 966 | } |
945 | 967 | ||
@@ -975,16 +997,17 @@ int cpqhp_configure_board(struct controller *ctrl, struct pci_func * func) | |||
975 | pci_bus->number = func->bus; | 997 | pci_bus->number = func->bus; |
976 | devfn = PCI_DEVFN(func->device, func->function); | 998 | devfn = PCI_DEVFN(func->device, func->function); |
977 | 999 | ||
978 | // Start at the top of config space so that the control | 1000 | /* Start at the top of config space so that the control |
979 | // registers are programmed last | 1001 | * registers are programmed last |
1002 | */ | ||
980 | for (cloop = 0x3C; cloop > 0; cloop -= 4) { | 1003 | for (cloop = 0x3C; cloop > 0; cloop -= 4) { |
981 | pci_bus_write_config_dword (pci_bus, devfn, cloop, func->config_space[cloop >> 2]); | 1004 | pci_bus_write_config_dword (pci_bus, devfn, cloop, func->config_space[cloop >> 2]); |
982 | } | 1005 | } |
983 | 1006 | ||
984 | pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type); | 1007 | pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type); |
985 | 1008 | ||
986 | // If this is a bridge device, restore subordinate devices | 1009 | /* If this is a bridge device, restore subordinate devices */ |
987 | if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { // PCI-PCI Bridge | 1010 | if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { |
988 | pci_bus_read_config_byte (pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); | 1011 | pci_bus_read_config_byte (pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); |
989 | 1012 | ||
990 | sub_bus = (int) secondary_bus; | 1013 | sub_bus = (int) secondary_bus; |
@@ -1000,8 +1023,9 @@ int cpqhp_configure_board(struct controller *ctrl, struct pci_func * func) | |||
1000 | } | 1023 | } |
1001 | } else { | 1024 | } else { |
1002 | 1025 | ||
1003 | // Check all the base Address Registers to make sure | 1026 | /* Check all the base Address Registers to make sure |
1004 | // they are the same. If not, the board is different. | 1027 | * they are the same. If not, the board is different. |
1028 | */ | ||
1005 | 1029 | ||
1006 | for (cloop = 16; cloop < 40; cloop += 4) { | 1030 | for (cloop = 16; cloop < 40; cloop += 4) { |
1007 | pci_bus_read_config_dword (pci_bus, devfn, cloop, &temp); | 1031 | pci_bus_read_config_dword (pci_bus, devfn, cloop, &temp); |
@@ -1058,27 +1082,28 @@ int cpqhp_valid_replace(struct controller *ctrl, struct pci_func * func) | |||
1058 | 1082 | ||
1059 | pci_bus_read_config_dword (pci_bus, devfn, PCI_VENDOR_ID, &temp_register); | 1083 | pci_bus_read_config_dword (pci_bus, devfn, PCI_VENDOR_ID, &temp_register); |
1060 | 1084 | ||
1061 | // No adapter present | 1085 | /* No adapter present */ |
1062 | if (temp_register == 0xFFFFFFFF) | 1086 | if (temp_register == 0xFFFFFFFF) |
1063 | return(NO_ADAPTER_PRESENT); | 1087 | return(NO_ADAPTER_PRESENT); |
1064 | 1088 | ||
1065 | if (temp_register != func->config_space[0]) | 1089 | if (temp_register != func->config_space[0]) |
1066 | return(ADAPTER_NOT_SAME); | 1090 | return(ADAPTER_NOT_SAME); |
1067 | 1091 | ||
1068 | // Check for same revision number and class code | 1092 | /* Check for same revision number and class code */ |
1069 | pci_bus_read_config_dword (pci_bus, devfn, PCI_CLASS_REVISION, &temp_register); | 1093 | pci_bus_read_config_dword (pci_bus, devfn, PCI_CLASS_REVISION, &temp_register); |
1070 | 1094 | ||
1071 | // Adapter not the same | 1095 | /* Adapter not the same */ |
1072 | if (temp_register != func->config_space[0x08 >> 2]) | 1096 | if (temp_register != func->config_space[0x08 >> 2]) |
1073 | return(ADAPTER_NOT_SAME); | 1097 | return(ADAPTER_NOT_SAME); |
1074 | 1098 | ||
1075 | // Check for Bridge | 1099 | /* Check for Bridge */ |
1076 | pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type); | 1100 | pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type); |
1077 | 1101 | ||
1078 | if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { // PCI-PCI Bridge | 1102 | if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { |
1079 | // In order to continue checking, we must program the | 1103 | /* In order to continue checking, we must program the |
1080 | // bus registers in the bridge to respond to accesses | 1104 | * bus registers in the bridge to respond to accesses |
1081 | // for it's subordinate bus(es) | 1105 | * for its subordinate bus(es) |
1106 | */ | ||
1082 | 1107 | ||
1083 | temp_register = func->config_space[0x18 >> 2]; | 1108 | temp_register = func->config_space[0x18 >> 2]; |
1084 | pci_bus_write_config_dword (pci_bus, devfn, PCI_PRIMARY_BUS, temp_register); | 1109 | pci_bus_write_config_dword (pci_bus, devfn, PCI_PRIMARY_BUS, temp_register); |
@@ -1096,35 +1121,39 @@ int cpqhp_valid_replace(struct controller *ctrl, struct pci_func * func) | |||
1096 | } | 1121 | } |
1097 | 1122 | ||
1098 | } | 1123 | } |
1099 | // Check to see if it is a standard config header | 1124 | /* Check to see if it is a standard config header */ |
1100 | else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) { | 1125 | else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) { |
1101 | // Check subsystem vendor and ID | 1126 | /* Check subsystem vendor and ID */ |
1102 | pci_bus_read_config_dword (pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register); | 1127 | pci_bus_read_config_dword (pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register); |
1103 | 1128 | ||
1104 | if (temp_register != func->config_space[0x2C >> 2]) { | 1129 | if (temp_register != func->config_space[0x2C >> 2]) { |
1105 | // If it's a SMART-2 and the register isn't filled | 1130 | /* If it's a SMART-2 and the register isn't |
1106 | // in, ignore the difference because | 1131 | * filled in, ignore the difference because |
1107 | // they just have an old rev of the firmware | 1132 | * they just have an old rev of the firmware |
1108 | 1133 | */ | |
1109 | if (!((func->config_space[0] == 0xAE100E11) | 1134 | if (!((func->config_space[0] == 0xAE100E11) |
1110 | && (temp_register == 0x00L))) | 1135 | && (temp_register == 0x00L))) |
1111 | return(ADAPTER_NOT_SAME); | 1136 | return(ADAPTER_NOT_SAME); |
1112 | } | 1137 | } |
1113 | // Figure out IO and memory base lengths | 1138 | /* Figure out IO and memory base lengths */ |
1114 | for (cloop = 0x10; cloop <= 0x24; cloop += 4) { | 1139 | for (cloop = 0x10; cloop <= 0x24; cloop += 4) { |
1115 | temp_register = 0xFFFFFFFF; | 1140 | temp_register = 0xFFFFFFFF; |
1116 | pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register); | 1141 | pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register); |
1117 | pci_bus_read_config_dword (pci_bus, devfn, cloop, &base); | 1142 | pci_bus_read_config_dword (pci_bus, devfn, cloop, &base); |
1118 | if (base) { // If this register is implemented | 1143 | |
1144 | /* If this register is implemented */ | ||
1145 | if (base) { | ||
1119 | if (base & 0x01L) { | 1146 | if (base & 0x01L) { |
1120 | // IO base | 1147 | /* IO base |
1121 | // set base = amount of IO space requested | 1148 | * set base = amount of IO |
1149 | * space requested | ||
1150 | */ | ||
1122 | base = base & 0xFFFFFFFE; | 1151 | base = base & 0xFFFFFFFE; |
1123 | base = (~base) + 1; | 1152 | base = (~base) + 1; |
1124 | 1153 | ||
1125 | type = 1; | 1154 | type = 1; |
1126 | } else { | 1155 | } else { |
1127 | // memory base | 1156 | /* memory base */ |
1128 | base = base & 0xFFFFFFF0; | 1157 | base = base & 0xFFFFFFF0; |
1129 | base = (~base) + 1; | 1158 | base = (~base) + 1; |
1130 | 1159 | ||
@@ -1135,23 +1164,24 @@ int cpqhp_valid_replace(struct controller *ctrl, struct pci_func * func) | |||
1135 | type = 0; | 1164 | type = 0; |
1136 | } | 1165 | } |
1137 | 1166 | ||
1138 | // Check information in slot structure | 1167 | /* Check information in slot structure */ |
1139 | if (func->base_length[(cloop - 0x10) >> 2] != base) | 1168 | if (func->base_length[(cloop - 0x10) >> 2] != base) |
1140 | return(ADAPTER_NOT_SAME); | 1169 | return(ADAPTER_NOT_SAME); |
1141 | 1170 | ||
1142 | if (func->base_type[(cloop - 0x10) >> 2] != type) | 1171 | if (func->base_type[(cloop - 0x10) >> 2] != type) |
1143 | return(ADAPTER_NOT_SAME); | 1172 | return(ADAPTER_NOT_SAME); |
1144 | 1173 | ||
1145 | } // End of base register loop | 1174 | } /* End of base register loop */ |
1146 | 1175 | ||
1147 | } // End of (type 0 config space) else | 1176 | } /* End of (type 0 config space) else */ |
1148 | else { | 1177 | else { |
1149 | // this is not a type 0 or 1 config space header so | 1178 | /* this is not a type 0 or 1 config space header so |
1150 | // we don't know how to do it | 1179 | * we don't know how to do it |
1180 | */ | ||
1151 | return(DEVICE_TYPE_NOT_SUPPORTED); | 1181 | return(DEVICE_TYPE_NOT_SUPPORTED); |
1152 | } | 1182 | } |
1153 | 1183 | ||
1154 | // Get the next function | 1184 | /* Get the next function */ |
1155 | func = cpqhp_slot_find(func->bus, func->device, index++); | 1185 | func = cpqhp_slot_find(func->bus, func->device, index++); |
1156 | } | 1186 | } |
1157 | 1187 | ||
@@ -1190,7 +1220,7 @@ int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_st | |||
1190 | if (rom_resource_table == NULL) { | 1220 | if (rom_resource_table == NULL) { |
1191 | return -ENODEV; | 1221 | return -ENODEV; |
1192 | } | 1222 | } |
1193 | // Sum all resources and setup resource maps | 1223 | /* Sum all resources and setup resource maps */ |
1194 | unused_IRQ = readl(rom_resource_table + UNUSED_IRQ); | 1224 | unused_IRQ = readl(rom_resource_table + UNUSED_IRQ); |
1195 | dbg("unused_IRQ = %x\n", unused_IRQ); | 1225 | dbg("unused_IRQ = %x\n", unused_IRQ); |
1196 | 1226 | ||
@@ -1262,13 +1292,13 @@ int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_st | |||
1262 | dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length, | 1292 | dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length, |
1263 | primary_bus, secondary_bus, max_bus); | 1293 | primary_bus, secondary_bus, max_bus); |
1264 | 1294 | ||
1265 | // If this entry isn't for our controller's bus, ignore it | 1295 | /* If this entry isn't for our controller's bus, ignore it */ |
1266 | if (primary_bus != ctrl->bus) { | 1296 | if (primary_bus != ctrl->bus) { |
1267 | i--; | 1297 | i--; |
1268 | one_slot += sizeof (struct slot_rt); | 1298 | one_slot += sizeof (struct slot_rt); |
1269 | continue; | 1299 | continue; |
1270 | } | 1300 | } |
1271 | // find out if this entry is for an occupied slot | 1301 | /* find out if this entry is for an occupied slot */ |
1272 | ctrl->pci_bus->number = primary_bus; | 1302 | ctrl->pci_bus->number = primary_bus; |
1273 | pci_bus_read_config_dword (ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword); | 1303 | pci_bus_read_config_dword (ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword); |
1274 | dbg("temp_D_word = %x\n", temp_dword); | 1304 | dbg("temp_D_word = %x\n", temp_dword); |
@@ -1282,13 +1312,13 @@ int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_st | |||
1282 | func = cpqhp_slot_find(primary_bus, dev_func >> 3, index++); | 1312 | func = cpqhp_slot_find(primary_bus, dev_func >> 3, index++); |
1283 | } | 1313 | } |
1284 | 1314 | ||
1285 | // If we can't find a match, skip this table entry | 1315 | /* If we can't find a match, skip this table entry */ |
1286 | if (!func) { | 1316 | if (!func) { |
1287 | i--; | 1317 | i--; |
1288 | one_slot += sizeof (struct slot_rt); | 1318 | one_slot += sizeof (struct slot_rt); |
1289 | continue; | 1319 | continue; |
1290 | } | 1320 | } |
1291 | // this may not work and shouldn't be used | 1321 | /* this may not work and shouldn't be used */ |
1292 | if (secondary_bus != primary_bus) | 1322 | if (secondary_bus != primary_bus) |
1293 | bridged_slot = 1; | 1323 | bridged_slot = 1; |
1294 | else | 1324 | else |
@@ -1301,7 +1331,7 @@ int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_st | |||
1301 | } | 1331 | } |
1302 | 1332 | ||
1303 | 1333 | ||
1304 | // If we've got a valid IO base, use it | 1334 | /* If we've got a valid IO base, use it */ |
1305 | 1335 | ||
1306 | temp_dword = io_base + io_length; | 1336 | temp_dword = io_base + io_length; |
1307 | 1337 | ||
@@ -1325,7 +1355,7 @@ int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_st | |||
1325 | } | 1355 | } |
1326 | } | 1356 | } |
1327 | 1357 | ||
1328 | // If we've got a valid memory base, use it | 1358 | /* If we've got a valid memory base, use it */ |
1329 | temp_dword = mem_base + mem_length; | 1359 | temp_dword = mem_base + mem_length; |
1330 | if ((mem_base) && (temp_dword < 0x10000)) { | 1360 | if ((mem_base) && (temp_dword < 0x10000)) { |
1331 | mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL); | 1361 | mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL); |
@@ -1348,8 +1378,9 @@ int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_st | |||
1348 | } | 1378 | } |
1349 | } | 1379 | } |
1350 | 1380 | ||
1351 | // If we've got a valid prefetchable memory base, and | 1381 | /* If we've got a valid prefetchable memory base, and |
1352 | // the base + length isn't greater than 0xFFFF | 1382 | * the base + length isn't greater than 0xFFFF |
1383 | */ | ||
1353 | temp_dword = pre_mem_base + pre_mem_length; | 1384 | temp_dword = pre_mem_base + pre_mem_length; |
1354 | if ((pre_mem_base) && (temp_dword < 0x10000)) { | 1385 | if ((pre_mem_base) && (temp_dword < 0x10000)) { |
1355 | p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL); | 1386 | p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL); |
@@ -1372,9 +1403,10 @@ int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_st | |||
1372 | } | 1403 | } |
1373 | } | 1404 | } |
1374 | 1405 | ||
1375 | // If we've got a valid bus number, use it | 1406 | /* If we've got a valid bus number, use it |
1376 | // The second condition is to ignore bus numbers on | 1407 | * The second condition is to ignore bus numbers on |
1377 | // populated slots that don't have PCI-PCI bridges | 1408 | * populated slots that don't have PCI-PCI bridges |
1409 | */ | ||
1378 | if (secondary_bus && (secondary_bus != primary_bus)) { | 1410 | if (secondary_bus && (secondary_bus != primary_bus)) { |
1379 | bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL); | 1411 | bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL); |
1380 | if (!bus_node) | 1412 | if (!bus_node) |
@@ -1398,8 +1430,9 @@ int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_st | |||
1398 | one_slot += sizeof (struct slot_rt); | 1430 | one_slot += sizeof (struct slot_rt); |
1399 | } | 1431 | } |
1400 | 1432 | ||
1401 | // If all of the following fail, we don't have any resources for | 1433 | /* If all of the following fail, we don't have any resources for |
1402 | // hot plug add | 1434 | * hot plug add |
1435 | */ | ||
1403 | rc = 1; | 1436 | rc = 1; |
1404 | rc &= cpqhp_resource_sort_and_combine(&(ctrl->mem_head)); | 1437 | rc &= cpqhp_resource_sort_and_combine(&(ctrl->mem_head)); |
1405 | rc &= cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head)); | 1438 | rc &= cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head)); |