PCI: designware: Fix comment for setting number of lanes

Corrects comment for setting number of lanes.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 509a29d84509..8909e7748e67 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -764,7 +764,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
         u32 membase;
         u32 memlimit;
 
-        /* set the number of lines as 4 */
+        /* set the number of lanes */
         dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
         val &= ~PORT_LINK_MODE_MASK;
         switch (pp->lanes) {