Merge tag 'pci-v3.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI changes from Bjorn Helgaas: "Enumeration - Increment max correctly in pci_scan_bridge() (Andreas Noever) - Clarify the "scan anyway" comment in pci_scan_bridge() (Andreas Noever) - Assign CardBus bus number only during the second pass (Andreas Noever) - Use request_resource_conflict() instead of insert_ for bus numbers (Andreas Noever) - Make sure bus number resources stay within their parents bounds (Andreas Noever) - Remove pci_fixup_parent_subordinate_busnr() (Andreas Noever) - Check for child busses which use more bus numbers than allocated (Andreas Noever) - Don't scan random busses in pci_scan_bridge() (Andreas Noever) - x86: Drop pcibios_scan_root() check for bus already scanned (Bjorn Helgaas) - x86: Use pcibios_scan_root() instead of pci_scan_bus_with_sysdata() (Bjorn Helgaas) - x86: Use pcibios_scan_root() instead of pci_scan_bus_on_node() (Bjorn Helgaas) - x86: Merge pci_scan_bus_on_node() into pcibios_scan_root() (Bjorn Helgaas) - x86: Drop return value of pcibios_scan_root() (Bjorn Helgaas) NUMA - x86: Add x86_pci_root_bus_node() to look up NUMA node from PCI bus (Bjorn Helgaas) - x86: Use x86_pci_root_bus_node() instead of get_mp_bus_to_node() (Bjorn Helgaas) - x86: Remove mp_bus_to_node[], set_mp_bus_to_node(), get_mp_bus_to_node() (Bjorn Helgaas) - x86: Use NUMA_NO_NODE, not -1, for unknown node (Bjorn Helgaas) - x86: Remove acpi_get_pxm() usage (Bjorn Helgaas) - ia64: Use NUMA_NO_NODE, not MAX_NUMNODES, for unknown node (Bjorn Helgaas) - ia64: Remove acpi_get_pxm() usage (Bjorn Helgaas) - ACPI: Fix acpi_get_node() prototype (Bjorn Helgaas) Resource management - i2o: Fix and refactor PCI space allocation (Bjorn Helgaas) - Add resource_contains() (Bjorn Helgaas) - Add %pR support for IORESOURCE_UNSET (Bjorn Helgaas) - Mark resources as IORESOURCE_UNSET if we can't assign them (Bjorn Helgaas) - Don't clear IORESOURCE_UNSET when updating BAR (Bjorn Helgaas) - Check IORESOURCE_UNSET before updating BAR (Bjorn Helgaas) - Don't try to claim IORESOURCE_UNSET resources (Bjorn Helgaas) - Mark 64-bit resource as IORESOURCE_UNSET if we only support 32-bit (Bjorn Helgaas) - Don't enable decoding if BAR hasn't been assigned an address (Bjorn Helgaas) - Add "weak" generic pcibios_enable_device() implementation (Bjorn Helgaas) - alpha, microblaze, sh, sparc, tile: Use default pcibios_enable_device() (Bjorn Helgaas) - s390: Use generic pci_enable_resources() (Bjorn Helgaas) - Don't check resource_size() in pci_bus_alloc_resource() (Bjorn Helgaas) - Set type in __request_region() (Bjorn Helgaas) - Check all IORESOURCE_TYPE_BITS in pci_bus_alloc_from_region() (Bjorn Helgaas) - Change pci_bus_alloc_resource() type_mask to unsigned long (Bjorn Helgaas) - Log IDE resource quirk in dmesg (Bjorn Helgaas) - Revert "[PATCH] Insert GART region into resource map" (Bjorn Helgaas) PCI device hotplug - Make check_link_active() non-static (Rajat Jain) - Use link change notifications for hot-plug and removal (Rajat Jain) - Enable link state change notifications (Rajat Jain) - Don't disable the link permanently during removal (Rajat Jain) - Don't check adapter or latch status while disabling (Rajat Jain) - Disable link notification across slot reset (Rajat Jain) - Ensure very fast hotplug events are also processed (Rajat Jain) - Add hotplug_lock to serialize hotplug events (Rajat Jain) - Remove a non-existent card, regardless of "surprise" capability (Rajat Jain) - Don't turn slot off when hot-added device already exists (Yijing Wang) MSI - Keep pci_enable_msi() documentation (Alexander Gordeev) - ahci: Fix broken single MSI fallback (Alexander Gordeev) - ahci, vfio: Use pci_enable_msi_range() (Alexander Gordeev) - Check kmalloc() return value, fix leak of name (Greg Kroah-Hartman) - Fix leak of msi_attrs (Greg Kroah-Hartman) - Fix pci_msix_vec_count() htmldocs failure (Masanari Iida) Virtualization - Device-specific ACS support (Alex Williamson) Freescale i.MX6 - Wait for retraining (Marek Vasut) Marvell MVEBU - Use Device ID and revision from underlying endpoint (Andrew Lunn) - Fix incorrect size for PCI aperture resources (Jason Gunthorpe) - Call request_resource() on the apertures (Jason Gunthorpe) - Fix potential issue in range parsing (Jean-Jacques Hiblot) Renesas R-Car - Check platform_get_irq() return code (Ben Dooks) - Add error interrupt handling (Ben Dooks) - Fix bridge logic configuration accesses (Ben Dooks) - Register each instance independently (Magnus Damm) - Break out window size handling (Magnus Damm) - Make the Kconfig dependencies more generic (Magnus Damm) Synopsys DesignWare - Fix RC BAR to be single 64-bit non-prefetchable memory (Mohit Kumar) Miscellaneous - Remove unused SR-IOV VF Migration support (Bjorn Helgaas) - Enable INTx if BIOS left them disabled (Bjorn Helgaas) - Fix hex vs decimal typo in cpqhpc_probe() (Dan Carpenter) - Clean up par-arch object file list (Liviu Dudau) - Set IORESOURCE_ROM_SHADOW only for the default VGA device (Sander Eikelenboom) - ACPI, ARM, drm, powerpc, pcmcia, PCI: Use list_for_each_entry() for bus traversal (Yijing Wang) - Fix pci_bus_b() build failure (Paul Gortmaker)" * tag 'pci-v3.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (108 commits) Revert "[PATCH] Insert GART region into resource map" PCI: Log IDE resource quirk in dmesg PCI: Change pci_bus_alloc_resource() type_mask to unsigned long PCI: Check all IORESOURCE_TYPE_BITS in pci_bus_alloc_from_region() resources: Set type in __request_region() PCI: Don't check resource_size() in pci_bus_alloc_resource() s390/PCI: Use generic pci_enable_resources() tile PCI RC: Use default pcibios_enable_device() sparc/PCI: Use default pcibios_enable_device() (Leon only) sh/PCI: Use default pcibios_enable_device() microblaze/PCI: Use default pcibios_enable_device() alpha/PCI: Use default pcibios_enable_device() PCI: Add "weak" generic pcibios_enable_device() implementation PCI: Don't enable decoding if BAR hasn't been assigned an address PCI: Enable INTx in pci_reenable_device() only when MSI/MSI-X not enabled PCI: Mark 64-bit resource as IORESOURCE_UNSET if we only support 32-bit PCI: Don't try to claim IORESOURCE_UNSET resources PCI: Check IORESOURCE_UNSET before updating BAR PCI: Don't clear IORESOURCE_UNSET when updating BAR PCI: Mark resources as IORESOURCE_UNSET if we can't assign them ... Conflicts: arch/x86/include/asm/topology.h drivers/ata/ahci.c
author: Linus Torvalds <torvalds@linux-foundation.org> 2014-04-01 18:14:04 -0400
committer: Linus Torvalds <torvalds@linux-foundation.org> 2014-04-01 18:14:04 -0400
commit: 4b1779c2cf030c68aefe939d946475e4136c1895 (patch)
tree: 27e4bda2f6c8d269d02dec52a62dd1443880c6dc /drivers/pci/host
parent: 62ff577fa2fec87edbf26f53e87210ba726d4d44 (diff)
parent: 30723cbf6f7aec2ab4810bdc4bf12c5749a09e33 (diff)
5 files changed, 177 insertions, 80 deletions
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 47d46c6d8468..a6f67ec8882f 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -27,7 +27,7 @@ config PCI_TEGRA
 config PCI_RCAR_GEN2
        bool "Renesas R-Car Gen2 Internal PCI controller"
-        depends on ARM && (ARCH_R8A7790 || ARCH_R8A7791 || COMPILE_TEST)
+        depends on ARCH_SHMOBILE || (ARM && COMPILE_TEST)
        help
          Say Y here if you want internal PCI support on R-Car Gen2 SoC.
          There are 3 internal PCI controllers available with a single
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index e8663a8c3406..ee082509b0ba 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -424,20 +424,40 @@ static void imx6_pcie_reset_phy(struct pcie_port *pp)
 static int imx6_pcie_link_up(struct pcie_port *pp)
 {
-        u32 rc, ltssm, rx_valid;
+        u32 rc, debug_r0, rx_valid;
+        int count = 5;
        /*
-         * Test if the PHY reports that the link is up and also that
+         * Test if the PHY reports that the link is up and also that the LTSSM
-         * the link training finished.  It might happen that the PHY
+         * training finished. There are three possible states of the link when
-         * reports the link is already up, but the link training bit
+         * this code is called:
-         * is still set, so make sure to check the training is done
+         * 1) The link is DOWN (unlikely)
-         * as well here.
+         *     The link didn't come up yet for some reason. This usually means
+         *     we have a real problem somewhere. Reset the PHY and exit. This
+         *     state calls for inspection of the DEBUG registers.
+         * 2) The link is UP, but still in LTSSM training
+         *     Wait for the training to finish, which should take a very short
+         *     time. If the training does not finish, we have a problem and we
+         *     need to inspect the DEBUG registers. If the training does finish,
+         *     the link is up and operating correctly.
+         * 3) The link is UP and no longer in LTSSM training
+         *     The link is up and operating correctly.
         */
-        rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
+        while (1) {
-        if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) &&
+                rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
-            !(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
+                if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP))
-                return 1;
+                        break;
+                if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
+                        return 1;
+                if (!count--)
+                        break;
+                dev_dbg(pp->dev, "Link is up, but still in training\n");
+                /*
+                 * Wait a little bit, then re-check if the link finished
+                 * the training.
+                 */
+                usleep_range(1000, 2000);
+        }
        /*
         * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
         * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
@@ -446,15 +466,16 @@ static int imx6_pcie_link_up(struct pcie_port *pp)
         * to gen2 is stuck
         */
        pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
-        ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
+        debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0);
        if (rx_valid & 0x01)
                return 0;
-        if (ltssm != 0x0d)
+        if ((debug_r0 & 0x3f) != 0x0d)
                return 0;
        dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
+        dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc);
        imx6_pcie_reset_phy(pp);
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 0e79665afd44..d3d1cfd51e09 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -101,7 +101,9 @@ struct mvebu_pcie {
        struct mvebu_pcie_port *ports;
        struct msi_chip *msi;
        struct resource io;
+        char io_name[30];
        struct resource realio;
+        char mem_name[30];
        struct resource mem;
        struct resource busn;
        int nports;
@@ -672,10 +674,30 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
 {
        struct mvebu_pcie *pcie = sys_to_pcie(sys);
        int i;
+        int domain = 0;
-        if (resource_size(&pcie->realio) != 0)
+#ifdef CONFIG_PCI_DOMAINS
+        domain = sys->domain;
+#endif
+        snprintf(pcie->mem_name, sizeof(pcie->mem_name), "PCI MEM %04x",
+                 domain);
+        pcie->mem.name = pcie->mem_name;
+        snprintf(pcie->io_name, sizeof(pcie->io_name), "PCI I/O %04x", domain);
+        pcie->realio.name = pcie->io_name;
+        if (request_resource(&iomem_resource, &pcie->mem))
+                return 0;
+        if (resource_size(&pcie->realio) != 0) {
+                if (request_resource(&ioport_resource, &pcie->realio)) {
+                        release_resource(&pcie->mem);
+                        return 0;
+                }
                pci_add_resource_offset(&sys->resources, &pcie->realio,
                                        sys->io_offset);
+        }
        pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
        pci_add_resource(&sys->resources, &pcie->busn);
@@ -797,7 +819,7 @@ static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
        for (i = 0; i < nranges; i++) {
                u32 flags = of_read_number(range, 1);
-                u32 slot = of_read_number(range, 2);
+                u32 slot = of_read_number(range + 1, 1);
                u64 cpuaddr = of_read_number(range + na, pna);
                unsigned long rtype;
diff --git a/drivers/pci/host/pci-rcar-gen2.c b/drivers/pci/host/pci-rcar-gen2.c
index ceec147baec3..fd3e3ab56509 100644
--- a/drivers/pci/host/pci-rcar-gen2.c
+++ b/drivers/pci/host/pci-rcar-gen2.c
@@ -18,6 +18,7 @@
 #include <linux/pci.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/sizes.h>
 #include <linux/slab.h>
 /* AHB-PCI Bridge PCI communication registers */
@@ -39,9 +40,26 @@
 #define RCAR_PCI_INT_ENABLE_REG         (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
 #define RCAR_PCI_INT_STATUS_REG         (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
+#define RCAR_PCI_INT_SIGTABORT          (1 << 0)
+#define RCAR_PCI_INT_SIGRETABORT        (1 << 1)
+#define RCAR_PCI_INT_REMABORT           (1 << 2)
+#define RCAR_PCI_INT_PERR               (1 << 3)
+#define RCAR_PCI_INT_SIGSERR            (1 << 4)
+#define RCAR_PCI_INT_RESERR             (1 << 5)
+#define RCAR_PCI_INT_WIN1ERR            (1 << 12)
+#define RCAR_PCI_INT_WIN2ERR            (1 << 13)
 #define RCAR_PCI_INT_A                  (1 << 16)
 #define RCAR_PCI_INT_B                  (1 << 17)
 #define RCAR_PCI_INT_PME                (1 << 19)
+#define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT          | \
+                                RCAR_PCI_INT_SIGRETABORT        | \
+                                RCAR_PCI_INT_SIGRETABORT        | \
+                                RCAR_PCI_INT_REMABORT           | \
+                                RCAR_PCI_INT_PERR               | \
+                                RCAR_PCI_INT_SIGSERR            | \
+                                RCAR_PCI_INT_RESERR             | \
+                                RCAR_PCI_INT_WIN1ERR            | \
+                                RCAR_PCI_INT_WIN2ERR)
 #define RCAR_AHB_BUS_CTR_REG            (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
 #define RCAR_AHB_BUS_MMODE_HTRANS       (1 << 0)
@@ -74,9 +92,6 @@
 #define RCAR_PCI_UNIT_REV_REG           (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
-/* Number of internal PCI controllers */
-#define RCAR_PCI_NR_CONTROLLERS         3
 struct rcar_pci_priv {
        struct device *dev;
        void __iomem *reg;
@@ -84,6 +99,7 @@ struct rcar_pci_priv {
        struct resource mem_res;
        struct resource *cfg_res;
        int irq;
+        unsigned long window_size;
 };
 /* PCI configuration space operations */
@@ -102,6 +118,10 @@ static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
        if (slot > 2)
                return NULL;
+        /* bridge logic only has registers to 0x40 */
+        if (slot == 0x0 && where >= 0x40)
+                return NULL;
        val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
                     RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
@@ -156,7 +176,7 @@ static int rcar_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 }
 /* PCI interrupt mapping */
-static int __init rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
        struct pci_sys_data *sys = dev->bus->sysdata;
        struct rcar_pci_priv *priv = sys->private_data;
@@ -164,8 +184,48 @@ static int __init rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
        return priv->irq;
 }
+#ifdef CONFIG_PCI_DEBUG
+/* if debug enabled, then attach an error handler irq to the bridge */
+static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
+{
+        struct rcar_pci_priv *priv = pw;
+        u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
+        if (status & RCAR_PCI_INT_ALLERRORS) {
+                dev_err(priv->dev, "error irq: status %08x\n", status);
+                /* clear the error(s) */
+                iowrite32(status & RCAR_PCI_INT_ALLERRORS,
+                          priv->reg + RCAR_PCI_INT_STATUS_REG);
+                return IRQ_HANDLED;
+        }
+        return IRQ_NONE;
+}
+static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
+{
+        int ret;
+        u32 val;
+        ret = devm_request_irq(priv->dev, priv->irq, rcar_pci_err_irq,
+                               IRQF_SHARED, "error irq", priv);
+        if (ret) {
+                dev_err(priv->dev, "cannot claim IRQ for error handling\n");
+                return;
+        }
+        val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
+        val |= RCAR_PCI_INT_ALLERRORS;
+        iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
+}
+#else
+static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
+#endif
 /* PCI host controller setup */
-static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
+static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
 {
        struct rcar_pci_priv *priv = sys->private_data;
        void __iomem *reg = priv->reg;
@@ -183,10 +243,31 @@ static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
        iowrite32(val, reg + RCAR_USBCTR_REG);
        udelay(4);
-        /* De-assert reset and set PCIAHB window1 size to 1GB */
+        /* De-assert reset and reset PCIAHB window1 size */
        val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
                 RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
-        iowrite32(val | RCAR_USBCTR_PCIAHB_WIN1_1G, reg + RCAR_USBCTR_REG);
+        /* Setup PCIAHB window1 size */
+        switch (priv->window_size) {
+        case SZ_2G:
+                val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
+                break;
+        case SZ_1G:
+                val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
+                break;
+        case SZ_512M:
+                val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
+                break;
+        default:
+                pr_warn("unknown window size %ld - defaulting to 256M\n",
+                        priv->window_size);
+                priv->window_size = SZ_256M;
+                /* fall-through */
+        case SZ_256M:
+                val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
+                break;
+        }
+        iowrite32(val, reg + RCAR_USBCTR_REG);
        /* Configure AHB master and slave modes */
        iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
@@ -197,7 +278,7 @@ static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
               RCAR_PCI_ARBITER_PCIBP_MODE;
        iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
-        /* PCI-AHB mapping: 0x40000000-0x80000000 */
+        /* PCI-AHB mapping: 0x40000000 base */
        iowrite32(0x40000000 | RCAR_PCIAHB_PREFETCH16,
                  reg + RCAR_PCIAHB_WIN1_CTR_REG);
@@ -224,10 +305,15 @@ static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
        iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
                  reg + RCAR_PCI_INT_ENABLE_REG);
+        if (priv->irq > 0)
+                rcar_pci_setup_errirq(priv);
        /* Add PCI resources */
        pci_add_resource(&sys->resources, &priv->io_res);
        pci_add_resource(&sys->resources, &priv->mem_res);
+        /* Setup bus number based on platform device id */
+        sys->busnr = to_platform_device(priv->dev)->id;
        return 1;
 }
@@ -236,48 +322,13 @@ static struct pci_ops rcar_pci_ops = {
        .write  = rcar_pci_write_config,
 };
-static struct hw_pci rcar_hw_pci __initdata = {
+static int rcar_pci_probe(struct platform_device *pdev)
-        .map_irq        = rcar_pci_map_irq,
-        .ops            = &rcar_pci_ops,
-        .setup          = rcar_pci_setup,
-};
-static int rcar_pci_count __initdata;
-static int __init rcar_pci_add_controller(struct rcar_pci_priv *priv)
-{
-        void **private_data;
-        int count;
-        if (rcar_hw_pci.nr_controllers < rcar_pci_count)
-                goto add_priv;
-        /* (Re)allocate private data pointer array if needed */
-        count = rcar_pci_count + RCAR_PCI_NR_CONTROLLERS;
-        private_data = kzalloc(count * sizeof(void *), GFP_KERNEL);
-        if (!private_data)
-                return -ENOMEM;
-        rcar_pci_count = count;
-        if (rcar_hw_pci.private_data) {
-                memcpy(private_data, rcar_hw_pci.private_data,
-                       rcar_hw_pci.nr_controllers * sizeof(void *));
-                kfree(rcar_hw_pci.private_data);
-        }
-        rcar_hw_pci.private_data = private_data;
-add_priv:
-        /* Add private data pointer to the array */
-        rcar_hw_pci.private_data[rcar_hw_pci.nr_controllers++] = priv;
-        return 0;
-}
-static int __init rcar_pci_probe(struct platform_device *pdev)
 {
        struct resource *cfg_res, *mem_res;
        struct rcar_pci_priv *priv;
        void __iomem *reg;
+        struct hw_pci hw;
+        void *hw_private[1];
        cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        reg = devm_ioremap_resource(&pdev->dev, cfg_res);
@@ -308,31 +359,34 @@ static int __init rcar_pci_probe(struct platform_device *pdev)
        priv->reg = reg;
        priv->dev = &pdev->dev;
-        return rcar_pci_add_controller(priv);
+        if (priv->irq < 0) {
+                dev_err(&pdev->dev, "no valid irq found\n");
+                return priv->irq;
+        }
+        priv->window_size = SZ_1G;
+        hw_private[0] = priv;
+        memset(&hw, 0, sizeof(hw));
+        hw.nr_controllers = ARRAY_SIZE(hw_private);
+        hw.private_data = hw_private;
+        hw.map_irq = rcar_pci_map_irq;
+        hw.ops = &rcar_pci_ops;
+        hw.setup = rcar_pci_setup;
+        pci_common_init_dev(&pdev->dev, &hw);
+        return 0;
 }
 static struct platform_driver rcar_pci_driver = {
        .driver = {
                .name = "pci-rcar-gen2",
+                .owner = THIS_MODULE,
+                .suppress_bind_attrs = true,
        },
+        .probe = rcar_pci_probe,
 };
-static int __init rcar_pci_init(void)
+module_platform_driver(rcar_pci_driver);
-{
-        int retval;
-        retval = platform_driver_probe(&rcar_pci_driver, rcar_pci_probe);
-        if (!retval)
-                pci_common_init(&rcar_hw_pci);
-        /* Private data pointer array is not needed any more */
-        kfree(rcar_hw_pci.private_data);
-        rcar_hw_pci.private_data = NULL;
-        return retval;
-}
-subsys_initcall(rcar_pci_init);
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 2e48ecf09e2c..509a29d84509 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -798,7 +798,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
        /* setup RC BARs */
        dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
-        dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1);
+        dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
        /* setup interrupt pins */
        dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
author	Linus Torvalds <torvalds@linux-foundation.org>	2014-04-01 18:14:04 -0400
committer	Linus Torvalds <torvalds@linux-foundation.org>	2014-04-01 18:14:04 -0400
commit	4b1779c2cf030c68aefe939d946475e4136c1895 (patch)
tree	27e4bda2f6c8d269d02dec52a62dd1443880c6dc /drivers/pci/host
parent	62ff577fa2fec87edbf26f53e87210ba726d4d44 (diff)
parent	30723cbf6f7aec2ab4810bdc4bf12c5749a09e33 (diff)

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index 47d46c6d8468..a6f67ec8882f 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig
@@ -27,7 +27,7 @@ config PCI_TEGRA
27		27
28	config PCI_RCAR_GEN2	28	config PCI_RCAR_GEN2
29	bool "Renesas R-Car Gen2 Internal PCI controller"	29	bool "Renesas R-Car Gen2 Internal PCI controller"
30	depends on ARM && (ARCH_R8A7790 \|\| ARCH_R8A7791 \|\| COMPILE_TEST)	30	depends on ARCH_SHMOBILE \|\| (ARM && COMPILE_TEST)
31	help	31	help
32	Say Y here if you want internal PCI support on R-Car Gen2 SoC.	32	Say Y here if you want internal PCI support on R-Car Gen2 SoC.
33	There are 3 internal PCI controllers available with a single	33	There are 3 internal PCI controllers available with a single


diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index e8663a8c3406..ee082509b0ba 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c
@@ -424,20 +424,40 @@ static void imx6_pcie_reset_phy(struct pcie_port *pp)
424		424
425	static int imx6_pcie_link_up(struct pcie_port *pp)	425	static int imx6_pcie_link_up(struct pcie_port *pp)
426	{	426	{
427	u32 rc, ltssm, rx_valid;	427	u32 rc, debug_r0, rx_valid;
		428	int count = 5;
428		429
429	/*	430	/*
430	* Test if the PHY reports that the link is up and also that	431	* Test if the PHY reports that the link is up and also that the LTSSM
431	* the link training finished. It might happen that the PHY	432	* training finished. There are three possible states of the link when
432	* reports the link is already up, but the link training bit	433	* this code is called:
433	* is still set, so make sure to check the training is done	434	* 1) The link is DOWN (unlikely)
434	* as well here.	435	* The link didn't come up yet for some reason. This usually means
		436	* we have a real problem somewhere. Reset the PHY and exit. This
		437	* state calls for inspection of the DEBUG registers.
		438	* 2) The link is UP, but still in LTSSM training
		439	* Wait for the training to finish, which should take a very short
		440	* time. If the training does not finish, we have a problem and we
		441	* need to inspect the DEBUG registers. If the training does finish,
		442	* the link is up and operating correctly.
		443	* 3) The link is UP and no longer in LTSSM training
		444	* The link is up and operating correctly.
435	*/	445	*/
436	rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);	446	while (1) {
437	if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) &&	447	rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
438	!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))	448	if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP))
439	return 1;	449	break;
440		450	if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
		451	return 1;
		452	if (!count--)
		453	break;
		454	dev_dbg(pp->dev, "Link is up, but still in training\n");
		455	/*
		456	* Wait a little bit, then re-check if the link finished
		457	* the training.
		458	*/
		459	usleep_range(1000, 2000);
		460	}
441	/*	461	/*
442	* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.	462	* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
443	* Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).	463	* Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
@@ -446,15 +466,16 @@ static int imx6_pcie_link_up(struct pcie_port *pp)
446	* to gen2 is stuck	466	* to gen2 is stuck
447	*/	467	*/
448	pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);	468	pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
449	ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;	469	debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0);
450		470
451	if (rx_valid & 0x01)	471	if (rx_valid & 0x01)
452	return 0;	472	return 0;
453		473
454	if (ltssm != 0x0d)	474	if ((debug_r0 & 0x3f) != 0x0d)
455	return 0;	475	return 0;
456		476
457	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");	477	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
		478	dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc);
458		479
459	imx6_pcie_reset_phy(pp);	480	imx6_pcie_reset_phy(pp);
460		481


diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c index 0e79665afd44..d3d1cfd51e09 100644 --- a/drivers/pci/host/pci-mvebu.c +++ b/drivers/pci/host/pci-mvebu.c
@@ -101,7 +101,9 @@ struct mvebu_pcie {
101	struct mvebu_pcie_port *ports;	101	struct mvebu_pcie_port *ports;
102	struct msi_chip *msi;	102	struct msi_chip *msi;
103	struct resource io;	103	struct resource io;
		104	char io_name[30];
104	struct resource realio;	105	struct resource realio;
		106	char mem_name[30];
105	struct resource mem;	107	struct resource mem;
106	struct resource busn;	108	struct resource busn;
107	int nports;	109	int nports;
@@ -672,10 +674,30 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
672	{	674	{
673	struct mvebu_pcie *pcie = sys_to_pcie(sys);	675	struct mvebu_pcie *pcie = sys_to_pcie(sys);
674	int i;	676	int i;
		677	int domain = 0;
675		678
676	if (resource_size(&pcie->realio) != 0)	679	#ifdef CONFIG_PCI_DOMAINS
		680	domain = sys->domain;
		681	#endif
		682
		683	snprintf(pcie->mem_name, sizeof(pcie->mem_name), "PCI MEM %04x",
		684	domain);
		685	pcie->mem.name = pcie->mem_name;
		686
		687	snprintf(pcie->io_name, sizeof(pcie->io_name), "PCI I/O %04x", domain);
		688	pcie->realio.name = pcie->io_name;
		689
		690	if (request_resource(&iomem_resource, &pcie->mem))
		691	return 0;
		692
		693	if (resource_size(&pcie->realio) != 0) {
		694	if (request_resource(&ioport_resource, &pcie->realio)) {
		695	release_resource(&pcie->mem);
		696	return 0;
		697	}
677	pci_add_resource_offset(&sys->resources, &pcie->realio,	698	pci_add_resource_offset(&sys->resources, &pcie->realio,
678	sys->io_offset);	699	sys->io_offset);
		700	}
679	pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);	701	pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
680	pci_add_resource(&sys->resources, &pcie->busn);	702	pci_add_resource(&sys->resources, &pcie->busn);
681		703
@@ -797,7 +819,7 @@ static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
797		819
798	for (i = 0; i < nranges; i++) {	820	for (i = 0; i < nranges; i++) {
799	u32 flags = of_read_number(range, 1);	821	u32 flags = of_read_number(range, 1);
800	u32 slot = of_read_number(range, 2);	822	u32 slot = of_read_number(range + 1, 1);
801	u64 cpuaddr = of_read_number(range + na, pna);	823	u64 cpuaddr = of_read_number(range + na, pna);
802	unsigned long rtype;	824	unsigned long rtype;
803		825


diff --git a/drivers/pci/host/pci-rcar-gen2.c b/drivers/pci/host/pci-rcar-gen2.c index ceec147baec3..fd3e3ab56509 100644 --- a/drivers/pci/host/pci-rcar-gen2.c +++ b/drivers/pci/host/pci-rcar-gen2.c
@@ -18,6 +18,7 @@
18	#include <linux/pci.h>	18	#include <linux/pci.h>
19	#include <linux/platform_device.h>	19	#include <linux/platform_device.h>
20	#include <linux/pm_runtime.h>	20	#include <linux/pm_runtime.h>
		21	#include <linux/sizes.h>
21	#include <linux/slab.h>	22	#include <linux/slab.h>
22		23
23	/* AHB-PCI Bridge PCI communication registers */	24	/* AHB-PCI Bridge PCI communication registers */
@@ -39,9 +40,26 @@
39		40
40	#define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)	41	#define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
41	#define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)	42	#define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
		43	#define RCAR_PCI_INT_SIGTABORT (1 << 0)
		44	#define RCAR_PCI_INT_SIGRETABORT (1 << 1)
		45	#define RCAR_PCI_INT_REMABORT (1 << 2)
		46	#define RCAR_PCI_INT_PERR (1 << 3)
		47	#define RCAR_PCI_INT_SIGSERR (1 << 4)
		48	#define RCAR_PCI_INT_RESERR (1 << 5)
		49	#define RCAR_PCI_INT_WIN1ERR (1 << 12)
		50	#define RCAR_PCI_INT_WIN2ERR (1 << 13)
42	#define RCAR_PCI_INT_A (1 << 16)	51	#define RCAR_PCI_INT_A (1 << 16)
43	#define RCAR_PCI_INT_B (1 << 17)	52	#define RCAR_PCI_INT_B (1 << 17)
44	#define RCAR_PCI_INT_PME (1 << 19)	53	#define RCAR_PCI_INT_PME (1 << 19)
		54	#define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT \| \
		55	RCAR_PCI_INT_SIGRETABORT \| \
		56	RCAR_PCI_INT_SIGRETABORT \| \
		57	RCAR_PCI_INT_REMABORT \| \
		58	RCAR_PCI_INT_PERR \| \
		59	RCAR_PCI_INT_SIGSERR \| \
		60	RCAR_PCI_INT_RESERR \| \
		61	RCAR_PCI_INT_WIN1ERR \| \
		62	RCAR_PCI_INT_WIN2ERR)
45		63
46	#define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)	64	#define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
47	#define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0)	65	#define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0)
@@ -74,9 +92,6 @@
74		92
75	#define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)	93	#define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
76		94
77	/* Number of internal PCI controllers */
78	#define RCAR_PCI_NR_CONTROLLERS 3
79
80	struct rcar_pci_priv {	95	struct rcar_pci_priv {
81	struct device *dev;	96	struct device *dev;
82	void __iomem *reg;	97	void __iomem *reg;
@@ -84,6 +99,7 @@ struct rcar_pci_priv {
84	struct resource mem_res;	99	struct resource mem_res;
85	struct resource *cfg_res;	100	struct resource *cfg_res;
86	int irq;	101	int irq;
		102	unsigned long window_size;
87	};	103	};
88		104
89	/* PCI configuration space operations */	105	/* PCI configuration space operations */
@@ -102,6 +118,10 @@ static void __iomem rcar_pci_cfg_base(struct pci_bus bus, unsigned int devfn,
102	if (slot > 2)	118	if (slot > 2)
103	return NULL;	119	return NULL;
104		120
		121	/* bridge logic only has registers to 0x40 */
		122	if (slot == 0x0 && where >= 0x40)
		123	return NULL;
		124
105	val = slot ? RCAR_AHBPCI_WIN1_DEVICE \| RCAR_AHBPCI_WIN_CTR_CFG :	125	val = slot ? RCAR_AHBPCI_WIN1_DEVICE \| RCAR_AHBPCI_WIN_CTR_CFG :
106	RCAR_AHBPCI_WIN1_HOST \| RCAR_AHBPCI_WIN_CTR_CFG;	126	RCAR_AHBPCI_WIN1_HOST \| RCAR_AHBPCI_WIN_CTR_CFG;
107		127
@@ -156,7 +176,7 @@ static int rcar_pci_write_config(struct pci_bus *bus, unsigned int devfn,
156	}	176	}
157		177
158	/* PCI interrupt mapping */	178	/* PCI interrupt mapping */
159	static int __init rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)	179	static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
160	{	180	{
161	struct pci_sys_data *sys = dev->bus->sysdata;	181	struct pci_sys_data *sys = dev->bus->sysdata;
162	struct rcar_pci_priv *priv = sys->private_data;	182	struct rcar_pci_priv *priv = sys->private_data;
@@ -164,8 +184,48 @@ static int __init rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
164	return priv->irq;	184	return priv->irq;
165	}	185	}
166		186
		187	#ifdef CONFIG_PCI_DEBUG
		188	/* if debug enabled, then attach an error handler irq to the bridge */
		189
		190	static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
		191	{
		192	struct rcar_pci_priv *priv = pw;
		193	u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
		194
		195	if (status & RCAR_PCI_INT_ALLERRORS) {
		196	dev_err(priv->dev, "error irq: status %08x\n", status);
		197
		198	/* clear the error(s) */
		199	iowrite32(status & RCAR_PCI_INT_ALLERRORS,
		200	priv->reg + RCAR_PCI_INT_STATUS_REG);
		201	return IRQ_HANDLED;
		202	}
		203
		204	return IRQ_NONE;
		205	}
		206
		207	static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
		208	{
		209	int ret;
		210	u32 val;
		211
		212	ret = devm_request_irq(priv->dev, priv->irq, rcar_pci_err_irq,
		213	IRQF_SHARED, "error irq", priv);
		214	if (ret) {
		215	dev_err(priv->dev, "cannot claim IRQ for error handling\n");
		216	return;
		217	}
		218
		219	val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
		220	val \|= RCAR_PCI_INT_ALLERRORS;
		221	iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
		222	}
		223	#else
		224	static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
		225	#endif
		226
167	/* PCI host controller setup */	227	/* PCI host controller setup */
168	static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)	228	static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
169	{	229	{
170	struct rcar_pci_priv *priv = sys->private_data;	230	struct rcar_pci_priv *priv = sys->private_data;
171	void __iomem *reg = priv->reg;	231	void __iomem *reg = priv->reg;
@@ -183,10 +243,31 @@ static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
183	iowrite32(val, reg + RCAR_USBCTR_REG);	243	iowrite32(val, reg + RCAR_USBCTR_REG);
184	udelay(4);	244	udelay(4);
185		245
186	/* De-assert reset and set PCIAHB window1 size to 1GB */	246	/* De-assert reset and reset PCIAHB window1 size */
187	val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK \| RCAR_USBCTR_PCICLK_MASK \|	247	val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK \| RCAR_USBCTR_PCICLK_MASK \|
188	RCAR_USBCTR_USBH_RST \| RCAR_USBCTR_PLL_RST);	248	RCAR_USBCTR_USBH_RST \| RCAR_USBCTR_PLL_RST);
189	iowrite32(val \| RCAR_USBCTR_PCIAHB_WIN1_1G, reg + RCAR_USBCTR_REG);	249
		250	/* Setup PCIAHB window1 size */
		251	switch (priv->window_size) {
		252	case SZ_2G:
		253	val \|= RCAR_USBCTR_PCIAHB_WIN1_2G;
		254	break;
		255	case SZ_1G:
		256	val \|= RCAR_USBCTR_PCIAHB_WIN1_1G;
		257	break;
		258	case SZ_512M:
		259	val \|= RCAR_USBCTR_PCIAHB_WIN1_512M;
		260	break;
		261	default:
		262	pr_warn("unknown window size %ld - defaulting to 256M\n",
		263	priv->window_size);
		264	priv->window_size = SZ_256M;
		265	/* fall-through */
		266	case SZ_256M:
		267	val \|= RCAR_USBCTR_PCIAHB_WIN1_256M;
		268	break;
		269	}
		270	iowrite32(val, reg + RCAR_USBCTR_REG);
190		271
191	/* Configure AHB master and slave modes */	272	/* Configure AHB master and slave modes */
192	iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);	273	iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
@@ -197,7 +278,7 @@ static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
197	RCAR_PCI_ARBITER_PCIBP_MODE;	278	RCAR_PCI_ARBITER_PCIBP_MODE;
198	iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);	279	iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
199		280
200	/* PCI-AHB mapping: 0x40000000-0x80000000 */	281	/* PCI-AHB mapping: 0x40000000 base */
201	iowrite32(0x40000000 \| RCAR_PCIAHB_PREFETCH16,	282	iowrite32(0x40000000 \| RCAR_PCIAHB_PREFETCH16,
202	reg + RCAR_PCIAHB_WIN1_CTR_REG);	283	reg + RCAR_PCIAHB_WIN1_CTR_REG);
203		284
@@ -224,10 +305,15 @@ static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
224	iowrite32(RCAR_PCI_INT_A \| RCAR_PCI_INT_B \| RCAR_PCI_INT_PME,	305	iowrite32(RCAR_PCI_INT_A \| RCAR_PCI_INT_B \| RCAR_PCI_INT_PME,
225	reg + RCAR_PCI_INT_ENABLE_REG);	306	reg + RCAR_PCI_INT_ENABLE_REG);
226		307
		308	if (priv->irq > 0)
		309	rcar_pci_setup_errirq(priv);
		310
227	/* Add PCI resources */	311	/* Add PCI resources */
228	pci_add_resource(&sys->resources, &priv->io_res);	312	pci_add_resource(&sys->resources, &priv->io_res);
229	pci_add_resource(&sys->resources, &priv->mem_res);	313	pci_add_resource(&sys->resources, &priv->mem_res);
230		314
		315	/* Setup bus number based on platform device id */
		316	sys->busnr = to_platform_device(priv->dev)->id;
231	return 1;	317	return 1;
232	}	318	}
233		319
@@ -236,48 +322,13 @@ static struct pci_ops rcar_pci_ops = {
236	.write = rcar_pci_write_config,	322	.write = rcar_pci_write_config,
237	};	323	};
238		324
239	static struct hw_pci rcar_hw_pci __initdata = {	325	static int rcar_pci_probe(struct platform_device *pdev)
240	.map_irq = rcar_pci_map_irq,
241	.ops = &rcar_pci_ops,
242	.setup = rcar_pci_setup,
243	};
244
245	static int rcar_pci_count __initdata;
246
247	static int __init rcar_pci_add_controller(struct rcar_pci_priv *priv)
248	{
249	void **private_data;
250	int count;
251
252	if (rcar_hw_pci.nr_controllers < rcar_pci_count)
253	goto add_priv;
254
255	/* (Re)allocate private data pointer array if needed */
256	count = rcar_pci_count + RCAR_PCI_NR_CONTROLLERS;
257	private_data = kzalloc(count * sizeof(void *), GFP_KERNEL);
258	if (!private_data)
259	return -ENOMEM;
260
261	rcar_pci_count = count;
262	if (rcar_hw_pci.private_data) {
263	memcpy(private_data, rcar_hw_pci.private_data,
264	rcar_hw_pci.nr_controllers * sizeof(void *));
265	kfree(rcar_hw_pci.private_data);
266	}
267
268	rcar_hw_pci.private_data = private_data;
269
270	add_priv:
271	/* Add private data pointer to the array */
272	rcar_hw_pci.private_data[rcar_hw_pci.nr_controllers++] = priv;
273	return 0;
274	}
275
276	static int __init rcar_pci_probe(struct platform_device *pdev)
277	{	326	{
278	struct resource cfg_res, mem_res;	327	struct resource cfg_res, mem_res;
279	struct rcar_pci_priv *priv;	328	struct rcar_pci_priv *priv;
280	void __iomem *reg;	329	void __iomem *reg;
		330	struct hw_pci hw;
		331	void *hw_private[1];
281		332
282	cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);	333	cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
283	reg = devm_ioremap_resource(&pdev->dev, cfg_res);	334	reg = devm_ioremap_resource(&pdev->dev, cfg_res);
@@ -308,31 +359,34 @@ static int __init rcar_pci_probe(struct platform_device *pdev)
308	priv->reg = reg;	359	priv->reg = reg;
309	priv->dev = &pdev->dev;	360	priv->dev = &pdev->dev;
310		361
311	return rcar_pci_add_controller(priv);	362	if (priv->irq < 0) {
		363	dev_err(&pdev->dev, "no valid irq found\n");
		364	return priv->irq;
		365	}
		366
		367	priv->window_size = SZ_1G;
		368
		369	hw_private[0] = priv;
		370	memset(&hw, 0, sizeof(hw));
		371	hw.nr_controllers = ARRAY_SIZE(hw_private);
		372	hw.private_data = hw_private;
		373	hw.map_irq = rcar_pci_map_irq;
		374	hw.ops = &rcar_pci_ops;
		375	hw.setup = rcar_pci_setup;
		376	pci_common_init_dev(&pdev->dev, &hw);
		377	return 0;
312	}	378	}
313		379
314	static struct platform_driver rcar_pci_driver = {	380	static struct platform_driver rcar_pci_driver = {
315	.driver = {	381	.driver = {
316	.name = "pci-rcar-gen2",	382	.name = "pci-rcar-gen2",
		383	.owner = THIS_MODULE,
		384	.suppress_bind_attrs = true,
317	},	385	},
		386	.probe = rcar_pci_probe,
318	};	387	};
319		388
320	static int __init rcar_pci_init(void)	389	module_platform_driver(rcar_pci_driver);
321	{
322	int retval;
323
324	retval = platform_driver_probe(&rcar_pci_driver, rcar_pci_probe);
325	if (!retval)
326	pci_common_init(&rcar_hw_pci);
327
328	/* Private data pointer array is not needed any more */
329	kfree(rcar_hw_pci.private_data);
330	rcar_hw_pci.private_data = NULL;
331
332	return retval;
333	}
334
335	subsys_initcall(rcar_pci_init);
336		390
337	MODULE_LICENSE("GPL v2");	391	MODULE_LICENSE("GPL v2");
338	MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");	392	MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");


diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 2e48ecf09e2c..509a29d84509 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c
@@ -798,7 +798,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
798		798
799	/* setup RC BARs */	799	/* setup RC BARs */
800	dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);	800	dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
801	dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1);	801	dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
802		802
803	/* setup interrupt pins */	803	/* setup interrupt pins */
804	dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);	804	dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);