diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2014-01-07 19:34:06 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2014-01-07 19:34:06 -0500 |
| commit | 133a36051bc5db5c0a20df41079c246166eab23c (patch) | |
| tree | e9f51e954fa65a3f6f35a2f20f6a223de8ac992e /drivers/pci/host | |
| parent | 79bf7fc51118e4ffc61a0a8c943b94c394aa3ecc (diff) | |
| parent | 58275f2f0a6acd750b0acdc62d6457fb3e0f264e (diff) | |
Merge branch 'pci/host-designware' into next
* pci/host-designware:
PCI: designware: Fix indent code style
Diffstat (limited to 'drivers/pci/host')
| -rw-r--r-- | drivers/pci/host/pcie-designware.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 4a08d30548ce..17ce88f79d2b 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c | |||
| @@ -213,14 +213,14 @@ static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0) | |||
| 213 | } | 213 | } |
| 214 | 214 | ||
| 215 | static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, | 215 | static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, |
| 216 | unsigned int nvec, unsigned int pos) | 216 | unsigned int nvec, unsigned int pos) |
| 217 | { | 217 | { |
| 218 | unsigned int i, res, bit, val; | 218 | unsigned int i, res, bit, val; |
| 219 | 219 | ||
| 220 | for (i = 0; i < nvec; i++) { | 220 | for (i = 0; i < nvec; i++) { |
| 221 | irq_set_msi_desc_off(irq_base, i, NULL); | 221 | irq_set_msi_desc_off(irq_base, i, NULL); |
| 222 | clear_bit(pos + i, pp->msi_irq_in_use); | 222 | clear_bit(pos + i, pp->msi_irq_in_use); |
| 223 | /* Disable corresponding interrupt on MSI interrupt controller */ | 223 | /* Disable corresponding interrupt on MSI controller */ |
| 224 | res = ((pos + i) / 32) * 12; | 224 | res = ((pos + i) / 32) * 12; |
| 225 | bit = (pos + i) % 32; | 225 | bit = (pos + i) % 32; |
| 226 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); | 226 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); |