diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2015-02-10 17:31:28 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2015-02-10 17:31:28 -0500 |
commit | c08f8467939e7d2eebcba7cf2330242c4f53f2f7 (patch) | |
tree | 3430b9acdac374da5fda10d913b52f608494894c /drivers/pci/host/pcie-xilinx.c | |
parent | bdccc4edeb03ad68c55053b0260bdaaac547bbd9 (diff) | |
parent | cb8e92d8e4d9f8562071b6ab39e1b837e9e7af39 (diff) |
Merge tag 'pci-v3.20-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI changes from Bjorn Helgaas:
"Enumeration
- Move domain assignment from arm64 to generic code (Lorenzo Pieralisi)
- ARM: Remove artificial dependency on pci_sys_data domain (Lorenzo Pieralisi)
- ARM: Move to generic PCI domains (Lorenzo Pieralisi)
- Generate uppercase hex for modalias var in uevent (Ricardo Ribalda Delgado)
- Add and use generic config accessors on ARM, PowerPC (Rob Herring)
Resource management
- Free resources on failure in of_pci_get_host_bridge_resources() (Lorenzo Pieralisi)
- Fix infinite loop with ROM image of size 0 (Michel Dänzer)
PCI device hotplug
- Handle surprise add even if surprise removal isn't supported (Bjorn Helgaas)
Virtualization
- Mark AMD/ATI VGA devices that don't reset on D3hot->D0 transition (Alex Williamson)
- Add DMA alias quirk for Adaptec 3405 (Alex Williamson)
- Add Wellsburg (X99) to Intel PCH root port ACS quirk (Alex Williamson)
- Add ACS quirk for Emulex NICs (Vasundhara Volam)
MSI
- Fail MSI-X mappings if there's no space assigned to MSI-X BAR (Yijing Wang)
Freescale Layerscape host bridge driver
- Fix platform_no_drv_owner.cocci warnings (Julia Lawall)
NVIDIA Tegra host bridge driver
- Remove unnecessary tegra_pcie_fixup_bridge() (Lucas Stach)
Renesas R-Car host bridge driver
- Fix error handling of irq_of_parse_and_map() (Dmitry Torokhov)
TI Keystone host bridge driver
- Fix error handling of irq_of_parse_and_map() (Dmitry Torokhov)
- Fix misspelling of current function in debug output (Julia Lawall)
Xilinx AXI host bridge driver
- Fix harmless format string warning (Arnd Bergmann)
Miscellaneous
- Use standard parsing functions for ASPM sysfs setters (Chris J Arges)
- Add pci_device_to_OF_node() stub for !CONFIG_OF (Kevin Hao)
- Delete unnecessary NULL pointer checks (Markus Elfring)
- Add and use defines for PCIe Max_Read_Request_Size (Rafał Miłecki)
- Include clk.h instead of clk-private.h (Stephen Boyd)"
* tag 'pci-v3.20-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (48 commits)
PCI: Add pci_device_to_OF_node() stub for !CONFIG_OF
PCI: xilinx: Convert to use generic config accessors
PCI: xgene: Convert to use generic config accessors
PCI: tegra: Convert to use generic config accessors
PCI: rcar: Convert to use generic config accessors
PCI: generic: Convert to use generic config accessors
powerpc/powermac: Convert PCI to use generic config accessors
powerpc/fsl_pci: Convert PCI to use generic config accessors
ARM: ks8695: Convert PCI to use generic config accessors
ARM: sa1100: Convert PCI to use generic config accessors
ARM: integrator: Convert PCI to use generic config accessors
PCI: versatile: Add DT-based ARM Versatile PB PCIe host driver
ARM: dts: versatile: add PCI controller binding
of/pci: Free resources on failure in of_pci_get_host_bridge_resources()
PCI: versatile: Add DT docs for ARM Versatile PB PCIe driver
PCI: Fail MSI-X mappings if there's no space assigned to MSI-X BAR
r8169: use PCI define for Max_Read_Request_Size
[SCSI] esas2r: use PCI define for Max_Read_Request_Size
tile: use PCI define for Max_Read_Request_Size
rapidio/tsi721: use PCI define for Max_Read_Request_Size
...
Diffstat (limited to 'drivers/pci/host/pcie-xilinx.c')
-rw-r--r-- | drivers/pci/host/pcie-xilinx.c | 92 |
1 files changed, 11 insertions, 81 deletions
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index ef3ebaf9a738..eac4a4b957ca 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c | |||
@@ -148,10 +148,10 @@ static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *port) | |||
148 | */ | 148 | */ |
149 | static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port) | 149 | static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port) |
150 | { | 150 | { |
151 | u32 val = pcie_read(port, XILINX_PCIE_REG_RPEFR); | 151 | unsigned long val = pcie_read(port, XILINX_PCIE_REG_RPEFR); |
152 | 152 | ||
153 | if (val & XILINX_PCIE_RPEFR_ERR_VALID) { | 153 | if (val & XILINX_PCIE_RPEFR_ERR_VALID) { |
154 | dev_dbg(port->dev, "Requester ID %d\n", | 154 | dev_dbg(port->dev, "Requester ID %lu\n", |
155 | val & XILINX_PCIE_RPEFR_REQ_ID); | 155 | val & XILINX_PCIE_RPEFR_REQ_ID); |
156 | pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK, | 156 | pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK, |
157 | XILINX_PCIE_REG_RPEFR); | 157 | XILINX_PCIE_REG_RPEFR); |
@@ -189,7 +189,7 @@ static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) | |||
189 | } | 189 | } |
190 | 190 | ||
191 | /** | 191 | /** |
192 | * xilinx_pcie_config_base - Get configuration base | 192 | * xilinx_pcie_map_bus - Get configuration base |
193 | * @bus: PCI Bus structure | 193 | * @bus: PCI Bus structure |
194 | * @devfn: Device/function | 194 | * @devfn: Device/function |
195 | * @where: Offset from base | 195 | * @where: Offset from base |
@@ -197,96 +197,26 @@ static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) | |||
197 | * Return: Base address of the configuration space needed to be | 197 | * Return: Base address of the configuration space needed to be |
198 | * accessed. | 198 | * accessed. |
199 | */ | 199 | */ |
200 | static void __iomem *xilinx_pcie_config_base(struct pci_bus *bus, | 200 | static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus, |
201 | unsigned int devfn, int where) | 201 | unsigned int devfn, int where) |
202 | { | 202 | { |
203 | struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata); | 203 | struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata); |
204 | int relbus; | 204 | int relbus; |
205 | 205 | ||
206 | if (!xilinx_pcie_valid_device(bus, devfn)) | ||
207 | return NULL; | ||
208 | |||
206 | relbus = (bus->number << ECAM_BUS_NUM_SHIFT) | | 209 | relbus = (bus->number << ECAM_BUS_NUM_SHIFT) | |
207 | (devfn << ECAM_DEV_NUM_SHIFT); | 210 | (devfn << ECAM_DEV_NUM_SHIFT); |
208 | 211 | ||
209 | return port->reg_base + relbus + where; | 212 | return port->reg_base + relbus + where; |
210 | } | 213 | } |
211 | 214 | ||
212 | /** | ||
213 | * xilinx_pcie_read_config - Read configuration space | ||
214 | * @bus: PCI Bus structure | ||
215 | * @devfn: Device/function | ||
216 | * @where: Offset from base | ||
217 | * @size: Byte/word/dword | ||
218 | * @val: Value to be read | ||
219 | * | ||
220 | * Return: PCIBIOS_SUCCESSFUL on success | ||
221 | * PCIBIOS_DEVICE_NOT_FOUND on failure | ||
222 | */ | ||
223 | static int xilinx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, | ||
224 | int where, int size, u32 *val) | ||
225 | { | ||
226 | void __iomem *addr; | ||
227 | |||
228 | if (!xilinx_pcie_valid_device(bus, devfn)) { | ||
229 | *val = 0xFFFFFFFF; | ||
230 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
231 | } | ||
232 | |||
233 | addr = xilinx_pcie_config_base(bus, devfn, where); | ||
234 | |||
235 | switch (size) { | ||
236 | case 1: | ||
237 | *val = readb(addr); | ||
238 | break; | ||
239 | case 2: | ||
240 | *val = readw(addr); | ||
241 | break; | ||
242 | default: | ||
243 | *val = readl(addr); | ||
244 | break; | ||
245 | } | ||
246 | |||
247 | return PCIBIOS_SUCCESSFUL; | ||
248 | } | ||
249 | |||
250 | /** | ||
251 | * xilinx_pcie_write_config - Write configuration space | ||
252 | * @bus: PCI Bus structure | ||
253 | * @devfn: Device/function | ||
254 | * @where: Offset from base | ||
255 | * @size: Byte/word/dword | ||
256 | * @val: Value to be written to device | ||
257 | * | ||
258 | * Return: PCIBIOS_SUCCESSFUL on success | ||
259 | * PCIBIOS_DEVICE_NOT_FOUND on failure | ||
260 | */ | ||
261 | static int xilinx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, | ||
262 | int where, int size, u32 val) | ||
263 | { | ||
264 | void __iomem *addr; | ||
265 | |||
266 | if (!xilinx_pcie_valid_device(bus, devfn)) | ||
267 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
268 | |||
269 | addr = xilinx_pcie_config_base(bus, devfn, where); | ||
270 | |||
271 | switch (size) { | ||
272 | case 1: | ||
273 | writeb(val, addr); | ||
274 | break; | ||
275 | case 2: | ||
276 | writew(val, addr); | ||
277 | break; | ||
278 | default: | ||
279 | writel(val, addr); | ||
280 | break; | ||
281 | } | ||
282 | |||
283 | return PCIBIOS_SUCCESSFUL; | ||
284 | } | ||
285 | |||
286 | /* PCIe operations */ | 215 | /* PCIe operations */ |
287 | static struct pci_ops xilinx_pcie_ops = { | 216 | static struct pci_ops xilinx_pcie_ops = { |
288 | .read = xilinx_pcie_read_config, | 217 | .map_bus = xilinx_pcie_map_bus, |
289 | .write = xilinx_pcie_write_config, | 218 | .read = pci_generic_config_read, |
219 | .write = pci_generic_config_write, | ||
290 | }; | 220 | }; |
291 | 221 | ||
292 | /* MSI functions */ | 222 | /* MSI functions */ |