[PATCH] PCI: Block config access during BIST

Some PCI adapters (eg.  ipr scsi adapters) have an exposure today in that they
issue BIST to the adapter to reset the card.  If, during the time it takes to
complete BIST, userspace attempts to access PCI config space, the host bus
bridge will master abort the access since the ipr adapter does not respond on
the PCI bus for a brief period of time when running BIST.  On PPC64 hardware,
this master abort results in the host PCI bridge isolating that PCI device
from the rest of the system, making the device unusable until Linux is
rebooted.  This patch is an attempt to close that exposure by introducing some
blocking code in the PCI code.  When blocked, writes will be humored and reads
will return the cached value.  Ben Herrenschmidt has also mentioned that he
plans to use this in PPC power management.

Signed-off-by: Brian King <brking@us.ibm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

 drivers/pci/access.c    |   89 ++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/pci/pci-sysfs.c |   20 +++++-----
 drivers/pci/pci.h       |    7 +++
 drivers/pci/proc.c      |   28 +++++++--------
 drivers/pci/syscall.c   |   14 +++----
 include/linux/pci.h     |    7 +++
 6 files changed, 134 insertions(+), 31 deletions(-)

1 files changed, 89 insertions, 0 deletions

diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 24a76de49f41..2a42add7f563 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -60,3 +60,92 @@ EXPORT_SYMBOL(pci_bus_read_config_dword);
 EXPORT_SYMBOL(pci_bus_write_config_byte);
 EXPORT_SYMBOL(pci_bus_write_config_word);
 EXPORT_SYMBOL(pci_bus_write_config_dword);
+
+static u32 pci_user_cached_config(struct pci_dev *dev, int pos)
+{
+        u32 data;
+
+        data = dev->saved_config_space[pos/sizeof(dev->saved_config_space[0])];
+        data >>= (pos % sizeof(dev->saved_config_space[0])) * 8;
+        return data;
+}
+
+#define PCI_USER_READ_CONFIG(size,type)                                 \
+int pci_user_read_config_##size                                         \
+        (struct pci_dev *dev, int pos, type *val)                       \
+{                                                                       \
+        unsigned long flags;                                            \
+        int ret = 0;                                                    \
+        u32 data = -1;                                                  \
+        if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;       \
+        spin_lock_irqsave(&pci_lock, flags);                            \
+        if (likely(!dev->block_ucfg_access))                            \
+                ret = dev->bus->ops->read(dev->bus, dev->devfn,         \
+                                        pos, sizeof(type), &data);      \
+        else if (pos < sizeof(dev->saved_config_space))                 \
+                data = pci_user_cached_config(dev, pos);                \
+        spin_unlock_irqrestore(&pci_lock, flags);                       \
+        *val = (type)data;                                              \
+        return ret;                                                     \
+}
+
+#define PCI_USER_WRITE_CONFIG(size,type)                                \
+int pci_user_write_config_##size                                        \
+        (struct pci_dev *dev, int pos, type val)                        \
+{                                                                       \
+        unsigned long flags;                                            \
+        int ret = -EIO;                                                 \
+        if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;       \
+        spin_lock_irqsave(&pci_lock, flags);                            \
+        if (likely(!dev->block_ucfg_access))                            \
+                ret = dev->bus->ops->write(dev->bus, dev->devfn,        \
+                                        pos, sizeof(type), val);        \
+        spin_unlock_irqrestore(&pci_lock, flags);                       \
+        return ret;                                                     \
+}
+
+PCI_USER_READ_CONFIG(byte, u8)
+PCI_USER_READ_CONFIG(word, u16)
+PCI_USER_READ_CONFIG(dword, u32)
+PCI_USER_WRITE_CONFIG(byte, u8)
+PCI_USER_WRITE_CONFIG(word, u16)
+PCI_USER_WRITE_CONFIG(dword, u32)
+
+/**
+ * pci_block_user_cfg_access - Block userspace PCI config reads/writes
+ * @dev:        pci device struct
+ *
+ * This function blocks any userspace PCI config accesses from occurring.
+ * When blocked, any writes will be bit bucketed and reads will return the
+ * data saved using pci_save_state for the first 64 bytes of config
+ * space and return 0xff for all other config reads.
+ **/
+void pci_block_user_cfg_access(struct pci_dev *dev)
+{
+        unsigned long flags;
+
+        pci_save_state(dev);
+
+        /* spinlock to synchronize with anyone reading config space now */
+        spin_lock_irqsave(&pci_lock, flags);
+        dev->block_ucfg_access = 1;
+        spin_unlock_irqrestore(&pci_lock, flags);
+}
+EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);
+
+/**
+ * pci_unblock_user_cfg_access - Unblock userspace PCI config reads/writes
+ * @dev:        pci device struct
+ *
+ * This function allows userspace PCI config accesses to resume.
+ **/
+void pci_unblock_user_cfg_access(struct pci_dev *dev)
+{
+        unsigned long flags;
+
+        /* spinlock to synchronize with anyone reading saved config space */
+        spin_lock_irqsave(&pci_lock, flags);
+        dev->block_ucfg_access = 0;
+        spin_unlock_irqrestore(&pci_lock, flags);
+}
+EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access);