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authorHelge Deller <deller@gmx.de>2013-05-02 16:41:45 -0400
committerHelge Deller <deller@gmx.de>2013-05-06 17:08:32 -0400
commit6a45716abbf9dc0f397946306db1f78b2eba3086 (patch)
treeba6f1e47ff957dfc07e538d1d19dfc4615425cae /drivers/parisc/sba_iommu.c
parent7f64fb41aad9a8504dd76e81b2391eae64e1498a (diff)
parisc: fix partly 16/64k PAGE_SIZE boot
This patch fixes partly PAGE_SIZEs of 16K or 64K by adjusting the assembler PTE lookup code and the assembler TEMPALIAS code. Furthermore some data alignments for PAGE_SIZE have been limited to 4K (or less) to not waste too much memory with greater page sizes. As a side note, the palo loader can (currently) only handle up to 10 ELF segments which is fixed with tighter aligning as well. My testings indicated that the ldci command in the sba iommu coding needed adjustment by the PAGE_SHIFT value and that the I/O PDIR Page size was only set to 4K for my machine (C3000). All this fixes partly the boot, but there are still quite some caching problems left. Examples are e.g. the symbios logic driver which is failing: sym0: <896> rev 0x7 at pci 0000:00:0f.0 irq 69 sym0: PA-RISC Firmware, ID 7, Fast-40, SE, parity checking CACHE TEST FAILED: DMA error (dstat=0x81).sym0: CACHE INCORRECTLY CONFIGURED. and the tulip network driver which doesn't seem to work correctly either: Sending BOOTP requests .net eth0: Setting full-duplex based on MII#1 link partner capability of 05e1 ..... timed out! Beside those kernel fixes glibc will need fixes too to be able to handle >4K page sizes. Signed-off-by: Helge Deller <deller@gmx.de>
Diffstat (limited to 'drivers/parisc/sba_iommu.c')
-rw-r--r--drivers/parisc/sba_iommu.c19
1 files changed, 15 insertions, 4 deletions
diff --git a/drivers/parisc/sba_iommu.c b/drivers/parisc/sba_iommu.c
index 42cfcd9eb9aa..1ff1b67e8b27 100644
--- a/drivers/parisc/sba_iommu.c
+++ b/drivers/parisc/sba_iommu.c
@@ -575,7 +575,7 @@ sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
575 575
576 mtsp(sid,1); 576 mtsp(sid,1);
577 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); 577 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
578 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */ 578 pa |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */
579 579
580 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */ 580 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
581 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */ 581 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
@@ -1376,7 +1376,7 @@ static void
1376sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1376sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1377{ 1377{
1378 u32 iova_space_size, iova_space_mask; 1378 u32 iova_space_size, iova_space_mask;
1379 unsigned int pdir_size, iov_order; 1379 unsigned int pdir_size, iov_order, tcnfg;
1380 1380
1381 /* 1381 /*
1382 ** Determine IOVA Space size from memory size. 1382 ** Determine IOVA Space size from memory size.
@@ -1468,8 +1468,19 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1468 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE); 1468 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
1469 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK); 1469 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1470 1470
1471 /* Set I/O PDIR Page size to 4K */ 1471 /* Set I/O PDIR Page size to system page size */
1472 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG); 1472 switch (PAGE_SHIFT) {
1473 case 12: tcnfg = 0; break; /* 4K */
1474 case 13: tcnfg = 1; break; /* 8K */
1475 case 14: tcnfg = 2; break; /* 16K */
1476 case 16: tcnfg = 3; break; /* 64K */
1477 default:
1478 panic(__FILE__ "Unsupported system page size %d",
1479 1 << PAGE_SHIFT);
1480 break;
1481 }
1482 /* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */
1483 WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG);
1473 1484
1474 /* 1485 /*
1475 ** Clear I/O TLB of any possible entries. 1486 ** Clear I/O TLB of any possible entries.