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authorGiuseppe CAVALLARO <peppe.cavallaro@st.com>2010-09-16 23:23:39 -0400
committerDavid S. Miller <davem@davemloft.net>2010-09-17 19:12:56 -0400
commitdfb8fb96ae2b5126cd0c08c0ccd7c42e1f46568a (patch)
tree9727f43bae819ece67c1c9bc26b3cb52e236e5ce /drivers/net
parent67c9660831f6b6b76866a0838466c83765ffbbd3 (diff)
stmmac: add CSR Clock range selection
This patch adds the CSR Clock range selection. Original patch from Johannes Stezenbach fixed the CSR in the stmmac_mdio. We agreed to provide this through the platform instead of. Also thanks to Johannes for having tested it on ARM. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Johannes Stezenbach <js@sig21.net> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/stmmac/stmmac.h1
-rw-r--r--drivers/net/stmmac/stmmac_main.c1
-rw-r--r--drivers/net/stmmac/stmmac_mdio.c5
3 files changed, 5 insertions, 2 deletions
diff --git a/drivers/net/stmmac/stmmac.h b/drivers/net/stmmac/stmmac.h
index d0ddab0d21c2..12d1cb00c0d7 100644
--- a/drivers/net/stmmac/stmmac.h
+++ b/drivers/net/stmmac/stmmac.h
@@ -78,6 +78,7 @@ struct stmmac_priv {
78 unsigned int flow_ctrl; 78 unsigned int flow_ctrl;
79 unsigned int pause; 79 unsigned int pause;
80 struct mii_bus *mii; 80 struct mii_bus *mii;
81 int mii_clk_csr;
81 82
82 u32 msg_enable; 83 u32 msg_enable;
83 spinlock_t lock; 84 spinlock_t lock;
diff --git a/drivers/net/stmmac/stmmac_main.c b/drivers/net/stmmac/stmmac_main.c
index 03c160c6d75c..a169b1441d50 100644
--- a/drivers/net/stmmac/stmmac_main.c
+++ b/drivers/net/stmmac/stmmac_main.c
@@ -1704,6 +1704,7 @@ static int stmmac_dvr_probe(struct platform_device *pdev)
1704 plat_dat = pdev->dev.platform_data; 1704 plat_dat = pdev->dev.platform_data;
1705 priv->bus_id = plat_dat->bus_id; 1705 priv->bus_id = plat_dat->bus_id;
1706 priv->pbl = plat_dat->pbl; /* TLI */ 1706 priv->pbl = plat_dat->pbl; /* TLI */
1707 priv->mii_clk_csr = plat_dat->clk_csr;
1707 priv->is_gmac = plat_dat->has_gmac; /* GMAC is on board */ 1708 priv->is_gmac = plat_dat->has_gmac; /* GMAC is on board */
1708 priv->enh_desc = plat_dat->enh_desc; 1709 priv->enh_desc = plat_dat->enh_desc;
1709 priv->ioaddr = addr; 1710 priv->ioaddr = addr;
diff --git a/drivers/net/stmmac/stmmac_mdio.c b/drivers/net/stmmac/stmmac_mdio.c
index 03dea1401571..d7441616357d 100644
--- a/drivers/net/stmmac/stmmac_mdio.c
+++ b/drivers/net/stmmac/stmmac_mdio.c
@@ -53,7 +53,7 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
53 int data; 53 int data;
54 u16 regValue = (((phyaddr << 11) & (0x0000F800)) | 54 u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
55 ((phyreg << 6) & (0x000007C0))); 55 ((phyreg << 6) & (0x000007C0)));
56 regValue |= MII_BUSY; /* in case of GMAC */ 56 regValue |= MII_BUSY | ((priv->mii_clk_csr & 7) << 2);
57 57
58 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); 58 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
59 writel(regValue, priv->ioaddr + mii_address); 59 writel(regValue, priv->ioaddr + mii_address);
@@ -85,7 +85,8 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
85 (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0))) 85 (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
86 | MII_WRITE; 86 | MII_WRITE;
87 87
88 value |= MII_BUSY; 88 value |= MII_BUSY | ((priv->mii_clk_csr & 7) << 2);
89
89 90
90 /* Wait until any existing MII operation is complete */ 91 /* Wait until any existing MII operation is complete */
91 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); 92 do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);