diff options
author | Al Viro <viro@ftp.linux.org.uk> | 2008-01-13 09:17:45 -0500 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2008-01-18 14:44:33 -0500 |
commit | d50956af74859b4e9ba544a0211a94bc2621c1d9 (patch) | |
tree | a2f34ca5053722e3e20490ff107642288e10dd0f /drivers/net | |
parent | b665982409fd5e4d3f1b71591d2f6badf9d2ee99 (diff) |
dl2k: BMCR_t fixes
broken use of bitfields; FUBAR on big-endian (and not valid C,
strictly speaking).
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/dl2k.c | 76 | ||||
-rw-r--r-- | drivers/net/dl2k.h | 17 |
2 files changed, 32 insertions, 61 deletions
diff --git a/drivers/net/dl2k.c b/drivers/net/dl2k.c index 47cce9cad30f..badc60103d34 100644 --- a/drivers/net/dl2k.c +++ b/drivers/net/dl2k.c | |||
@@ -1455,7 +1455,6 @@ mii_get_media (struct net_device *dev) | |||
1455 | { | 1455 | { |
1456 | ANAR_t negotiate; | 1456 | ANAR_t negotiate; |
1457 | BMSR_t bmsr; | 1457 | BMSR_t bmsr; |
1458 | BMCR_t bmcr; | ||
1459 | MSCR_t mscr; | 1458 | MSCR_t mscr; |
1460 | MSSR_t mssr; | 1459 | MSSR_t mssr; |
1461 | int phy_addr; | 1460 | int phy_addr; |
@@ -1508,15 +1507,18 @@ mii_get_media (struct net_device *dev) | |||
1508 | } | 1507 | } |
1509 | /* else tx_flow, rx_flow = user select */ | 1508 | /* else tx_flow, rx_flow = user select */ |
1510 | } else { | 1509 | } else { |
1511 | bmcr.image = mii_read (dev, phy_addr, MII_BMCR); | 1510 | __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR); |
1512 | if (bmcr.bits.speed100 == 1 && bmcr.bits.speed1000 == 0) { | 1511 | switch (bmcr & (MII_BMCR_SPEED_100 | MII_BMCR_SPEED_1000)) { |
1512 | case MII_BMCR_SPEED_1000: | ||
1513 | printk (KERN_INFO "Operating at 1000 Mbps, "); | ||
1514 | break; | ||
1515 | case MII_BMCR_SPEED_100: | ||
1513 | printk (KERN_INFO "Operating at 100 Mbps, "); | 1516 | printk (KERN_INFO "Operating at 100 Mbps, "); |
1514 | } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 0) { | 1517 | break; |
1518 | case 0: | ||
1515 | printk (KERN_INFO "Operating at 10 Mbps, "); | 1519 | printk (KERN_INFO "Operating at 10 Mbps, "); |
1516 | } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 1) { | ||
1517 | printk (KERN_INFO "Operating at 1000 Mbps, "); | ||
1518 | } | 1520 | } |
1519 | if (bmcr.bits.duplex_mode) { | 1521 | if (bmcr & MII_BMCR_DUPLEX_MODE) { |
1520 | printk ("Full duplex\n"); | 1522 | printk ("Full duplex\n"); |
1521 | } else { | 1523 | } else { |
1522 | printk ("Half duplex\n"); | 1524 | printk ("Half duplex\n"); |
@@ -1538,7 +1540,7 @@ static int | |||
1538 | mii_set_media (struct net_device *dev) | 1540 | mii_set_media (struct net_device *dev) |
1539 | { | 1541 | { |
1540 | PHY_SCR_t pscr; | 1542 | PHY_SCR_t pscr; |
1541 | BMCR_t bmcr; | 1543 | __u16 bmcr; |
1542 | BMSR_t bmsr; | 1544 | BMSR_t bmsr; |
1543 | ANAR_t anar; | 1545 | ANAR_t anar; |
1544 | int phy_addr; | 1546 | int phy_addr; |
@@ -1567,11 +1569,8 @@ mii_set_media (struct net_device *dev) | |||
1567 | 1569 | ||
1568 | /* Soft reset PHY */ | 1570 | /* Soft reset PHY */ |
1569 | mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET); | 1571 | mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET); |
1570 | bmcr.image = 0; | 1572 | bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | MII_BMCR_RESET; |
1571 | bmcr.bits.an_enable = 1; | 1573 | mii_write (dev, phy_addr, MII_BMCR, bmcr); |
1572 | bmcr.bits.restart_an = 1; | ||
1573 | bmcr.bits.reset = 1; | ||
1574 | mii_write (dev, phy_addr, MII_BMCR, bmcr.image); | ||
1575 | mdelay(1); | 1574 | mdelay(1); |
1576 | } else { | 1575 | } else { |
1577 | /* Force speed setting */ | 1576 | /* Force speed setting */ |
@@ -1581,35 +1580,30 @@ mii_set_media (struct net_device *dev) | |||
1581 | mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image); | 1580 | mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image); |
1582 | 1581 | ||
1583 | /* 2) PHY Reset */ | 1582 | /* 2) PHY Reset */ |
1584 | bmcr.image = mii_read (dev, phy_addr, MII_BMCR); | 1583 | bmcr = mii_read (dev, phy_addr, MII_BMCR); |
1585 | bmcr.bits.reset = 1; | 1584 | bmcr |= MII_BMCR_RESET; |
1586 | mii_write (dev, phy_addr, MII_BMCR, bmcr.image); | 1585 | mii_write (dev, phy_addr, MII_BMCR, bmcr); |
1587 | 1586 | ||
1588 | /* 3) Power Down */ | 1587 | /* 3) Power Down */ |
1589 | bmcr.image = 0x1940; /* must be 0x1940 */ | 1588 | bmcr = 0x1940; /* must be 0x1940 */ |
1590 | mii_write (dev, phy_addr, MII_BMCR, bmcr.image); | 1589 | mii_write (dev, phy_addr, MII_BMCR, bmcr); |
1591 | mdelay (100); /* wait a certain time */ | 1590 | mdelay (100); /* wait a certain time */ |
1592 | 1591 | ||
1593 | /* 4) Advertise nothing */ | 1592 | /* 4) Advertise nothing */ |
1594 | mii_write (dev, phy_addr, MII_ANAR, 0); | 1593 | mii_write (dev, phy_addr, MII_ANAR, 0); |
1595 | 1594 | ||
1596 | /* 5) Set media and Power Up */ | 1595 | /* 5) Set media and Power Up */ |
1597 | bmcr.image = 0; | 1596 | bmcr = MII_BMCR_POWER_DOWN; |
1598 | bmcr.bits.power_down = 1; | ||
1599 | if (np->speed == 100) { | 1597 | if (np->speed == 100) { |
1600 | bmcr.bits.speed100 = 1; | 1598 | bmcr |= MII_BMCR_SPEED_100; |
1601 | bmcr.bits.speed1000 = 0; | ||
1602 | printk (KERN_INFO "Manual 100 Mbps, "); | 1599 | printk (KERN_INFO "Manual 100 Mbps, "); |
1603 | } else if (np->speed == 10) { | 1600 | } else if (np->speed == 10) { |
1604 | bmcr.bits.speed100 = 0; | ||
1605 | bmcr.bits.speed1000 = 0; | ||
1606 | printk (KERN_INFO "Manual 10 Mbps, "); | 1601 | printk (KERN_INFO "Manual 10 Mbps, "); |
1607 | } | 1602 | } |
1608 | if (np->full_duplex) { | 1603 | if (np->full_duplex) { |
1609 | bmcr.bits.duplex_mode = 1; | 1604 | bmcr |= MII_BMCR_DUPLEX_MODE; |
1610 | printk ("Full duplex\n"); | 1605 | printk ("Full duplex\n"); |
1611 | } else { | 1606 | } else { |
1612 | bmcr.bits.duplex_mode = 0; | ||
1613 | printk ("Half duplex\n"); | 1607 | printk ("Half duplex\n"); |
1614 | } | 1608 | } |
1615 | #if 0 | 1609 | #if 0 |
@@ -1618,7 +1612,7 @@ mii_set_media (struct net_device *dev) | |||
1618 | mscr.bits.cfg_enable = 1; | 1612 | mscr.bits.cfg_enable = 1; |
1619 | mscr.bits.cfg_value = 0; | 1613 | mscr.bits.cfg_value = 0; |
1620 | #endif | 1614 | #endif |
1621 | mii_write (dev, phy_addr, MII_BMCR, bmcr.image); | 1615 | mii_write (dev, phy_addr, MII_BMCR, bmcr); |
1622 | mdelay(10); | 1616 | mdelay(10); |
1623 | } | 1617 | } |
1624 | return 0; | 1618 | return 0; |
@@ -1629,7 +1623,6 @@ mii_get_media_pcs (struct net_device *dev) | |||
1629 | { | 1623 | { |
1630 | ANAR_PCS_t negotiate; | 1624 | ANAR_PCS_t negotiate; |
1631 | BMSR_t bmsr; | 1625 | BMSR_t bmsr; |
1632 | BMCR_t bmcr; | ||
1633 | int phy_addr; | 1626 | int phy_addr; |
1634 | struct netdev_private *np; | 1627 | struct netdev_private *np; |
1635 | 1628 | ||
@@ -1661,9 +1654,9 @@ mii_get_media_pcs (struct net_device *dev) | |||
1661 | } | 1654 | } |
1662 | /* else tx_flow, rx_flow = user select */ | 1655 | /* else tx_flow, rx_flow = user select */ |
1663 | } else { | 1656 | } else { |
1664 | bmcr.image = mii_read (dev, phy_addr, PCS_BMCR); | 1657 | __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR); |
1665 | printk (KERN_INFO "Operating at 1000 Mbps, "); | 1658 | printk (KERN_INFO "Operating at 1000 Mbps, "); |
1666 | if (bmcr.bits.duplex_mode) { | 1659 | if (bmcr & MII_BMCR_DUPLEX_MODE) { |
1667 | printk ("Full duplex\n"); | 1660 | printk ("Full duplex\n"); |
1668 | } else { | 1661 | } else { |
1669 | printk ("Half duplex\n"); | 1662 | printk ("Half duplex\n"); |
@@ -1684,7 +1677,7 @@ mii_get_media_pcs (struct net_device *dev) | |||
1684 | static int | 1677 | static int |
1685 | mii_set_media_pcs (struct net_device *dev) | 1678 | mii_set_media_pcs (struct net_device *dev) |
1686 | { | 1679 | { |
1687 | BMCR_t bmcr; | 1680 | __u16 bmcr; |
1688 | ESR_t esr; | 1681 | ESR_t esr; |
1689 | ANAR_PCS_t anar; | 1682 | ANAR_PCS_t anar; |
1690 | int phy_addr; | 1683 | int phy_addr; |
@@ -1707,29 +1700,24 @@ mii_set_media_pcs (struct net_device *dev) | |||
1707 | 1700 | ||
1708 | /* Soft reset PHY */ | 1701 | /* Soft reset PHY */ |
1709 | mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET); | 1702 | mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET); |
1710 | bmcr.image = 0; | 1703 | bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | |
1711 | bmcr.bits.an_enable = 1; | 1704 | MII_BMCR_RESET; |
1712 | bmcr.bits.restart_an = 1; | 1705 | mii_write (dev, phy_addr, MII_BMCR, bmcr); |
1713 | bmcr.bits.reset = 1; | ||
1714 | mii_write (dev, phy_addr, MII_BMCR, bmcr.image); | ||
1715 | mdelay(1); | 1706 | mdelay(1); |
1716 | } else { | 1707 | } else { |
1717 | /* Force speed setting */ | 1708 | /* Force speed setting */ |
1718 | /* PHY Reset */ | 1709 | /* PHY Reset */ |
1719 | bmcr.image = 0; | 1710 | bmcr = MII_BMCR_RESET; |
1720 | bmcr.bits.reset = 1; | 1711 | mii_write (dev, phy_addr, MII_BMCR, bmcr); |
1721 | mii_write (dev, phy_addr, MII_BMCR, bmcr.image); | ||
1722 | mdelay(10); | 1712 | mdelay(10); |
1723 | bmcr.image = 0; | ||
1724 | bmcr.bits.an_enable = 0; | ||
1725 | if (np->full_duplex) { | 1713 | if (np->full_duplex) { |
1726 | bmcr.bits.duplex_mode = 1; | 1714 | bmcr = MII_BMCR_DUPLEX_MODE; |
1727 | printk (KERN_INFO "Manual full duplex\n"); | 1715 | printk (KERN_INFO "Manual full duplex\n"); |
1728 | } else { | 1716 | } else { |
1729 | bmcr.bits.duplex_mode = 0; | 1717 | bmcr = 0; |
1730 | printk (KERN_INFO "Manual half duplex\n"); | 1718 | printk (KERN_INFO "Manual half duplex\n"); |
1731 | } | 1719 | } |
1732 | mii_write (dev, phy_addr, MII_BMCR, bmcr.image); | 1720 | mii_write (dev, phy_addr, MII_BMCR, bmcr); |
1733 | mdelay(10); | 1721 | mdelay(10); |
1734 | 1722 | ||
1735 | /* Advertise nothing */ | 1723 | /* Advertise nothing */ |
diff --git a/drivers/net/dl2k.h b/drivers/net/dl2k.h index 014b77ce96df..931fd0e58f3c 100644 --- a/drivers/net/dl2k.h +++ b/drivers/net/dl2k.h | |||
@@ -298,23 +298,6 @@ enum _pcs_reg { | |||
298 | }; | 298 | }; |
299 | 299 | ||
300 | /* Basic Mode Control Register */ | 300 | /* Basic Mode Control Register */ |
301 | typedef union t_MII_BMCR { | ||
302 | u16 image; | ||
303 | struct { | ||
304 | u16 _bit_5_0:6; // bit 5:0 | ||
305 | u16 speed1000:1; // bit 6 | ||
306 | u16 col_test_enable:1; // bit 7 | ||
307 | u16 duplex_mode:1; // bit 8 | ||
308 | u16 restart_an:1; // bit 9 | ||
309 | u16 isolate:1; // bit 10 | ||
310 | u16 power_down:1; // bit 11 | ||
311 | u16 an_enable:1; // bit 12 | ||
312 | u16 speed100:1; // bit 13 | ||
313 | u16 loopback:1; // bit 14 | ||
314 | u16 reset:1; // bit 15 | ||
315 | } bits; | ||
316 | } BMCR_t, *PBMCR_t; | ||
317 | |||
318 | enum _mii_bmcr { | 301 | enum _mii_bmcr { |
319 | MII_BMCR_RESET = 0x8000, | 302 | MII_BMCR_RESET = 0x8000, |
320 | MII_BMCR_LOOP_BACK = 0x4000, | 303 | MII_BMCR_LOOP_BACK = 0x4000, |