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authorMichael Chan <mchan@broadcom.com>2008-05-17 01:17:45 -0400
committerDavid S. Miller <davem@davemloft.net>2008-05-17 01:17:45 -0400
commit9a120bc570627342c17befaa6af9b0a556dfda48 (patch)
treea732ea873d0a963071963833b854dfe17b132013 /drivers/net
parentf42a44494bcdf03fc851c03d438464d59c0ceaf5 (diff)
bnx2: Allow phy reset to be skipped during chip reset.
Andy Gospodarek <andy@greyhouse.net> found that netconsole would panic when resetting bnx2 devices. >From Andy: "The issue is the bnx2_set_link in bnx2_init_nic will print a link-status message before we are fully initialized and ready to start polling. Polling is currently disabled in this state, but since the __LINK_STATE_RX_SCHED is overloaded to not only try and disable polling but also to make the system aware there is something waiting to be polled, we really have to fix this in drivers. The problematic call is the one to netif_rx_complete as it tries to remove an entry from the poll_list when there isn't one." While this netconsole problem should be fixed separately, we really should not reset the PHY when changing ring sizes, MTU, or other similar settings. The PHY reset causes several seconds of unnecessary link disruptions. Signed-off-by: Michael Chan <mchan@broadcom.com> Acked-by: Andy Gospodarek <andy@greyhouse.net> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/bnx2.c50
1 files changed, 27 insertions, 23 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 4b46e68183e0..934c2bfc464d 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -1875,7 +1875,7 @@ bnx2_setup_phy(struct bnx2 *bp, u8 port)
1875} 1875}
1876 1876
1877static int 1877static int
1878bnx2_init_5709s_phy(struct bnx2 *bp) 1878bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1879{ 1879{
1880 u32 val; 1880 u32 val;
1881 1881
@@ -1890,7 +1890,8 @@ bnx2_init_5709s_phy(struct bnx2 *bp)
1890 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); 1890 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1891 1891
1892 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1892 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1893 bnx2_reset_phy(bp); 1893 if (reset_phy)
1894 bnx2_reset_phy(bp);
1894 1895
1895 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); 1896 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1896 1897
@@ -1924,11 +1925,12 @@ bnx2_init_5709s_phy(struct bnx2 *bp)
1924} 1925}
1925 1926
1926static int 1927static int
1927bnx2_init_5708s_phy(struct bnx2 *bp) 1928bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
1928{ 1929{
1929 u32 val; 1930 u32 val;
1930 1931
1931 bnx2_reset_phy(bp); 1932 if (reset_phy)
1933 bnx2_reset_phy(bp);
1932 1934
1933 bp->mii_up1 = BCM5708S_UP1; 1935 bp->mii_up1 = BCM5708S_UP1;
1934 1936
@@ -1981,9 +1983,10 @@ bnx2_init_5708s_phy(struct bnx2 *bp)
1981} 1983}
1982 1984
1983static int 1985static int
1984bnx2_init_5706s_phy(struct bnx2 *bp) 1986bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
1985{ 1987{
1986 bnx2_reset_phy(bp); 1988 if (reset_phy)
1989 bnx2_reset_phy(bp);
1987 1990
1988 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; 1991 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1989 1992
@@ -2018,11 +2021,12 @@ bnx2_init_5706s_phy(struct bnx2 *bp)
2018} 2021}
2019 2022
2020static int 2023static int
2021bnx2_init_copper_phy(struct bnx2 *bp) 2024bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2022{ 2025{
2023 u32 val; 2026 u32 val;
2024 2027
2025 bnx2_reset_phy(bp); 2028 if (reset_phy)
2029 bnx2_reset_phy(bp);
2026 2030
2027 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) { 2031 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2028 bnx2_write_phy(bp, 0x18, 0x0c00); 2032 bnx2_write_phy(bp, 0x18, 0x0c00);
@@ -2070,7 +2074,7 @@ bnx2_init_copper_phy(struct bnx2 *bp)
2070 2074
2071 2075
2072static int 2076static int
2073bnx2_init_phy(struct bnx2 *bp) 2077bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2074{ 2078{
2075 u32 val; 2079 u32 val;
2076 int rc = 0; 2080 int rc = 0;
@@ -2096,14 +2100,14 @@ bnx2_init_phy(struct bnx2 *bp)
2096 2100
2097 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 2101 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2098 if (CHIP_NUM(bp) == CHIP_NUM_5706) 2102 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2099 rc = bnx2_init_5706s_phy(bp); 2103 rc = bnx2_init_5706s_phy(bp, reset_phy);
2100 else if (CHIP_NUM(bp) == CHIP_NUM_5708) 2104 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2101 rc = bnx2_init_5708s_phy(bp); 2105 rc = bnx2_init_5708s_phy(bp, reset_phy);
2102 else if (CHIP_NUM(bp) == CHIP_NUM_5709) 2106 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2103 rc = bnx2_init_5709s_phy(bp); 2107 rc = bnx2_init_5709s_phy(bp, reset_phy);
2104 } 2108 }
2105 else { 2109 else {
2106 rc = bnx2_init_copper_phy(bp); 2110 rc = bnx2_init_copper_phy(bp, reset_phy);
2107 } 2111 }
2108 2112
2109setup_phy: 2113setup_phy:
@@ -4873,7 +4877,7 @@ bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4873} 4877}
4874 4878
4875static int 4879static int
4876bnx2_init_nic(struct bnx2 *bp) 4880bnx2_init_nic(struct bnx2 *bp, int reset_phy)
4877{ 4881{
4878 int rc; 4882 int rc;
4879 4883
@@ -4881,7 +4885,7 @@ bnx2_init_nic(struct bnx2 *bp)
4881 return rc; 4885 return rc;
4882 4886
4883 spin_lock_bh(&bp->phy_lock); 4887 spin_lock_bh(&bp->phy_lock);
4884 bnx2_init_phy(bp); 4888 bnx2_init_phy(bp, reset_phy);
4885 bnx2_set_link(bp); 4889 bnx2_set_link(bp);
4886 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 4890 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
4887 bnx2_remote_phy_event(bp); 4891 bnx2_remote_phy_event(bp);
@@ -5269,7 +5273,7 @@ bnx2_test_loopback(struct bnx2 *bp)
5269 5273
5270 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); 5274 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5271 spin_lock_bh(&bp->phy_lock); 5275 spin_lock_bh(&bp->phy_lock);
5272 bnx2_init_phy(bp); 5276 bnx2_init_phy(bp, 1);
5273 spin_unlock_bh(&bp->phy_lock); 5277 spin_unlock_bh(&bp->phy_lock);
5274 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK)) 5278 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5275 rc |= BNX2_MAC_LOOPBACK_FAILED; 5279 rc |= BNX2_MAC_LOOPBACK_FAILED;
@@ -5659,7 +5663,7 @@ bnx2_open(struct net_device *dev)
5659 return rc; 5663 return rc;
5660 } 5664 }
5661 5665
5662 rc = bnx2_init_nic(bp); 5666 rc = bnx2_init_nic(bp, 1);
5663 5667
5664 if (rc) { 5668 if (rc) {
5665 bnx2_napi_disable(bp); 5669 bnx2_napi_disable(bp);
@@ -5691,7 +5695,7 @@ bnx2_open(struct net_device *dev)
5691 5695
5692 bnx2_setup_int_mode(bp, 1); 5696 bnx2_setup_int_mode(bp, 1);
5693 5697
5694 rc = bnx2_init_nic(bp); 5698 rc = bnx2_init_nic(bp, 0);
5695 5699
5696 if (!rc) 5700 if (!rc)
5697 rc = bnx2_request_irq(bp); 5701 rc = bnx2_request_irq(bp);
@@ -5727,7 +5731,7 @@ bnx2_reset_task(struct work_struct *work)
5727 bp->in_reset_task = 1; 5731 bp->in_reset_task = 1;
5728 bnx2_netif_stop(bp); 5732 bnx2_netif_stop(bp);
5729 5733
5730 bnx2_init_nic(bp); 5734 bnx2_init_nic(bp, 1);
5731 5735
5732 atomic_set(&bp->intr_sem, 1); 5736 atomic_set(&bp->intr_sem, 1);
5733 bnx2_netif_start(bp); 5737 bnx2_netif_start(bp);
@@ -6421,7 +6425,7 @@ bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6421 6425
6422 if (netif_running(bp->dev)) { 6426 if (netif_running(bp->dev)) {
6423 bnx2_netif_stop(bp); 6427 bnx2_netif_stop(bp);
6424 bnx2_init_nic(bp); 6428 bnx2_init_nic(bp, 0);
6425 bnx2_netif_start(bp); 6429 bnx2_netif_start(bp);
6426 } 6430 }
6427 6431
@@ -6464,7 +6468,7 @@ bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6464 rc = bnx2_alloc_mem(bp); 6468 rc = bnx2_alloc_mem(bp);
6465 if (rc) 6469 if (rc)
6466 return rc; 6470 return rc;
6467 bnx2_init_nic(bp); 6471 bnx2_init_nic(bp, 0);
6468 bnx2_netif_start(bp); 6472 bnx2_netif_start(bp);
6469 } 6473 }
6470 return 0; 6474 return 0;
@@ -6732,7 +6736,7 @@ bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6732 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); 6736 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6733 } 6737 }
6734 else { 6738 else {
6735 bnx2_init_nic(bp); 6739 bnx2_init_nic(bp, 1);
6736 bnx2_netif_start(bp); 6740 bnx2_netif_start(bp);
6737 } 6741 }
6738 6742
@@ -7619,7 +7623,7 @@ bnx2_resume(struct pci_dev *pdev)
7619 7623
7620 bnx2_set_power_state(bp, PCI_D0); 7624 bnx2_set_power_state(bp, PCI_D0);
7621 netif_device_attach(dev); 7625 netif_device_attach(dev);
7622 bnx2_init_nic(bp); 7626 bnx2_init_nic(bp, 1);
7623 bnx2_netif_start(bp); 7627 bnx2_netif_start(bp);
7624 return 0; 7628 return 0;
7625} 7629}