Merge tag 'v3.10' into sched/core

Merge in a recent upstream commit:

  c2853c8df57f include/linux/math64.h: add div64_ul()

because:

  72a4cf20cb71 sched: Change cfs_rq load avg to unsigned long

relies on it.

[ We don't rebase sched/core for this, because the handful of
  followup commits after the broken commit are not behavioral
  changes so are unlikely to be needed during bisection. ]

Signed-off-by: Ingo Molnar <mingo@kernel.org>

104 files changed, 5597 insertions, 594 deletions

diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index 29b846cbfb48..f97569613526 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -764,8 +764,8 @@ static void bond_resend_igmp_join_requests(struct bonding *bond)
         struct net_device *bond_dev, *vlan_dev, *upper_dev;
         struct vlan_entry *vlan;
 
-        rcu_read_lock();
         read_lock(&bond->lock);
+        rcu_read_lock();
 
         bond_dev = bond->dev;
 
@@ -787,12 +787,19 @@ static void bond_resend_igmp_join_requests(struct bonding *bond)
                 if (vlan_dev)
                         __bond_resend_igmp_join_requests(vlan_dev);
         }
+        rcu_read_unlock();
 
-        if (--bond->igmp_retrans > 0)
+        /* We use curr_slave_lock to protect against concurrent access to
+         * igmp_retrans from multiple running instances of this function and
+         * bond_change_active_slave
+         */
+        write_lock_bh(&bond->curr_slave_lock);
+        if (bond->igmp_retrans > 1) {
+                bond->igmp_retrans--;
                 queue_delayed_work(bond->wq, &bond->mcast_work, HZ/5);
-
+        }
+        write_unlock_bh(&bond->curr_slave_lock);
         read_unlock(&bond->lock);
-        rcu_read_unlock();
 }
 
 static void bond_resend_igmp_join_requests_delayed(struct work_struct *work)
@@ -1957,6 +1964,10 @@ err_free:
 
 err_undo_flags:
         bond_compute_features(bond);
+        /* Enslave of first slave has failed and we need to fix master's mac */
+        if (bond->slave_cnt == 0 &&
+            ether_addr_equal(bond_dev->dev_addr, slave_dev->dev_addr))
+                eth_hw_addr_random(bond_dev);
 
         return res;
 }
@@ -2402,7 +2413,8 @@ static void bond_miimon_commit(struct bonding *bond)
 
                         pr_info("%s: link status definitely up for interface %s, %u Mbps %s duplex.\n",
                                 bond->dev->name, slave->dev->name,
-                                slave->speed, slave->duplex ? "full" : "half");
+                                slave->speed == SPEED_UNKNOWN ? 0 : slave->speed,
+                                slave->duplex ? "full" : "half");
 
                         /* notify ad that the link status has changed */
                         if (bond->params.mode == BOND_MODE_8023AD)
diff --git a/drivers/net/bonding/bonding.h b/drivers/net/bonding/bonding.h
index 2baec24388b1..f989e1529a29 100644
--- a/drivers/net/bonding/bonding.h
+++ b/drivers/net/bonding/bonding.h
@@ -225,7 +225,7 @@ struct bonding {
         rwlock_t curr_slave_lock;
         u8       send_peer_notif;
         s8       setup_by_slave;
-        s8       igmp_retrans;
+        u8       igmp_retrans;
 #ifdef CONFIG_PROC_FS
         struct   proc_dir_entry *proc_entry;
         char     proc_file_name[IFNAMSIZ];
diff --git a/drivers/net/can/usb/esd_usb2.c b/drivers/net/can/usb/esd_usb2.c
index 9b74d1e3ad44..6aa7b3266c80 100644
--- a/drivers/net/can/usb/esd_usb2.c
+++ b/drivers/net/can/usb/esd_usb2.c
@@ -612,9 +612,15 @@ static int esd_usb2_start(struct esd_usb2_net_priv *priv)
 {
         struct esd_usb2 *dev = priv->usb2;
         struct net_device *netdev = priv->netdev;
-        struct esd_usb2_msg msg;
+        struct esd_usb2_msg *msg;
         int err, i;
 
+        msg = kmalloc(sizeof(*msg), GFP_KERNEL);
+        if (!msg) {
+                err = -ENOMEM;
+                goto out;
+        }
+
         /*
          * Enable all IDs
          * The IDADD message takes up to 64 32 bit bitmasks (2048 bits).
@@ -628,33 +634,32 @@ static int esd_usb2_start(struct esd_usb2_net_priv *priv)
          * the number of the starting bitmask (0..64) to the filter.option
          * field followed by only some bitmasks.
          */
-        msg.msg.hdr.cmd = CMD_IDADD;
-        msg.msg.hdr.len = 2 + ESD_MAX_ID_SEGMENT;
-        msg.msg.filter.net = priv->index;
-        msg.msg.filter.option = ESD_ID_ENABLE; /* start with segment 0 */
+        msg->msg.hdr.cmd = CMD_IDADD;
+        msg->msg.hdr.len = 2 + ESD_MAX_ID_SEGMENT;
+        msg->msg.filter.net = priv->index;
+        msg->msg.filter.option = ESD_ID_ENABLE; /* start with segment 0 */
         for (i = 0; i < ESD_MAX_ID_SEGMENT; i++)
-                msg.msg.filter.mask[i] = cpu_to_le32(0xffffffff);
+                msg->msg.filter.mask[i] = cpu_to_le32(0xffffffff);
         /* enable 29bit extended IDs */
-        msg.msg.filter.mask[ESD_MAX_ID_SEGMENT] = cpu_to_le32(0x00000001);
+        msg->msg.filter.mask[ESD_MAX_ID_SEGMENT] = cpu_to_le32(0x00000001);
 
-        err = esd_usb2_send_msg(dev, &msg);
+        err = esd_usb2_send_msg(dev, msg);
         if (err)
-                goto failed;
+                goto out;
 
         err = esd_usb2_setup_rx_urbs(dev);
         if (err)
-                goto failed;
+                goto out;
 
         priv->can.state = CAN_STATE_ERROR_ACTIVE;
 
-        return 0;
-
-failed:
+out:
         if (err == -ENODEV)
                 netif_device_detach(netdev);
+        if (err)
+                netdev_err(netdev, "couldn't start device: %d\n", err);
 
-        netdev_err(netdev, "couldn't start device: %d\n", err);
-
+        kfree(msg);
         return err;
 }
 
@@ -833,26 +838,30 @@ nourbmem:
 static int esd_usb2_close(struct net_device *netdev)
 {
         struct esd_usb2_net_priv *priv = netdev_priv(netdev);
-        struct esd_usb2_msg msg;
+        struct esd_usb2_msg *msg;
         int i;
 
+        msg = kmalloc(sizeof(*msg), GFP_KERNEL);
+        if (!msg)
+                return -ENOMEM;
+
         /* Disable all IDs (see esd_usb2_start()) */
-        msg.msg.hdr.cmd = CMD_IDADD;
-        msg.msg.hdr.len = 2 + ESD_MAX_ID_SEGMENT;
-        msg.msg.filter.net = priv->index;
-        msg.msg.filter.option = ESD_ID_ENABLE; /* start with segment 0 */
+        msg->msg.hdr.cmd = CMD_IDADD;
+        msg->msg.hdr.len = 2 + ESD_MAX_ID_SEGMENT;
+        msg->msg.filter.net = priv->index;
+        msg->msg.filter.option = ESD_ID_ENABLE; /* start with segment 0 */
         for (i = 0; i <= ESD_MAX_ID_SEGMENT; i++)
-                msg.msg.filter.mask[i] = 0;
-        if (esd_usb2_send_msg(priv->usb2, &msg) < 0)
+                msg->msg.filter.mask[i] = 0;
+        if (esd_usb2_send_msg(priv->usb2, msg) < 0)
                 netdev_err(netdev, "sending idadd message failed\n");
 
         /* set CAN controller to reset mode */
-        msg.msg.hdr.len = 2;
-        msg.msg.hdr.cmd = CMD_SETBAUD;
-        msg.msg.setbaud.net = priv->index;
-        msg.msg.setbaud.rsvd = 0;
-        msg.msg.setbaud.baud = cpu_to_le32(ESD_USB2_NO_BAUDRATE);
-        if (esd_usb2_send_msg(priv->usb2, &msg) < 0)
+        msg->msg.hdr.len = 2;
+        msg->msg.hdr.cmd = CMD_SETBAUD;
+        msg->msg.setbaud.net = priv->index;
+        msg->msg.setbaud.rsvd = 0;
+        msg->msg.setbaud.baud = cpu_to_le32(ESD_USB2_NO_BAUDRATE);
+        if (esd_usb2_send_msg(priv->usb2, msg) < 0)
                 netdev_err(netdev, "sending setbaud message failed\n");
 
         priv->can.state = CAN_STATE_STOPPED;
@@ -861,6 +870,8 @@ static int esd_usb2_close(struct net_device *netdev)
 
         close_candev(netdev);
 
+        kfree(msg);
+
         return 0;
 }
 
@@ -886,7 +897,8 @@ static int esd_usb2_set_bittiming(struct net_device *netdev)
 {
         struct esd_usb2_net_priv *priv = netdev_priv(netdev);
         struct can_bittiming *bt = &priv->can.bittiming;
-        struct esd_usb2_msg msg;
+        struct esd_usb2_msg *msg;
+        int err;
         u32 canbtr;
         int sjw_shift;
 
@@ -912,15 +924,22 @@ static int esd_usb2_set_bittiming(struct net_device *netdev)
         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
                 canbtr |= ESD_USB2_3_SAMPLES;
 
-        msg.msg.hdr.len = 2;
-        msg.msg.hdr.cmd = CMD_SETBAUD;
-        msg.msg.setbaud.net = priv->index;
-        msg.msg.setbaud.rsvd = 0;
-        msg.msg.setbaud.baud = cpu_to_le32(canbtr);
+        msg = kmalloc(sizeof(*msg), GFP_KERNEL);
+        if (!msg)
+                return -ENOMEM;
+
+        msg->msg.hdr.len = 2;
+        msg->msg.hdr.cmd = CMD_SETBAUD;
+        msg->msg.setbaud.net = priv->index;
+        msg->msg.setbaud.rsvd = 0;
+        msg->msg.setbaud.baud = cpu_to_le32(canbtr);
 
         netdev_info(netdev, "setting BTR=%#x\n", canbtr);
 
-        return esd_usb2_send_msg(priv->usb2, &msg);
+        err = esd_usb2_send_msg(priv->usb2, msg);
+
+        kfree(msg);
+        return err;
 }
 
 static int esd_usb2_get_berr_counter(const struct net_device *netdev,
@@ -1022,7 +1041,7 @@ static int esd_usb2_probe(struct usb_interface *intf,
                          const struct usb_device_id *id)
 {
         struct esd_usb2 *dev;
-        struct esd_usb2_msg msg;
+        struct esd_usb2_msg *msg;
         int i, err;
 
         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
@@ -1037,27 +1056,33 @@ static int esd_usb2_probe(struct usb_interface *intf,
 
         usb_set_intfdata(intf, dev);
 
+        msg = kmalloc(sizeof(*msg), GFP_KERNEL);
+        if (!msg) {
+                err = -ENOMEM;
+                goto free_msg;
+        }
+
         /* query number of CAN interfaces (nets) */
-        msg.msg.hdr.cmd = CMD_VERSION;
-        msg.msg.hdr.len = 2;
-        msg.msg.version.rsvd = 0;
-        msg.msg.version.flags = 0;
-        msg.msg.version.drv_version = 0;
+        msg->msg.hdr.cmd = CMD_VERSION;
+        msg->msg.hdr.len = 2;
+        msg->msg.version.rsvd = 0;
+        msg->msg.version.flags = 0;
+        msg->msg.version.drv_version = 0;
 
-        err = esd_usb2_send_msg(dev, &msg);
+        err = esd_usb2_send_msg(dev, msg);
         if (err < 0) {
                 dev_err(&intf->dev, "sending version message failed\n");
-                goto free_dev;
+                goto free_msg;
         }
 
-        err = esd_usb2_wait_msg(dev, &msg);
+        err = esd_usb2_wait_msg(dev, msg);
         if (err < 0) {
                 dev_err(&intf->dev, "no version message answer\n");
-                goto free_dev;
+                goto free_msg;
         }
 
-        dev->net_count = (int)msg.msg.version_reply.nets;
-        dev->version = le32_to_cpu(msg.msg.version_reply.version);
+        dev->net_count = (int)msg->msg.version_reply.nets;
+        dev->version = le32_to_cpu(msg->msg.version_reply.version);
 
         if (device_create_file(&intf->dev, &dev_attr_firmware))
                 dev_err(&intf->dev,
@@ -1075,10 +1100,10 @@ static int esd_usb2_probe(struct usb_interface *intf,
         for (i = 0; i < dev->net_count; i++)
                 esd_usb2_probe_one_net(intf, i);
 
-        return 0;
-
-free_dev:
-        kfree(dev);
+free_msg:
+        kfree(msg);
+        if (err)
+                kfree(dev);
 done:
         return err;
 }
diff --git a/drivers/net/can/usb/kvaser_usb.c b/drivers/net/can/usb/kvaser_usb.c
index 45cb9f3c1324..3b9546588240 100644
--- a/drivers/net/can/usb/kvaser_usb.c
+++ b/drivers/net/can/usb/kvaser_usb.c
@@ -136,6 +136,9 @@
 #define KVASER_CTRL_MODE_SELFRECEPTION  3
 #define KVASER_CTRL_MODE_OFF            4
 
+/* log message */
+#define KVASER_EXTENDED_FRAME           BIT(31)
+
 struct kvaser_msg_simple {
         u8 tid;
         u8 channel;
@@ -817,8 +820,13 @@ static void kvaser_usb_rx_can_msg(const struct kvaser_usb *dev,
         priv = dev->nets[channel];
         stats = &priv->netdev->stats;
 
-        if (msg->u.rx_can.flag & (MSG_FLAG_ERROR_FRAME | MSG_FLAG_NERR |
-                                  MSG_FLAG_OVERRUN)) {
+        if ((msg->u.rx_can.flag & MSG_FLAG_ERROR_FRAME) &&
+            (msg->id == CMD_LOG_MESSAGE)) {
+                kvaser_usb_rx_error(dev, msg);
+                return;
+        } else if (msg->u.rx_can.flag & (MSG_FLAG_ERROR_FRAME |
+                                         MSG_FLAG_NERR |
+                                         MSG_FLAG_OVERRUN)) {
                 kvaser_usb_rx_can_err(priv, msg);
                 return;
         } else if (msg->u.rx_can.flag & ~MSG_FLAG_REMOTE_FRAME) {
@@ -834,22 +842,40 @@ static void kvaser_usb_rx_can_msg(const struct kvaser_usb *dev,
                 return;
         }
 
-        cf->can_id = ((msg->u.rx_can.msg[0] & 0x1f) << 6) |
-                     (msg->u.rx_can.msg[1] & 0x3f);
-        cf->can_dlc = get_can_dlc(msg->u.rx_can.msg[5]);
+        if (msg->id == CMD_LOG_MESSAGE) {
+                cf->can_id = le32_to_cpu(msg->u.log_message.id);
+                if (cf->can_id & KVASER_EXTENDED_FRAME)
+                        cf->can_id &= CAN_EFF_MASK | CAN_EFF_FLAG;
+                else
+                        cf->can_id &= CAN_SFF_MASK;
 
-        if (msg->id == CMD_RX_EXT_MESSAGE) {
-                cf->can_id <<= 18;
-                cf->can_id |= ((msg->u.rx_can.msg[2] & 0x0f) << 14) |
-                              ((msg->u.rx_can.msg[3] & 0xff) << 6) |
-                              (msg->u.rx_can.msg[4] & 0x3f);
-                cf->can_id |= CAN_EFF_FLAG;
-        }
+                cf->can_dlc = get_can_dlc(msg->u.log_message.dlc);
 
-        if (msg->u.rx_can.flag & MSG_FLAG_REMOTE_FRAME)
-                cf->can_id |= CAN_RTR_FLAG;
-        else
-                memcpy(cf->data, &msg->u.rx_can.msg[6], cf->can_dlc);
+                if (msg->u.log_message.flags & MSG_FLAG_REMOTE_FRAME)
+                        cf->can_id |= CAN_RTR_FLAG;
+                else
+                        memcpy(cf->data, &msg->u.log_message.data,
+                               cf->can_dlc);
+        } else {
+                cf->can_id = ((msg->u.rx_can.msg[0] & 0x1f) << 6) |
+                             (msg->u.rx_can.msg[1] & 0x3f);
+
+                if (msg->id == CMD_RX_EXT_MESSAGE) {
+                        cf->can_id <<= 18;
+                        cf->can_id |= ((msg->u.rx_can.msg[2] & 0x0f) << 14) |
+                                      ((msg->u.rx_can.msg[3] & 0xff) << 6) |
+                                      (msg->u.rx_can.msg[4] & 0x3f);
+                        cf->can_id |= CAN_EFF_FLAG;
+                }
+
+                cf->can_dlc = get_can_dlc(msg->u.rx_can.msg[5]);
+
+                if (msg->u.rx_can.flag & MSG_FLAG_REMOTE_FRAME)
+                        cf->can_id |= CAN_RTR_FLAG;
+                else
+                        memcpy(cf->data, &msg->u.rx_can.msg[6],
+                               cf->can_dlc);
+        }
 
         netif_rx(skb);
 
@@ -911,6 +937,7 @@ static void kvaser_usb_handle_message(const struct kvaser_usb *dev,
 
         case CMD_RX_STD_MESSAGE:
         case CMD_RX_EXT_MESSAGE:
+        case CMD_LOG_MESSAGE:
                 kvaser_usb_rx_can_msg(dev, msg);
                 break;
 
@@ -919,11 +946,6 @@ static void kvaser_usb_handle_message(const struct kvaser_usb *dev,
                 kvaser_usb_rx_error(dev, msg);
                 break;
 
-        case CMD_LOG_MESSAGE:
-                if (msg->u.log_message.flags & MSG_FLAG_ERROR_FRAME)
-                        kvaser_usb_rx_error(dev, msg);
-                break;
-
         case CMD_TX_ACKNOWLEDGE:
                 kvaser_usb_tx_acknowledge(dev, msg);
                 break;
diff --git a/drivers/net/can/usb/peak_usb/pcan_usb_pro.c b/drivers/net/can/usb/peak_usb/pcan_usb_pro.c
index 30d79bfa5b10..8ee9d1556e6e 100644
--- a/drivers/net/can/usb/peak_usb/pcan_usb_pro.c
+++ b/drivers/net/can/usb/peak_usb/pcan_usb_pro.c
@@ -504,15 +504,24 @@ static int pcan_usb_pro_restart_async(struct peak_usb_device *dev,
         return usb_submit_urb(urb, GFP_ATOMIC);
 }
 
-static void pcan_usb_pro_drv_loaded(struct peak_usb_device *dev, int loaded)
+static int pcan_usb_pro_drv_loaded(struct peak_usb_device *dev, int loaded)
 {
-        u8 buffer[16];
+        u8 *buffer;
+        int err;
+
+        buffer = kmalloc(PCAN_USBPRO_FCT_DRVLD_REQ_LEN, GFP_KERNEL);
+        if (!buffer)
+                return -ENOMEM;
 
         buffer[0] = 0;
         buffer[1] = !!loaded;
 
-        pcan_usb_pro_send_req(dev, PCAN_USBPRO_REQ_FCT,
-                              PCAN_USBPRO_FCT_DRVLD, buffer, sizeof(buffer));
+        err = pcan_usb_pro_send_req(dev, PCAN_USBPRO_REQ_FCT,
+                                    PCAN_USBPRO_FCT_DRVLD, buffer,
+                                    PCAN_USBPRO_FCT_DRVLD_REQ_LEN);
+        kfree(buffer);
+
+        return err;
 }
 
 static inline
@@ -851,21 +860,24 @@ static int pcan_usb_pro_stop(struct peak_usb_device *dev)
  */
 static int pcan_usb_pro_init(struct peak_usb_device *dev)
 {
-        struct pcan_usb_pro_interface *usb_if;
         struct pcan_usb_pro_device *pdev =
                         container_of(dev, struct pcan_usb_pro_device, dev);
+        struct pcan_usb_pro_interface *usb_if = NULL;
+        struct pcan_usb_pro_fwinfo *fi = NULL;
+        struct pcan_usb_pro_blinfo *bi = NULL;
+        int err;
 
         /* do this for 1st channel only */
         if (!dev->prev_siblings) {
-                struct pcan_usb_pro_fwinfo fi;
-                struct pcan_usb_pro_blinfo bi;
-                int err;
-
                 /* allocate netdevices common structure attached to first one */
                 usb_if = kzalloc(sizeof(struct pcan_usb_pro_interface),
                                  GFP_KERNEL);
-                if (!usb_if)
-                        return -ENOMEM;
+                fi = kmalloc(sizeof(struct pcan_usb_pro_fwinfo), GFP_KERNEL);
+                bi = kmalloc(sizeof(struct pcan_usb_pro_blinfo), GFP_KERNEL);
+                if (!usb_if || !fi || !bi) {
+                        err = -ENOMEM;
+                        goto err_out;
+                }
 
                 /* number of ts msgs to ignore before taking one into account */
                 usb_if->cm_ignore_count = 5;
@@ -877,34 +889,34 @@ static int pcan_usb_pro_init(struct peak_usb_device *dev)
                  */
                 err = pcan_usb_pro_send_req(dev, PCAN_USBPRO_REQ_INFO,
                                             PCAN_USBPRO_INFO_FW,
-                                            &fi, sizeof(fi));
+                                            fi, sizeof(*fi));
                 if (err) {
-                        kfree(usb_if);
                         dev_err(dev->netdev->dev.parent,
                                 "unable to read %s firmware info (err %d)\n",
                                 pcan_usb_pro.name, err);
-                        return err;
+                        goto err_out;
                 }
 
                 err = pcan_usb_pro_send_req(dev, PCAN_USBPRO_REQ_INFO,
                                             PCAN_USBPRO_INFO_BL,
-                                            &bi, sizeof(bi));
+                                            bi, sizeof(*bi));
                 if (err) {
-                        kfree(usb_if);
                         dev_err(dev->netdev->dev.parent,
                                 "unable to read %s bootloader info (err %d)\n",
                                 pcan_usb_pro.name, err);
-                        return err;
+                        goto err_out;
                 }
 
+                /* tell the device the can driver is running */
+                err = pcan_usb_pro_drv_loaded(dev, 1);
+                if (err)
+                        goto err_out;
+
                 dev_info(dev->netdev->dev.parent,
                      "PEAK-System %s hwrev %u serial %08X.%08X (%u channels)\n",
                      pcan_usb_pro.name,
-                     bi.hw_rev, bi.serial_num_hi, bi.serial_num_lo,
+                     bi->hw_rev, bi->serial_num_hi, bi->serial_num_lo,
                      pcan_usb_pro.ctrl_count);
-
-                /* tell the device the can driver is running */
-                pcan_usb_pro_drv_loaded(dev, 1);
         } else {
                 usb_if = pcan_usb_pro_dev_if(dev->prev_siblings);
         }
@@ -916,6 +928,13 @@ static int pcan_usb_pro_init(struct peak_usb_device *dev)
         pcan_usb_pro_set_led(dev, 0, 1);
 
         return 0;
+
+ err_out:
+        kfree(bi);
+        kfree(fi);
+        kfree(usb_if);
+
+        return err;
 }
 
 static void pcan_usb_pro_exit(struct peak_usb_device *dev)
diff --git a/drivers/net/can/usb/peak_usb/pcan_usb_pro.h b/drivers/net/can/usb/peak_usb/pcan_usb_pro.h
index a869918c5620..32275af547e0 100644
--- a/drivers/net/can/usb/peak_usb/pcan_usb_pro.h
+++ b/drivers/net/can/usb/peak_usb/pcan_usb_pro.h
@@ -29,6 +29,7 @@
 
 /* Vendor Request value for XXX_FCT */
 #define PCAN_USBPRO_FCT_DRVLD           5 /* tell device driver is loaded */
+#define PCAN_USBPRO_FCT_DRVLD_REQ_LEN   16
 
 /* PCAN_USBPRO_INFO_BL vendor request record type */
 struct __packed pcan_usb_pro_blinfo {
diff --git a/drivers/net/can/usb/usb_8dev.c b/drivers/net/can/usb/usb_8dev.c
index 6e15ef08f301..cbd388eea682 100644
--- a/drivers/net/can/usb/usb_8dev.c
+++ b/drivers/net/can/usb/usb_8dev.c
@@ -977,7 +977,7 @@ static int usb_8dev_probe(struct usb_interface *intf,
         err = usb_8dev_cmd_version(priv, &version);
         if (err) {
                 netdev_err(netdev, "can't get firmware version\n");
-                goto cleanup_cmd_msg_buffer;
+                goto cleanup_unregister_candev;
         } else {
                 netdev_info(netdev,
                          "firmware: %d.%d, hardware: %d.%d\n",
@@ -989,6 +989,9 @@ static int usb_8dev_probe(struct usb_interface *intf,
 
         return 0;
 
+cleanup_unregister_candev:
+        unregister_netdev(priv->netdev);
+
 cleanup_cmd_msg_buffer:
         kfree(priv->cmd_msg_buffer);
 
diff --git a/drivers/net/ethernet/atheros/Kconfig b/drivers/net/ethernet/atheros/Kconfig
index 36d6abd1cfff..ad6aa1e98348 100644
--- a/drivers/net/ethernet/atheros/Kconfig
+++ b/drivers/net/ethernet/atheros/Kconfig
@@ -67,4 +67,22 @@ config ATL1C
           To compile this driver as a module, choose M here.  The module
           will be called atl1c.
 
+config ALX
+        tristate "Qualcomm Atheros AR816x/AR817x support"
+        depends on PCI
+        select CRC32
+        select NET_CORE
+        select MDIO
+        help
+          This driver supports the Qualcomm Atheros L1F ethernet adapter,
+          i.e. the following chipsets:
+
+          1969:1091 - AR8161 Gigabit Ethernet
+          1969:1090 - AR8162 Fast Ethernet
+          1969:10A1 - AR8171 Gigabit Ethernet
+          1969:10A0 - AR8172 Fast Ethernet
+
+          To compile this driver as a module, choose M here.  The module
+          will be called alx.
+
 endif # NET_VENDOR_ATHEROS
diff --git a/drivers/net/ethernet/atheros/Makefile b/drivers/net/ethernet/atheros/Makefile
index e7e76fb576ff..5cf1c65bbce9 100644
--- a/drivers/net/ethernet/atheros/Makefile
+++ b/drivers/net/ethernet/atheros/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_ATL1) += atlx/
 obj-$(CONFIG_ATL2) += atlx/
 obj-$(CONFIG_ATL1E) += atl1e/
 obj-$(CONFIG_ATL1C) += atl1c/
+obj-$(CONFIG_ALX) += alx/
diff --git a/drivers/net/ethernet/atheros/alx/Makefile b/drivers/net/ethernet/atheros/alx/Makefile
new file mode 100644
index 000000000000..5901fa407d52
--- /dev/null
+++ b/drivers/net/ethernet/atheros/alx/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_ALX) += alx.o
+alx-objs := main.o ethtool.o hw.o
+ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/ethernet/atheros/alx/alx.h b/drivers/net/ethernet/atheros/alx/alx.h
new file mode 100644
index 000000000000..50b3ae2b143d
--- /dev/null
+++ b/drivers/net/ethernet/atheros/alx/alx.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
+ *
+ *  This file is free software: you may copy, redistribute and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation, either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  This file is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _ALX_H_
+#define _ALX_H_
+
+#include <linux/types.h>
+#include <linux/etherdevice.h>
+#include <linux/dma-mapping.h>
+#include <linux/spinlock.h>
+#include "hw.h"
+
+#define ALX_WATCHDOG_TIME   (5 * HZ)
+
+struct alx_buffer {
+        struct sk_buff *skb;
+        DEFINE_DMA_UNMAP_ADDR(dma);
+        DEFINE_DMA_UNMAP_LEN(size);
+};
+
+struct alx_rx_queue {
+        struct alx_rrd *rrd;
+        dma_addr_t rrd_dma;
+
+        struct alx_rfd *rfd;
+        dma_addr_t rfd_dma;
+
+        struct alx_buffer *bufs;
+
+        u16 write_idx, read_idx;
+        u16 rrd_read_idx;
+};
+#define ALX_RX_ALLOC_THRESH     32
+
+struct alx_tx_queue {
+        struct alx_txd *tpd;
+        dma_addr_t tpd_dma;
+        struct alx_buffer *bufs;
+        u16 write_idx, read_idx;
+};
+
+#define ALX_DEFAULT_TX_WORK 128
+
+enum alx_device_quirks {
+        ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG = BIT(0),
+};
+
+struct alx_priv {
+        struct net_device *dev;
+
+        struct alx_hw hw;
+
+        /* all descriptor memory */
+        struct {
+                dma_addr_t dma;
+                void *virt;
+                int size;
+        } descmem;
+
+        /* protect int_mask updates */
+        spinlock_t irq_lock;
+        u32 int_mask;
+
+        int tx_ringsz;
+        int rx_ringsz;
+        int rxbuf_size;
+
+        struct napi_struct napi;
+        struct alx_tx_queue txq;
+        struct alx_rx_queue rxq;
+
+        struct work_struct link_check_wk;
+        struct work_struct reset_wk;
+
+        u16 msg_enable;
+
+        bool msi;
+};
+
+extern const struct ethtool_ops alx_ethtool_ops;
+extern const char alx_drv_name[];
+
+#endif
diff --git a/drivers/net/ethernet/atheros/alx/ethtool.c b/drivers/net/ethernet/atheros/alx/ethtool.c
new file mode 100644
index 000000000000..6fa2aec2bc81
--- /dev/null
+++ b/drivers/net/ethernet/atheros/alx/ethtool.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
+ *
+ *  This file is free software: you may copy, redistribute and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation, either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  This file is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/pci.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/mdio.h>
+#include <linux/interrupt.h>
+#include <asm/byteorder.h>
+
+#include "alx.h"
+#include "reg.h"
+#include "hw.h"
+
+
+static int alx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+        struct alx_hw *hw = &alx->hw;
+
+        ecmd->supported = SUPPORTED_10baseT_Half |
+                          SUPPORTED_10baseT_Full |
+                          SUPPORTED_100baseT_Half |
+                          SUPPORTED_100baseT_Full |
+                          SUPPORTED_Autoneg |
+                          SUPPORTED_TP |
+                          SUPPORTED_Pause;
+        if (alx_hw_giga(hw))
+                ecmd->supported |= SUPPORTED_1000baseT_Full;
+
+        ecmd->advertising = ADVERTISED_TP;
+        if (hw->adv_cfg & ADVERTISED_Autoneg)
+                ecmd->advertising |= hw->adv_cfg;
+
+        ecmd->port = PORT_TP;
+        ecmd->phy_address = 0;
+        if (hw->adv_cfg & ADVERTISED_Autoneg)
+                ecmd->autoneg = AUTONEG_ENABLE;
+        else
+                ecmd->autoneg = AUTONEG_DISABLE;
+        ecmd->transceiver = XCVR_INTERNAL;
+
+        if (hw->flowctrl & ALX_FC_ANEG && hw->adv_cfg & ADVERTISED_Autoneg) {
+                if (hw->flowctrl & ALX_FC_RX) {
+                        ecmd->advertising |= ADVERTISED_Pause;
+
+                        if (!(hw->flowctrl & ALX_FC_TX))
+                                ecmd->advertising |= ADVERTISED_Asym_Pause;
+                } else if (hw->flowctrl & ALX_FC_TX) {
+                        ecmd->advertising |= ADVERTISED_Asym_Pause;
+                }
+        }
+
+        if (hw->link_speed != SPEED_UNKNOWN) {
+                ethtool_cmd_speed_set(ecmd,
+                                      hw->link_speed - hw->link_speed % 10);
+                ecmd->duplex = hw->link_speed % 10;
+        } else {
+                ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
+                ecmd->duplex = DUPLEX_UNKNOWN;
+        }
+
+        return 0;
+}
+
+static int alx_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+        struct alx_hw *hw = &alx->hw;
+        u32 adv_cfg;
+
+        ASSERT_RTNL();
+
+        if (ecmd->autoneg == AUTONEG_ENABLE) {
+                if (ecmd->advertising & ADVERTISED_1000baseT_Half)
+                        return -EINVAL;
+                adv_cfg = ecmd->advertising | ADVERTISED_Autoneg;
+        } else {
+                int speed = ethtool_cmd_speed(ecmd);
+
+                switch (speed + ecmd->duplex) {
+                case SPEED_10 + DUPLEX_HALF:
+                        adv_cfg = ADVERTISED_10baseT_Half;
+                        break;
+                case SPEED_10 + DUPLEX_FULL:
+                        adv_cfg = ADVERTISED_10baseT_Full;
+                        break;
+                case SPEED_100 + DUPLEX_HALF:
+                        adv_cfg = ADVERTISED_100baseT_Half;
+                        break;
+                case SPEED_100 + DUPLEX_FULL:
+                        adv_cfg = ADVERTISED_100baseT_Full;
+                        break;
+                default:
+                        return -EINVAL;
+                }
+        }
+
+        hw->adv_cfg = adv_cfg;
+        return alx_setup_speed_duplex(hw, adv_cfg, hw->flowctrl);
+}
+
+static void alx_get_pauseparam(struct net_device *netdev,
+                               struct ethtool_pauseparam *pause)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+        struct alx_hw *hw = &alx->hw;
+
+        if (hw->flowctrl & ALX_FC_ANEG &&
+            hw->adv_cfg & ADVERTISED_Autoneg)
+                pause->autoneg = AUTONEG_ENABLE;
+        else
+                pause->autoneg = AUTONEG_DISABLE;
+
+        if (hw->flowctrl & ALX_FC_TX)
+                pause->tx_pause = 1;
+        else
+                pause->tx_pause = 0;
+
+        if (hw->flowctrl & ALX_FC_RX)
+                pause->rx_pause = 1;
+        else
+                pause->rx_pause = 0;
+}
+
+
+static int alx_set_pauseparam(struct net_device *netdev,
+                              struct ethtool_pauseparam *pause)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+        struct alx_hw *hw = &alx->hw;
+        int err = 0;
+        bool reconfig_phy = false;
+        u8 fc = 0;
+
+        if (pause->tx_pause)
+                fc |= ALX_FC_TX;
+        if (pause->rx_pause)
+                fc |= ALX_FC_RX;
+        if (pause->autoneg)
+                fc |= ALX_FC_ANEG;
+
+        ASSERT_RTNL();
+
+        /* restart auto-neg for auto-mode */
+        if (hw->adv_cfg & ADVERTISED_Autoneg) {
+                if (!((fc ^ hw->flowctrl) & ALX_FC_ANEG))
+                        reconfig_phy = true;
+                if (fc & hw->flowctrl & ALX_FC_ANEG &&
+                    (fc ^ hw->flowctrl) & (ALX_FC_RX | ALX_FC_TX))
+                        reconfig_phy = true;
+        }
+
+        if (reconfig_phy) {
+                err = alx_setup_speed_duplex(hw, hw->adv_cfg, fc);
+                return err;
+        }
+
+        /* flow control on mac */
+        if ((fc ^ hw->flowctrl) & (ALX_FC_RX | ALX_FC_TX))
+                alx_cfg_mac_flowcontrol(hw, fc);
+
+        hw->flowctrl = fc;
+
+        return 0;
+}
+
+static u32 alx_get_msglevel(struct net_device *netdev)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+
+        return alx->msg_enable;
+}
+
+static void alx_set_msglevel(struct net_device *netdev, u32 data)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+
+        alx->msg_enable = data;
+}
+
+static void alx_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+        struct alx_hw *hw = &alx->hw;
+
+        wol->supported = WAKE_MAGIC | WAKE_PHY;
+        wol->wolopts = 0;
+
+        if (hw->sleep_ctrl & ALX_SLEEP_WOL_MAGIC)
+                wol->wolopts |= WAKE_MAGIC;
+        if (hw->sleep_ctrl & ALX_SLEEP_WOL_PHY)
+                wol->wolopts |= WAKE_PHY;
+}
+
+static int alx_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+        struct alx_hw *hw = &alx->hw;
+
+        if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE |
+                            WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
+                return -EOPNOTSUPP;
+
+        hw->sleep_ctrl = 0;
+
+        if (wol->wolopts & WAKE_MAGIC)
+                hw->sleep_ctrl |= ALX_SLEEP_WOL_MAGIC;
+        if (wol->wolopts & WAKE_PHY)
+                hw->sleep_ctrl |= ALX_SLEEP_WOL_PHY;
+
+        device_set_wakeup_enable(&alx->hw.pdev->dev, hw->sleep_ctrl);
+
+        return 0;
+}
+
+static void alx_get_drvinfo(struct net_device *netdev,
+                            struct ethtool_drvinfo *drvinfo)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+
+        strlcpy(drvinfo->driver, alx_drv_name, sizeof(drvinfo->driver));
+        strlcpy(drvinfo->bus_info, pci_name(alx->hw.pdev),
+                sizeof(drvinfo->bus_info));
+}
+
+const struct ethtool_ops alx_ethtool_ops = {
+        .get_settings   = alx_get_settings,
+        .set_settings   = alx_set_settings,
+        .get_pauseparam = alx_get_pauseparam,
+        .set_pauseparam = alx_set_pauseparam,
+        .get_drvinfo    = alx_get_drvinfo,
+        .get_msglevel   = alx_get_msglevel,
+        .set_msglevel   = alx_set_msglevel,
+        .get_wol        = alx_get_wol,
+        .set_wol        = alx_set_wol,
+        .get_link       = ethtool_op_get_link,
+};
diff --git a/drivers/net/ethernet/atheros/alx/hw.c b/drivers/net/ethernet/atheros/alx/hw.c
new file mode 100644
index 000000000000..220a16ad0e49
--- /dev/null
+++ b/drivers/net/ethernet/atheros/alx/hw.c
@@ -0,0 +1,1226 @@
+/*
+ * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
+ *
+ *  This file is free software: you may copy, redistribute and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation, either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  This file is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/mdio.h>
+#include "reg.h"
+#include "hw.h"
+
+static inline bool alx_is_rev_a(u8 rev)
+{
+        return rev == ALX_REV_A0 || rev == ALX_REV_A1;
+}
+
+static int alx_wait_mdio_idle(struct alx_hw *hw)
+{
+        u32 val;
+        int i;
+
+        for (i = 0; i < ALX_MDIO_MAX_AC_TO; i++) {
+                val = alx_read_mem32(hw, ALX_MDIO);
+                if (!(val & ALX_MDIO_BUSY))
+                        return 0;
+                udelay(10);
+        }
+
+        return -ETIMEDOUT;
+}
+
+static int alx_read_phy_core(struct alx_hw *hw, bool ext, u8 dev,
+                             u16 reg, u16 *phy_data)
+{
+        u32 val, clk_sel;
+        int err;
+
+        *phy_data = 0;
+
+        /* use slow clock when it's in hibernation status */
+        clk_sel = hw->link_speed != SPEED_UNKNOWN ?
+                        ALX_MDIO_CLK_SEL_25MD4 :
+                        ALX_MDIO_CLK_SEL_25MD128;
+
+        if (ext) {
+                val = dev << ALX_MDIO_EXTN_DEVAD_SHIFT |
+                      reg << ALX_MDIO_EXTN_REG_SHIFT;
+                alx_write_mem32(hw, ALX_MDIO_EXTN, val);
+
+                val = ALX_MDIO_SPRES_PRMBL | ALX_MDIO_START |
+                      ALX_MDIO_MODE_EXT | ALX_MDIO_OP_READ |
+                      clk_sel << ALX_MDIO_CLK_SEL_SHIFT;
+        } else {
+                val = ALX_MDIO_SPRES_PRMBL |
+                      clk_sel << ALX_MDIO_CLK_SEL_SHIFT |
+                      reg << ALX_MDIO_REG_SHIFT |
+                      ALX_MDIO_START | ALX_MDIO_OP_READ;
+        }
+        alx_write_mem32(hw, ALX_MDIO, val);
+
+        err = alx_wait_mdio_idle(hw);
+        if (err)
+                return err;
+        val = alx_read_mem32(hw, ALX_MDIO);
+        *phy_data = ALX_GET_FIELD(val, ALX_MDIO_DATA);
+        return 0;
+}
+
+static int alx_write_phy_core(struct alx_hw *hw, bool ext, u8 dev,
+                              u16 reg, u16 phy_data)
+{
+        u32 val, clk_sel;
+
+        /* use slow clock when it's in hibernation status */
+        clk_sel = hw->link_speed != SPEED_UNKNOWN ?
+                        ALX_MDIO_CLK_SEL_25MD4 :
+                        ALX_MDIO_CLK_SEL_25MD128;
+
+        if (ext) {
+                val = dev << ALX_MDIO_EXTN_DEVAD_SHIFT |
+                      reg << ALX_MDIO_EXTN_REG_SHIFT;
+                alx_write_mem32(hw, ALX_MDIO_EXTN, val);
+
+                val = ALX_MDIO_SPRES_PRMBL |
+                      clk_sel << ALX_MDIO_CLK_SEL_SHIFT |
+                      phy_data << ALX_MDIO_DATA_SHIFT |
+                      ALX_MDIO_START | ALX_MDIO_MODE_EXT;
+        } else {
+                val = ALX_MDIO_SPRES_PRMBL |
+                      clk_sel << ALX_MDIO_CLK_SEL_SHIFT |
+                      reg << ALX_MDIO_REG_SHIFT |
+                      phy_data << ALX_MDIO_DATA_SHIFT |
+                      ALX_MDIO_START;
+        }
+        alx_write_mem32(hw, ALX_MDIO, val);
+
+        return alx_wait_mdio_idle(hw);
+}
+
+static int __alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data)
+{
+        return alx_read_phy_core(hw, false, 0, reg, phy_data);
+}
+
+static int __alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data)
+{
+        return alx_write_phy_core(hw, false, 0, reg, phy_data);
+}
+
+static int __alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata)
+{
+        return alx_read_phy_core(hw, true, dev, reg, pdata);
+}
+
+static int __alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data)
+{
+        return alx_write_phy_core(hw, true, dev, reg, data);
+}
+
+static int __alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata)
+{
+        int err;
+
+        err = __alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, reg);
+        if (err)
+                return err;
+
+        return __alx_read_phy_reg(hw, ALX_MII_DBG_DATA, pdata);
+}
+
+static int __alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data)
+{
+        int err;
+
+        err = __alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, reg);
+        if (err)
+                return err;
+
+        return __alx_write_phy_reg(hw, ALX_MII_DBG_DATA, data);
+}
+
+int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data)
+{
+        int err;
+
+        spin_lock(&hw->mdio_lock);
+        err = __alx_read_phy_reg(hw, reg, phy_data);
+        spin_unlock(&hw->mdio_lock);
+
+        return err;
+}
+
+int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data)
+{
+        int err;
+
+        spin_lock(&hw->mdio_lock);
+        err = __alx_write_phy_reg(hw, reg, phy_data);
+        spin_unlock(&hw->mdio_lock);
+
+        return err;
+}
+
+int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata)
+{
+        int err;
+
+        spin_lock(&hw->mdio_lock);
+        err = __alx_read_phy_ext(hw, dev, reg, pdata);
+        spin_unlock(&hw->mdio_lock);
+
+        return err;
+}
+
+int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data)
+{
+        int err;
+
+        spin_lock(&hw->mdio_lock);
+        err = __alx_write_phy_ext(hw, dev, reg, data);
+        spin_unlock(&hw->mdio_lock);
+
+        return err;
+}
+
+static int alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata)
+{
+        int err;
+
+        spin_lock(&hw->mdio_lock);
+        err = __alx_read_phy_dbg(hw, reg, pdata);
+        spin_unlock(&hw->mdio_lock);
+
+        return err;
+}
+
+static int alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data)
+{
+        int err;
+
+        spin_lock(&hw->mdio_lock);
+        err = __alx_write_phy_dbg(hw, reg, data);
+        spin_unlock(&hw->mdio_lock);
+
+        return err;
+}
+
+static u16 alx_get_phy_config(struct alx_hw *hw)
+{
+        u32 val;
+        u16 phy_val;
+
+        val = alx_read_mem32(hw, ALX_PHY_CTRL);
+        /* phy in reset */
+        if ((val & ALX_PHY_CTRL_DSPRST_OUT) == 0)
+                return ALX_DRV_PHY_UNKNOWN;
+
+        val = alx_read_mem32(hw, ALX_DRV);
+        val = ALX_GET_FIELD(val, ALX_DRV_PHY);
+        if (ALX_DRV_PHY_UNKNOWN == val)
+                return ALX_DRV_PHY_UNKNOWN;
+
+        alx_read_phy_reg(hw, ALX_MII_DBG_ADDR, &phy_val);
+        if (ALX_PHY_INITED == phy_val)
+                return val;
+
+        return ALX_DRV_PHY_UNKNOWN;
+}
+
+static bool alx_wait_reg(struct alx_hw *hw, u32 reg, u32 wait, u32 *val)
+{
+        u32 read;
+        int i;
+
+        for (i = 0; i < ALX_SLD_MAX_TO; i++) {
+                read = alx_read_mem32(hw, reg);
+                if ((read & wait) == 0) {
+                        if (val)
+                                *val = read;
+                        return true;
+                }
+                mdelay(1);
+        }
+
+        return false;
+}
+
+static bool alx_read_macaddr(struct alx_hw *hw, u8 *addr)
+{
+        u32 mac0, mac1;
+
+        mac0 = alx_read_mem32(hw, ALX_STAD0);
+        mac1 = alx_read_mem32(hw, ALX_STAD1);
+
+        /* addr should be big-endian */
+        *(__be32 *)(addr + 2) = cpu_to_be32(mac0);
+        *(__be16 *)addr = cpu_to_be16(mac1);
+
+        return is_valid_ether_addr(addr);
+}
+
+int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr)
+{
+        u32 val;
+
+        /* try to get it from register first */
+        if (alx_read_macaddr(hw, addr))
+                return 0;
+
+        /* try to load from efuse */
+        if (!alx_wait_reg(hw, ALX_SLD, ALX_SLD_STAT | ALX_SLD_START, &val))
+                return -EIO;
+        alx_write_mem32(hw, ALX_SLD, val | ALX_SLD_START);
+        if (!alx_wait_reg(hw, ALX_SLD, ALX_SLD_START, NULL))
+                return -EIO;
+        if (alx_read_macaddr(hw, addr))
+                return 0;
+
+        /* try to load from flash/eeprom (if present) */
+        val = alx_read_mem32(hw, ALX_EFLD);
+        if (val & (ALX_EFLD_F_EXIST | ALX_EFLD_E_EXIST)) {
+                if (!alx_wait_reg(hw, ALX_EFLD,
+                                  ALX_EFLD_STAT | ALX_EFLD_START, &val))
+                        return -EIO;
+                alx_write_mem32(hw, ALX_EFLD, val | ALX_EFLD_START);
+                if (!alx_wait_reg(hw, ALX_EFLD, ALX_EFLD_START, NULL))
+                        return -EIO;
+                if (alx_read_macaddr(hw, addr))
+                        return 0;
+        }
+
+        return -EIO;
+}
+
+void alx_set_macaddr(struct alx_hw *hw, const u8 *addr)
+{
+        u32 val;
+
+        /* for example: 00-0B-6A-F6-00-DC * STAD0=6AF600DC, STAD1=000B */
+        val = be32_to_cpu(*(__be32 *)(addr + 2));
+        alx_write_mem32(hw, ALX_STAD0, val);
+        val = be16_to_cpu(*(__be16 *)addr);
+        alx_write_mem32(hw, ALX_STAD1, val);
+}
+
+static void alx_enable_osc(struct alx_hw *hw)
+{
+        u32 val;
+
+        /* rising edge */
+        val = alx_read_mem32(hw, ALX_MISC);
+        alx_write_mem32(hw, ALX_MISC, val & ~ALX_MISC_INTNLOSC_OPEN);
+        alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
+}
+
+static void alx_reset_osc(struct alx_hw *hw, u8 rev)
+{
+        u32 val, val2;
+
+        /* clear Internal OSC settings, switching OSC by hw itself */
+        val = alx_read_mem32(hw, ALX_MISC3);
+        alx_write_mem32(hw, ALX_MISC3,
+                        (val & ~ALX_MISC3_25M_BY_SW) |
+                        ALX_MISC3_25M_NOTO_INTNL);
+
+        /* 25M clk from chipset may be unstable 1s after de-assert of
+         * PERST, driver need re-calibrate before enter Sleep for WoL
+         */
+        val = alx_read_mem32(hw, ALX_MISC);
+        if (rev >= ALX_REV_B0) {
+                /* restore over current protection def-val,
+                 * this val could be reset by MAC-RST
+                 */
+                ALX_SET_FIELD(val, ALX_MISC_PSW_OCP, ALX_MISC_PSW_OCP_DEF);
+                /* a 0->1 change will update the internal val of osc */
+                val &= ~ALX_MISC_INTNLOSC_OPEN;
+                alx_write_mem32(hw, ALX_MISC, val);
+                alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
+                /* hw will automatically dis OSC after cab. */
+                val2 = alx_read_mem32(hw, ALX_MSIC2);
+                val2 &= ~ALX_MSIC2_CALB_START;
+                alx_write_mem32(hw, ALX_MSIC2, val2);
+                alx_write_mem32(hw, ALX_MSIC2, val2 | ALX_MSIC2_CALB_START);
+        } else {
+                val &= ~ALX_MISC_INTNLOSC_OPEN;
+                /* disable isolate for rev A devices */
+                if (alx_is_rev_a(rev))
+                        val &= ~ALX_MISC_ISO_EN;
+
+                alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
+                alx_write_mem32(hw, ALX_MISC, val);
+        }
+
+        udelay(20);
+}
+
+static int alx_stop_mac(struct alx_hw *hw)
+{
+        u32 rxq, txq, val;
+        u16 i;
+
+        rxq = alx_read_mem32(hw, ALX_RXQ0);
+        alx_write_mem32(hw, ALX_RXQ0, rxq & ~ALX_RXQ0_EN);
+        txq = alx_read_mem32(hw, ALX_TXQ0);
+        alx_write_mem32(hw, ALX_TXQ0, txq & ~ALX_TXQ0_EN);
+
+        udelay(40);
+
+        hw->rx_ctrl &= ~(ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_TX_EN);
+        alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
+
+        for (i = 0; i < ALX_DMA_MAC_RST_TO; i++) {
+                val = alx_read_mem32(hw, ALX_MAC_STS);
+                if (!(val & ALX_MAC_STS_IDLE))
+                        return 0;
+                udelay(10);
+        }
+
+        return -ETIMEDOUT;
+}
+
+int alx_reset_mac(struct alx_hw *hw)
+{
+        u32 val, pmctrl;
+        int i, ret;
+        u8 rev;
+        bool a_cr;
+
+        pmctrl = 0;
+        rev = alx_hw_revision(hw);
+        a_cr = alx_is_rev_a(rev) && alx_hw_with_cr(hw);
+
+        /* disable all interrupts, RXQ/TXQ */
+        alx_write_mem32(hw, ALX_MSIX_MASK, 0xFFFFFFFF);
+        alx_write_mem32(hw, ALX_IMR, 0);
+        alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS);
+
+        ret = alx_stop_mac(hw);
+        if (ret)
+                return ret;
+
+        /* mac reset workaroud */
+        alx_write_mem32(hw, ALX_RFD_PIDX, 1);
+
+        /* dis l0s/l1 before mac reset */
+        if (a_cr) {
+                pmctrl = alx_read_mem32(hw, ALX_PMCTRL);
+                if (pmctrl & (ALX_PMCTRL_L1_EN | ALX_PMCTRL_L0S_EN))
+                        alx_write_mem32(hw, ALX_PMCTRL,
+                                        pmctrl & ~(ALX_PMCTRL_L1_EN |
+                                                   ALX_PMCTRL_L0S_EN));
+        }
+
+        /* reset whole mac safely */
+        val = alx_read_mem32(hw, ALX_MASTER);
+        alx_write_mem32(hw, ALX_MASTER,
+                        val | ALX_MASTER_DMA_MAC_RST | ALX_MASTER_OOB_DIS);
+
+        /* make sure it's real idle */
+        udelay(10);
+        for (i = 0; i < ALX_DMA_MAC_RST_TO; i++) {
+                val = alx_read_mem32(hw, ALX_RFD_PIDX);
+                if (val == 0)
+                        break;
+                udelay(10);
+        }
+        for (; i < ALX_DMA_MAC_RST_TO; i++) {
+                val = alx_read_mem32(hw, ALX_MASTER);
+                if ((val & ALX_MASTER_DMA_MAC_RST) == 0)
+                        break;
+                udelay(10);
+        }
+        if (i == ALX_DMA_MAC_RST_TO)
+                return -EIO;
+        udelay(10);
+
+        if (a_cr) {
+                alx_write_mem32(hw, ALX_MASTER, val | ALX_MASTER_PCLKSEL_SRDS);
+                /* restore l0s / l1 */
+                if (pmctrl & (ALX_PMCTRL_L1_EN | ALX_PMCTRL_L0S_EN))
+                        alx_write_mem32(hw, ALX_PMCTRL, pmctrl);
+        }
+
+        alx_reset_osc(hw, rev);
+
+        /* clear Internal OSC settings, switching OSC by hw itself,
+         * disable isolate for rev A devices
+         */
+        val = alx_read_mem32(hw, ALX_MISC3);
+        alx_write_mem32(hw, ALX_MISC3,
+                        (val & ~ALX_MISC3_25M_BY_SW) |
+                        ALX_MISC3_25M_NOTO_INTNL);
+        val = alx_read_mem32(hw, ALX_MISC);
+        val &= ~ALX_MISC_INTNLOSC_OPEN;
+        if (alx_is_rev_a(rev))
+                val &= ~ALX_MISC_ISO_EN;
+        alx_write_mem32(hw, ALX_MISC, val);
+        udelay(20);
+
+        /* driver control speed/duplex, hash-alg */
+        alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
+
+        val = alx_read_mem32(hw, ALX_SERDES);
+        alx_write_mem32(hw, ALX_SERDES,
+                        val | ALX_SERDES_MACCLK_SLWDWN |
+                        ALX_SERDES_PHYCLK_SLWDWN);
+
+        return 0;
+}
+
+void alx_reset_phy(struct alx_hw *hw)
+{
+        int i;
+        u32 val;
+        u16 phy_val;
+
+        /* (DSP)reset PHY core */
+        val = alx_read_mem32(hw, ALX_PHY_CTRL);
+        val &= ~(ALX_PHY_CTRL_DSPRST_OUT | ALX_PHY_CTRL_IDDQ |
+                 ALX_PHY_CTRL_GATE_25M | ALX_PHY_CTRL_POWER_DOWN |
+                 ALX_PHY_CTRL_CLS);
+        val |= ALX_PHY_CTRL_RST_ANALOG;
+
+        val |= (ALX_PHY_CTRL_HIB_PULSE | ALX_PHY_CTRL_HIB_EN);
+        alx_write_mem32(hw, ALX_PHY_CTRL, val);
+        udelay(10);
+        alx_write_mem32(hw, ALX_PHY_CTRL, val | ALX_PHY_CTRL_DSPRST_OUT);
+
+        for (i = 0; i < ALX_PHY_CTRL_DSPRST_TO; i++)
+                udelay(10);
+
+        /* phy power saving & hib */
+        alx_write_phy_dbg(hw, ALX_MIIDBG_LEGCYPS, ALX_LEGCYPS_DEF);
+        alx_write_phy_dbg(hw, ALX_MIIDBG_SYSMODCTRL,
+                          ALX_SYSMODCTRL_IECHOADJ_DEF);
+        alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_VDRVBIAS,
+                          ALX_VDRVBIAS_DEF);
+
+        /* EEE advertisement */
+        val = alx_read_mem32(hw, ALX_LPI_CTRL);
+        alx_write_mem32(hw, ALX_LPI_CTRL, val & ~ALX_LPI_CTRL_EN);
+        alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_LOCAL_EEEADV, 0);
+
+        /* phy power saving */
+        alx_write_phy_dbg(hw, ALX_MIIDBG_TST10BTCFG, ALX_TST10BTCFG_DEF);
+        alx_write_phy_dbg(hw, ALX_MIIDBG_SRDSYSMOD, ALX_SRDSYSMOD_DEF);
+        alx_write_phy_dbg(hw, ALX_MIIDBG_TST100BTCFG, ALX_TST100BTCFG_DEF);
+        alx_write_phy_dbg(hw, ALX_MIIDBG_ANACTRL, ALX_ANACTRL_DEF);
+        alx_read_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, &phy_val);
+        alx_write_phy_dbg(hw, ALX_MIIDBG_GREENCFG2,
+                          phy_val & ~ALX_GREENCFG2_GATE_DFSE_EN);
+        /* rtl8139c, 120m issue */
+        alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_NLP78,
+                          ALX_MIIEXT_NLP78_120M_DEF);
+        alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_S3DIG10,
+                          ALX_MIIEXT_S3DIG10_DEF);
+
+        if (hw->lnk_patch) {
+                /* Turn off half amplitude */
+                alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL3,
+                                 &phy_val);
+                alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL3,
+                                  phy_val | ALX_CLDCTRL3_BP_CABLE1TH_DET_GT);
+                /* Turn off Green feature */
+                alx_read_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, &phy_val);
+                alx_write_phy_dbg(hw, ALX_MIIDBG_GREENCFG2,
+                                  phy_val | ALX_GREENCFG2_BP_GREEN);
+                /* Turn off half Bias */
+                alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL5,
+                                 &phy_val);
+                alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL5,
+                                  phy_val | ALX_CLDCTRL5_BP_VD_HLFBIAS);
+        }
+
+        /* set phy interrupt mask */
+        alx_write_phy_reg(hw, ALX_MII_IER, ALX_IER_LINK_UP | ALX_IER_LINK_DOWN);
+}
+
+#define ALX_PCI_CMD (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
+
+void alx_reset_pcie(struct alx_hw *hw)
+{
+        u8 rev = alx_hw_revision(hw);
+        u32 val;
+        u16 val16;
+
+        /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
+        pci_read_config_word(hw->pdev, PCI_COMMAND, &val16);
+        if (!(val16 & ALX_PCI_CMD) || (val16 & PCI_COMMAND_INTX_DISABLE)) {
+                val16 = (val16 | ALX_PCI_CMD) & ~PCI_COMMAND_INTX_DISABLE;
+                pci_write_config_word(hw->pdev, PCI_COMMAND, val16);
+        }
+
+        /* clear WoL setting/status */
+        val = alx_read_mem32(hw, ALX_WOL0);
+        alx_write_mem32(hw, ALX_WOL0, 0);
+
+        val = alx_read_mem32(hw, ALX_PDLL_TRNS1);
+        alx_write_mem32(hw, ALX_PDLL_TRNS1, val & ~ALX_PDLL_TRNS1_D3PLLOFF_EN);
+
+        /* mask some pcie error bits */
+        val = alx_read_mem32(hw, ALX_UE_SVRT);
+        val &= ~(ALX_UE_SVRT_DLPROTERR | ALX_UE_SVRT_FCPROTERR);
+        alx_write_mem32(hw, ALX_UE_SVRT, val);
+
+        /* wol 25M & pclk */
+        val = alx_read_mem32(hw, ALX_MASTER);
+        if (alx_is_rev_a(rev) && alx_hw_with_cr(hw)) {
+                if ((val & ALX_MASTER_WAKEN_25M) == 0 ||
+                    (val & ALX_MASTER_PCLKSEL_SRDS) == 0)
+                        alx_write_mem32(hw, ALX_MASTER,
+                                        val | ALX_MASTER_PCLKSEL_SRDS |
+                                        ALX_MASTER_WAKEN_25M);
+        } else {
+                if ((val & ALX_MASTER_WAKEN_25M) == 0 ||
+                    (val & ALX_MASTER_PCLKSEL_SRDS) != 0)
+                        alx_write_mem32(hw, ALX_MASTER,
+                                        (val & ~ALX_MASTER_PCLKSEL_SRDS) |
+                                        ALX_MASTER_WAKEN_25M);
+        }
+
+        /* ASPM setting */
+        alx_enable_aspm(hw, true, true);
+
+        udelay(10);
+}
+
+void alx_start_mac(struct alx_hw *hw)
+{
+        u32 mac, txq, rxq;
+
+        rxq = alx_read_mem32(hw, ALX_RXQ0);
+        alx_write_mem32(hw, ALX_RXQ0, rxq | ALX_RXQ0_EN);
+        txq = alx_read_mem32(hw, ALX_TXQ0);
+        alx_write_mem32(hw, ALX_TXQ0, txq | ALX_TXQ0_EN);
+
+        mac = hw->rx_ctrl;
+        if (hw->link_speed % 10 == DUPLEX_FULL)
+                mac |= ALX_MAC_CTRL_FULLD;
+        else
+                mac &= ~ALX_MAC_CTRL_FULLD;
+        ALX_SET_FIELD(mac, ALX_MAC_CTRL_SPEED,
+                      hw->link_speed >= SPEED_1000 ? ALX_MAC_CTRL_SPEED_1000 :
+                                                     ALX_MAC_CTRL_SPEED_10_100);
+        mac |= ALX_MAC_CTRL_TX_EN | ALX_MAC_CTRL_RX_EN;
+        hw->rx_ctrl = mac;
+        alx_write_mem32(hw, ALX_MAC_CTRL, mac);
+}
+
+void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc)
+{
+        if (fc & ALX_FC_RX)
+                hw->rx_ctrl |= ALX_MAC_CTRL_RXFC_EN;
+        else
+                hw->rx_ctrl &= ~ALX_MAC_CTRL_RXFC_EN;
+
+        if (fc & ALX_FC_TX)
+                hw->rx_ctrl |= ALX_MAC_CTRL_TXFC_EN;
+        else
+                hw->rx_ctrl &= ~ALX_MAC_CTRL_TXFC_EN;
+
+        alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
+}
+
+void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en)
+{
+        u32 pmctrl;
+        u8 rev = alx_hw_revision(hw);
+
+        pmctrl = alx_read_mem32(hw, ALX_PMCTRL);
+
+        ALX_SET_FIELD(pmctrl, ALX_PMCTRL_LCKDET_TIMER,
+                      ALX_PMCTRL_LCKDET_TIMER_DEF);
+        pmctrl |= ALX_PMCTRL_RCVR_WT_1US |
+                  ALX_PMCTRL_L1_CLKSW_EN |
+                  ALX_PMCTRL_L1_SRDSRX_PWD;
+        ALX_SET_FIELD(pmctrl, ALX_PMCTRL_L1REQ_TO, ALX_PMCTRL_L1REG_TO_DEF);
+        ALX_SET_FIELD(pmctrl, ALX_PMCTRL_L1_TIMER, ALX_PMCTRL_L1_TIMER_16US);
+        pmctrl &= ~(ALX_PMCTRL_L1_SRDS_EN |
+                    ALX_PMCTRL_L1_SRDSPLL_EN |
+                    ALX_PMCTRL_L1_BUFSRX_EN |
+                    ALX_PMCTRL_SADLY_EN |
+                    ALX_PMCTRL_HOTRST_WTEN|
+                    ALX_PMCTRL_L0S_EN |
+                    ALX_PMCTRL_L1_EN |
+                    ALX_PMCTRL_ASPM_FCEN |
+                    ALX_PMCTRL_TXL1_AFTER_L0S |
+                    ALX_PMCTRL_RXL1_AFTER_L0S);
+        if (alx_is_rev_a(rev) && alx_hw_with_cr(hw))
+                pmctrl |= ALX_PMCTRL_L1_SRDS_EN | ALX_PMCTRL_L1_SRDSPLL_EN;
+
+        if (l0s_en)
+                pmctrl |= (ALX_PMCTRL_L0S_EN | ALX_PMCTRL_ASPM_FCEN);
+        if (l1_en)
+                pmctrl |= (ALX_PMCTRL_L1_EN | ALX_PMCTRL_ASPM_FCEN);
+
+        alx_write_mem32(hw, ALX_PMCTRL, pmctrl);
+}
+
+
+static u32 ethadv_to_hw_cfg(struct alx_hw *hw, u32 ethadv_cfg)
+{
+        u32 cfg = 0;
+
+        if (ethadv_cfg & ADVERTISED_Autoneg) {
+                cfg |= ALX_DRV_PHY_AUTO;
+                if (ethadv_cfg & ADVERTISED_10baseT_Half)
+                        cfg |= ALX_DRV_PHY_10;
+                if (ethadv_cfg & ADVERTISED_10baseT_Full)
+                        cfg |= ALX_DRV_PHY_10 | ALX_DRV_PHY_DUPLEX;
+                if (ethadv_cfg & ADVERTISED_100baseT_Half)
+                        cfg |= ALX_DRV_PHY_100;
+                if (ethadv_cfg & ADVERTISED_100baseT_Full)
+                        cfg |= ALX_DRV_PHY_100 | ALX_DRV_PHY_DUPLEX;
+                if (ethadv_cfg & ADVERTISED_1000baseT_Half)
+                        cfg |= ALX_DRV_PHY_1000;
+                if (ethadv_cfg & ADVERTISED_1000baseT_Full)
+                        cfg |= ALX_DRV_PHY_100 | ALX_DRV_PHY_DUPLEX;
+                if (ethadv_cfg & ADVERTISED_Pause)
+                        cfg |= ADVERTISE_PAUSE_CAP;
+                if (ethadv_cfg & ADVERTISED_Asym_Pause)
+                        cfg |= ADVERTISE_PAUSE_ASYM;
+        } else {
+                switch (ethadv_cfg) {
+                case ADVERTISED_10baseT_Half:
+                        cfg |= ALX_DRV_PHY_10;
+                        break;
+                case ADVERTISED_100baseT_Half:
+                        cfg |= ALX_DRV_PHY_100;
+                        break;
+                case ADVERTISED_10baseT_Full:
+                        cfg |= ALX_DRV_PHY_10 | ALX_DRV_PHY_DUPLEX;
+                        break;
+                case ADVERTISED_100baseT_Full:
+                        cfg |= ALX_DRV_PHY_100 | ALX_DRV_PHY_DUPLEX;
+                        break;
+                }
+        }
+
+        return cfg;
+}
+
+int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl)
+{
+        u16 adv, giga, cr;
+        u32 val;
+        int err = 0;
+
+        alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, 0);
+        val = alx_read_mem32(hw, ALX_DRV);
+        ALX_SET_FIELD(val, ALX_DRV_PHY, 0);
+
+        if (ethadv & ADVERTISED_Autoneg) {
+                adv = ADVERTISE_CSMA;
+                adv |= ethtool_adv_to_mii_adv_t(ethadv);
+
+                if (flowctrl & ALX_FC_ANEG) {
+                        if (flowctrl & ALX_FC_RX) {
+                                adv |= ADVERTISED_Pause;
+                                if (!(flowctrl & ALX_FC_TX))
+                                        adv |= ADVERTISED_Asym_Pause;
+                        } else if (flowctrl & ALX_FC_TX) {
+                                adv |= ADVERTISED_Asym_Pause;
+                        }
+                }
+                giga = 0;
+                if (alx_hw_giga(hw))
+                        giga = ethtool_adv_to_mii_ctrl1000_t(ethadv);
+
+                cr = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART;
+
+                if (alx_write_phy_reg(hw, MII_ADVERTISE, adv) ||
+                    alx_write_phy_reg(hw, MII_CTRL1000, giga) ||
+                    alx_write_phy_reg(hw, MII_BMCR, cr))
+                        err = -EBUSY;
+        } else {
+                cr = BMCR_RESET;
+                if (ethadv == ADVERTISED_100baseT_Half ||
+                    ethadv == ADVERTISED_100baseT_Full)
+                        cr |= BMCR_SPEED100;
+                if (ethadv == ADVERTISED_10baseT_Full ||
+                    ethadv == ADVERTISED_100baseT_Full)
+                        cr |= BMCR_FULLDPLX;
+
+                err = alx_write_phy_reg(hw, MII_BMCR, cr);
+        }
+
+        if (!err) {
+                alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, ALX_PHY_INITED);
+                val |= ethadv_to_hw_cfg(hw, ethadv);
+        }
+
+        alx_write_mem32(hw, ALX_DRV, val);
+
+        return err;
+}
+
+
+void alx_post_phy_link(struct alx_hw *hw)
+{
+        u16 phy_val, len, agc;
+        u8 revid = alx_hw_revision(hw);
+        bool adj_th = revid == ALX_REV_B0;
+        int speed;
+
+        if (hw->link_speed == SPEED_UNKNOWN)
+                speed = SPEED_UNKNOWN;
+        else
+                speed = hw->link_speed - hw->link_speed % 10;
+
+        if (revid != ALX_REV_B0 && !alx_is_rev_a(revid))
+                return;
+
+        /* 1000BT/AZ, wrong cable length */
+        if (speed != SPEED_UNKNOWN) {
+                alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL6,
+                                 &phy_val);
+                len = ALX_GET_FIELD(phy_val, ALX_CLDCTRL6_CAB_LEN);
+                alx_read_phy_dbg(hw, ALX_MIIDBG_AGC, &phy_val);
+                agc = ALX_GET_FIELD(phy_val, ALX_AGC_2_VGA);
+
+                if ((speed == SPEED_1000 &&
+                     (len > ALX_CLDCTRL6_CAB_LEN_SHORT1G ||
+                      (len == 0 && agc > ALX_AGC_LONG1G_LIMT))) ||
+                    (speed == SPEED_100 &&
+                     (len > ALX_CLDCTRL6_CAB_LEN_SHORT100M ||
+                      (len == 0 && agc > ALX_AGC_LONG100M_LIMT)))) {
+                        alx_write_phy_dbg(hw, ALX_MIIDBG_AZ_ANADECT,
+                                          ALX_AZ_ANADECT_LONG);
+                        alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
+                                         &phy_val);
+                        alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
+                                          phy_val | ALX_AFE_10BT_100M_TH);
+                } else {
+                        alx_write_phy_dbg(hw, ALX_MIIDBG_AZ_ANADECT,
+                                          ALX_AZ_ANADECT_DEF);
+                        alx_read_phy_ext(hw, ALX_MIIEXT_ANEG,
+                                         ALX_MIIEXT_AFE, &phy_val);
+                        alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
+                                          phy_val & ~ALX_AFE_10BT_100M_TH);
+                }
+
+                /* threshold adjust */
+                if (adj_th && hw->lnk_patch) {
+                        if (speed == SPEED_100) {
+                                alx_write_phy_dbg(hw, ALX_MIIDBG_MSE16DB,
+                                                  ALX_MSE16DB_UP);
+                        } else if (speed == SPEED_1000) {
+                                /*
+                                 * Giga link threshold, raise the tolerance of
+                                 * noise 50%
+                                 */
+                                alx_read_phy_dbg(hw, ALX_MIIDBG_MSE20DB,
+                                                 &phy_val);
+                                ALX_SET_FIELD(phy_val, ALX_MSE20DB_TH,
+                                              ALX_MSE20DB_TH_HI);
+                                alx_write_phy_dbg(hw, ALX_MIIDBG_MSE20DB,
+                                                  phy_val);
+                        }
+                }
+        } else {
+                alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
+                                 &phy_val);
+                alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
+                                  phy_val & ~ALX_AFE_10BT_100M_TH);
+
+                if (adj_th && hw->lnk_patch) {
+                        alx_write_phy_dbg(hw, ALX_MIIDBG_MSE16DB,
+                                          ALX_MSE16DB_DOWN);
+                        alx_read_phy_dbg(hw, ALX_MIIDBG_MSE20DB, &phy_val);
+                        ALX_SET_FIELD(phy_val, ALX_MSE20DB_TH,
+                                      ALX_MSE20DB_TH_DEF);
+                        alx_write_phy_dbg(hw, ALX_MIIDBG_MSE20DB, phy_val);
+                }
+        }
+}
+
+
+/* NOTE:
+ *    1. phy link must be established before calling this function
+ *    2. wol option (pattern,magic,link,etc.) is configed before call it.
+ */
+int alx_pre_suspend(struct alx_hw *hw, int speed)
+{
+        u32 master, mac, phy, val;
+        int err = 0;
+
+        master = alx_read_mem32(hw, ALX_MASTER);
+        master &= ~ALX_MASTER_PCLKSEL_SRDS;
+        mac = hw->rx_ctrl;
+        /* 10/100 half */
+        ALX_SET_FIELD(mac, ALX_MAC_CTRL_SPEED,  ALX_MAC_CTRL_SPEED_10_100);
+        mac &= ~(ALX_MAC_CTRL_FULLD | ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_TX_EN);
+
+        phy = alx_read_mem32(hw, ALX_PHY_CTRL);
+        phy &= ~(ALX_PHY_CTRL_DSPRST_OUT | ALX_PHY_CTRL_CLS);
+        phy |= ALX_PHY_CTRL_RST_ANALOG | ALX_PHY_CTRL_HIB_PULSE |
+               ALX_PHY_CTRL_HIB_EN;
+
+        /* without any activity  */
+        if (!(hw->sleep_ctrl & ALX_SLEEP_ACTIVE)) {
+                err = alx_write_phy_reg(hw, ALX_MII_IER, 0);
+                if (err)
+                        return err;
+                phy |= ALX_PHY_CTRL_IDDQ | ALX_PHY_CTRL_POWER_DOWN;
+        } else {
+                if (hw->sleep_ctrl & (ALX_SLEEP_WOL_MAGIC | ALX_SLEEP_CIFS))
+                        mac |= ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_BRD_EN;
+                if (hw->sleep_ctrl & ALX_SLEEP_CIFS)
+                        mac |= ALX_MAC_CTRL_TX_EN;
+                if (speed % 10 == DUPLEX_FULL)
+                        mac |= ALX_MAC_CTRL_FULLD;
+                if (speed >= SPEED_1000)
+                        ALX_SET_FIELD(mac, ALX_MAC_CTRL_SPEED,
+                                      ALX_MAC_CTRL_SPEED_1000);
+                phy |= ALX_PHY_CTRL_DSPRST_OUT;
+                err = alx_write_phy_ext(hw, ALX_MIIEXT_ANEG,
+                                        ALX_MIIEXT_S3DIG10,
+                                        ALX_MIIEXT_S3DIG10_SL);
+                if (err)
+                        return err;
+        }
+
+        alx_enable_osc(hw);
+        hw->rx_ctrl = mac;
+        alx_write_mem32(hw, ALX_MASTER, master);
+        alx_write_mem32(hw, ALX_MAC_CTRL, mac);
+        alx_write_mem32(hw, ALX_PHY_CTRL, phy);
+
+        /* set val of PDLL D3PLLOFF */
+        val = alx_read_mem32(hw, ALX_PDLL_TRNS1);
+        val |= ALX_PDLL_TRNS1_D3PLLOFF_EN;
+        alx_write_mem32(hw, ALX_PDLL_TRNS1, val);
+
+        return 0;
+}
+
+bool alx_phy_configured(struct alx_hw *hw)
+{
+        u32 cfg, hw_cfg;
+
+        cfg = ethadv_to_hw_cfg(hw, hw->adv_cfg);
+        cfg = ALX_GET_FIELD(cfg, ALX_DRV_PHY);
+        hw_cfg = alx_get_phy_config(hw);
+
+        if (hw_cfg == ALX_DRV_PHY_UNKNOWN)
+                return false;
+
+        return cfg == hw_cfg;
+}
+
+int alx_get_phy_link(struct alx_hw *hw, int *speed)
+{
+        struct pci_dev *pdev = hw->pdev;
+        u16 bmsr, giga;
+        int err;
+
+        err = alx_read_phy_reg(hw, MII_BMSR, &bmsr);
+        if (err)
+                return err;
+
+        err = alx_read_phy_reg(hw, MII_BMSR, &bmsr);
+        if (err)
+                return err;
+
+        if (!(bmsr & BMSR_LSTATUS)) {
+                *speed = SPEED_UNKNOWN;
+                return 0;
+        }
+
+        /* speed/duplex result is saved in PHY Specific Status Register */
+        err = alx_read_phy_reg(hw, ALX_MII_GIGA_PSSR, &giga);
+        if (err)
+                return err;
+
+        if (!(giga & ALX_GIGA_PSSR_SPD_DPLX_RESOLVED))
+                goto wrong_speed;
+
+        switch (giga & ALX_GIGA_PSSR_SPEED) {
+        case ALX_GIGA_PSSR_1000MBS:
+                *speed = SPEED_1000;
+                break;
+        case ALX_GIGA_PSSR_100MBS:
+                *speed = SPEED_100;
+                break;
+        case ALX_GIGA_PSSR_10MBS:
+                *speed = SPEED_10;
+                break;
+        default:
+                goto wrong_speed;
+        }
+
+        *speed += (giga & ALX_GIGA_PSSR_DPLX) ? DUPLEX_FULL : DUPLEX_HALF;
+        return 1;
+
+wrong_speed:
+        dev_err(&pdev->dev, "invalid PHY speed/duplex: 0x%x\n", giga);
+        return -EINVAL;
+}
+
+int alx_clear_phy_intr(struct alx_hw *hw)
+{
+        u16 isr;
+
+        /* clear interrupt status by reading it */
+        return alx_read_phy_reg(hw, ALX_MII_ISR, &isr);
+}
+
+int alx_config_wol(struct alx_hw *hw)
+{
+        u32 wol = 0;
+        int err = 0;
+
+        /* turn on magic packet event */
+        if (hw->sleep_ctrl & ALX_SLEEP_WOL_MAGIC)
+                wol |= ALX_WOL0_MAGIC_EN | ALX_WOL0_PME_MAGIC_EN;
+
+        /* turn on link up event */
+        if (hw->sleep_ctrl & ALX_SLEEP_WOL_PHY) {
+                wol |=  ALX_WOL0_LINK_EN | ALX_WOL0_PME_LINK;
+                /* only link up can wake up */
+                err = alx_write_phy_reg(hw, ALX_MII_IER, ALX_IER_LINK_UP);
+        }
+        alx_write_mem32(hw, ALX_WOL0, wol);
+
+        return err;
+}
+
+void alx_disable_rss(struct alx_hw *hw)
+{
+        u32 ctrl = alx_read_mem32(hw, ALX_RXQ0);
+
+        ctrl &= ~ALX_RXQ0_RSS_HASH_EN;
+        alx_write_mem32(hw, ALX_RXQ0, ctrl);
+}
+
+void alx_configure_basic(struct alx_hw *hw)
+{
+        u32 val, raw_mtu, max_payload;
+        u16 val16;
+        u8 chip_rev = alx_hw_revision(hw);
+
+        alx_set_macaddr(hw, hw->mac_addr);
+
+        alx_write_mem32(hw, ALX_CLK_GATE, ALX_CLK_GATE_ALL);
+
+        /* idle timeout to switch clk_125M */
+        if (chip_rev >= ALX_REV_B0)
+                alx_write_mem32(hw, ALX_IDLE_DECISN_TIMER,
+                                ALX_IDLE_DECISN_TIMER_DEF);
+
+        alx_write_mem32(hw, ALX_SMB_TIMER, hw->smb_timer * 500UL);
+
+        val = alx_read_mem32(hw, ALX_MASTER);
+        val |= ALX_MASTER_IRQMOD2_EN |
+               ALX_MASTER_IRQMOD1_EN |
+               ALX_MASTER_SYSALVTIMER_EN;
+        alx_write_mem32(hw, ALX_MASTER, val);
+        alx_write_mem32(hw, ALX_IRQ_MODU_TIMER,
+                        (hw->imt >> 1) << ALX_IRQ_MODU_TIMER1_SHIFT);
+        /* intr re-trig timeout */
+        alx_write_mem32(hw, ALX_INT_RETRIG, ALX_INT_RETRIG_TO);
+        /* tpd threshold to trig int */
+        alx_write_mem32(hw, ALX_TINT_TPD_THRSHLD, hw->ith_tpd);
+        alx_write_mem32(hw, ALX_TINT_TIMER, hw->imt);
+
+        raw_mtu = hw->mtu + ETH_HLEN;
+        alx_write_mem32(hw, ALX_MTU, raw_mtu + 8);
+        if (raw_mtu > ALX_MTU_JUMBO_TH)
+                hw->rx_ctrl &= ~ALX_MAC_CTRL_FAST_PAUSE;
+
+        if ((raw_mtu + 8) < ALX_TXQ1_JUMBO_TSO_TH)
+                val = (raw_mtu + 8 + 7) >> 3;
+        else
+                val = ALX_TXQ1_JUMBO_TSO_TH >> 3;
+        alx_write_mem32(hw, ALX_TXQ1, val | ALX_TXQ1_ERRLGPKT_DROP_EN);
+
+        max_payload = pcie_get_readrq(hw->pdev) >> 8;
+        /*
+         * if BIOS had changed the default dma read max length,
+         * restore it to default value
+         */
+        if (max_payload < ALX_DEV_CTRL_MAXRRS_MIN)
+                pcie_set_readrq(hw->pdev, 128 << ALX_DEV_CTRL_MAXRRS_MIN);
+
+        val = ALX_TXQ_TPD_BURSTPREF_DEF << ALX_TXQ0_TPD_BURSTPREF_SHIFT |
+              ALX_TXQ0_MODE_ENHANCE | ALX_TXQ0_LSO_8023_EN |
+              ALX_TXQ0_SUPT_IPOPT |
+              ALX_TXQ_TXF_BURST_PREF_DEF << ALX_TXQ0_TXF_BURST_PREF_SHIFT;
+        alx_write_mem32(hw, ALX_TXQ0, val);
+        val = ALX_TXQ_TPD_BURSTPREF_DEF << ALX_HQTPD_Q1_NUMPREF_SHIFT |
+              ALX_TXQ_TPD_BURSTPREF_DEF << ALX_HQTPD_Q2_NUMPREF_SHIFT |
+              ALX_TXQ_TPD_BURSTPREF_DEF << ALX_HQTPD_Q3_NUMPREF_SHIFT |
+              ALX_HQTPD_BURST_EN;
+        alx_write_mem32(hw, ALX_HQTPD, val);
+
+        /* rxq, flow control */
+        val = alx_read_mem32(hw, ALX_SRAM5);
+        val = ALX_GET_FIELD(val, ALX_SRAM_RXF_LEN) << 3;
+        if (val > ALX_SRAM_RXF_LEN_8K) {
+                val16 = ALX_MTU_STD_ALGN >> 3;
+                val = (val - ALX_RXQ2_RXF_FLOW_CTRL_RSVD) >> 3;
+        } else {
+                val16 = ALX_MTU_STD_ALGN >> 3;
+                val = (val - ALX_MTU_STD_ALGN) >> 3;
+        }
+        alx_write_mem32(hw, ALX_RXQ2,
+                        val16 << ALX_RXQ2_RXF_XOFF_THRESH_SHIFT |
+                        val << ALX_RXQ2_RXF_XON_THRESH_SHIFT);
+        val = ALX_RXQ0_NUM_RFD_PREF_DEF << ALX_RXQ0_NUM_RFD_PREF_SHIFT |
+              ALX_RXQ0_RSS_MODE_DIS << ALX_RXQ0_RSS_MODE_SHIFT |
+              ALX_RXQ0_IDT_TBL_SIZE_DEF << ALX_RXQ0_IDT_TBL_SIZE_SHIFT |
+              ALX_RXQ0_RSS_HSTYP_ALL | ALX_RXQ0_RSS_HASH_EN |
+              ALX_RXQ0_IPV6_PARSE_EN;
+
+        if (alx_hw_giga(hw))
+                ALX_SET_FIELD(val, ALX_RXQ0_ASPM_THRESH,
+                              ALX_RXQ0_ASPM_THRESH_100M);
+
+        alx_write_mem32(hw, ALX_RXQ0, val);
+
+        val = alx_read_mem32(hw, ALX_DMA);
+        val = ALX_DMA_RORDER_MODE_OUT << ALX_DMA_RORDER_MODE_SHIFT |
+              ALX_DMA_RREQ_PRI_DATA |
+              max_payload << ALX_DMA_RREQ_BLEN_SHIFT |
+              ALX_DMA_WDLY_CNT_DEF << ALX_DMA_WDLY_CNT_SHIFT |
+              ALX_DMA_RDLY_CNT_DEF << ALX_DMA_RDLY_CNT_SHIFT |
+              (hw->dma_chnl - 1) << ALX_DMA_RCHNL_SEL_SHIFT;
+        alx_write_mem32(hw, ALX_DMA, val);
+
+        /* default multi-tx-q weights */
+        val = ALX_WRR_PRI_RESTRICT_NONE << ALX_WRR_PRI_SHIFT |
+              4 << ALX_WRR_PRI0_SHIFT |
+              4 << ALX_WRR_PRI1_SHIFT |
+              4 << ALX_WRR_PRI2_SHIFT |
+              4 << ALX_WRR_PRI3_SHIFT;
+        alx_write_mem32(hw, ALX_WRR, val);
+}
+
+static inline u32 alx_speed_to_ethadv(int speed)
+{
+        switch (speed) {
+        case SPEED_1000 + DUPLEX_FULL:
+                return ADVERTISED_1000baseT_Full;
+        case SPEED_100 + DUPLEX_FULL:
+                return ADVERTISED_100baseT_Full;
+        case SPEED_100 + DUPLEX_HALF:
+                return ADVERTISED_10baseT_Half;
+        case SPEED_10 + DUPLEX_FULL:
+                return ADVERTISED_10baseT_Full;
+        case SPEED_10 + DUPLEX_HALF:
+                return ADVERTISED_10baseT_Half;
+        default:
+                return 0;
+        }
+}
+
+int alx_select_powersaving_speed(struct alx_hw *hw, int *speed)
+{
+        int i, err, spd;
+        u16 lpa;
+
+        err = alx_get_phy_link(hw, &spd);
+        if (err < 0)
+                return err;
+
+        if (spd == SPEED_UNKNOWN)
+                return 0;
+
+        err = alx_read_phy_reg(hw, MII_LPA, &lpa);
+        if (err)
+                return err;
+
+        if (!(lpa & LPA_LPACK)) {
+                *speed = spd;
+                return 0;
+        }
+
+        if (lpa & LPA_10FULL)
+                *speed = SPEED_10 + DUPLEX_FULL;
+        else if (lpa & LPA_10HALF)
+                *speed = SPEED_10 + DUPLEX_HALF;
+        else if (lpa & LPA_100FULL)
+                *speed = SPEED_100 + DUPLEX_FULL;
+        else
+                *speed = SPEED_100 + DUPLEX_HALF;
+
+        if (*speed != spd) {
+                err = alx_write_phy_reg(hw, ALX_MII_IER, 0);
+                if (err)
+                        return err;
+                err = alx_setup_speed_duplex(hw,
+                                             alx_speed_to_ethadv(*speed) |
+                                             ADVERTISED_Autoneg,
+                                             ALX_FC_ANEG | ALX_FC_RX |
+                                             ALX_FC_TX);
+                if (err)
+                        return err;
+
+                /* wait for linkup */
+                for (i = 0; i < ALX_MAX_SETUP_LNK_CYCLE; i++) {
+                        int speed2;
+
+                        msleep(100);
+
+                        err = alx_get_phy_link(hw, &speed2);
+                        if (err < 0)
+                                return err;
+                        if (speed2 != SPEED_UNKNOWN)
+                                break;
+                }
+                if (i == ALX_MAX_SETUP_LNK_CYCLE)
+                        return -ETIMEDOUT;
+        }
+
+        return 0;
+}
+
+bool alx_get_phy_info(struct alx_hw *hw)
+{
+        u16  devs1, devs2;
+
+        if (alx_read_phy_reg(hw, MII_PHYSID1, &hw->phy_id[0]) ||
+            alx_read_phy_reg(hw, MII_PHYSID2, &hw->phy_id[1]))
+                return false;
+
+        /* since we haven't PMA/PMD status2 register, we can't
+         * use mdio45_probe function for prtad and mmds.
+         * use fixed MMD3 to get mmds.
+         */
+        if (alx_read_phy_ext(hw, 3, MDIO_DEVS1, &devs1) ||
+            alx_read_phy_ext(hw, 3, MDIO_DEVS2, &devs2))
+                return false;
+        hw->mdio.mmds = devs1 | devs2 << 16;
+
+        return true;
+}
diff --git a/drivers/net/ethernet/atheros/alx/hw.h b/drivers/net/ethernet/atheros/alx/hw.h
new file mode 100644
index 000000000000..65e723d2172a
--- /dev/null
+++ b/drivers/net/ethernet/atheros/alx/hw.h
@@ -0,0 +1,499 @@
+/*
+ * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
+ *
+ *  This file is free software: you may copy, redistribute and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation, either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  This file is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef ALX_HW_H_
+#define ALX_HW_H_
+#include <linux/types.h>
+#include <linux/mdio.h>
+#include <linux/pci.h>
+#include "reg.h"
+
+/* Transmit Packet Descriptor, contains 4 32-bit words.
+ *
+ *   31               16               0
+ *   +----------------+----------------+
+ *   |    vlan-tag    |   buf length   |
+ *   +----------------+----------------+
+ *   |              Word 1             |
+ *   +----------------+----------------+
+ *   |      Word 2: buf addr lo        |
+ *   +----------------+----------------+
+ *   |      Word 3: buf addr hi        |
+ *   +----------------+----------------+
+ *
+ * Word 2 and 3 combine to form a 64-bit buffer address
+ *
+ * Word 1 has three forms, depending on the state of bit 8/12/13:
+ * if bit8 =='1', the definition is just for custom checksum offload.
+ * if bit8 == '0' && bit12 == '1' && bit13 == '1', the *FIRST* descriptor
+ *     for the skb is special for LSO V2, Word 2 become total skb length ,
+ *     Word 3 is meaningless.
+ * other condition, the definition is for general skb or ip/tcp/udp
+ *     checksum or LSO(TSO) offload.
+ *
+ * Here is the depiction:
+ *
+ *   0-+                                  0-+
+ *   1 |                                  1 |
+ *   2 |                                  2 |
+ *   3 |    Payload offset                3 |    L4 header offset
+ *   4 |        (7:0)                     4 |        (7:0)
+ *   5 |                                  5 |
+ *   6 |                                  6 |
+ *   7-+                                  7-+
+ *   8      Custom csum enable = 1        8      Custom csum enable = 0
+ *   9      General IPv4 checksum         9      General IPv4 checksum
+ *   10     General TCP checksum          10     General TCP checksum
+ *   11     General UDP checksum          11     General UDP checksum
+ *   12     Large Send Segment enable     12     Large Send Segment enable
+ *   13     Large Send Segment type       13     Large Send Segment type
+ *   14     VLAN tagged                   14     VLAN tagged
+ *   15     Insert VLAN tag               15     Insert VLAN tag
+ *   16     IPv4 packet                   16     IPv4 packet
+ *   17     Ethernet frame type           17     Ethernet frame type
+ *   18-+                                 18-+
+ *   19 |                                 19 |
+ *   20 |                                 20 |
+ *   21 |   Custom csum offset            21 |
+ *   22 |       (25:18)                   22 |
+ *   23 |                                 23 |   MSS (30:18)
+ *   24 |                                 24 |
+ *   25-+                                 25 |
+ *   26-+                                 26 |
+ *   27 |                                 27 |
+ *   28 |   Reserved                      28 |
+ *   29 |                                 29 |
+ *   30-+                                 30-+
+ *   31     End of packet                 31     End of packet
+ */
+struct alx_txd {
+        __le16 len;
+        __le16 vlan_tag;
+        __le32 word1;
+        union {
+                __le64 addr;
+                struct {
+                        __le32 pkt_len;
+                        __le32 resvd;
+                } l;
+        } adrl;
+} __packed;
+
+/* tpd word 1 */
+#define TPD_CXSUMSTART_MASK             0x00FF
+#define TPD_CXSUMSTART_SHIFT            0
+#define TPD_L4HDROFFSET_MASK            0x00FF
+#define TPD_L4HDROFFSET_SHIFT           0
+#define TPD_CXSUM_EN_MASK               0x0001
+#define TPD_CXSUM_EN_SHIFT              8
+#define TPD_IP_XSUM_MASK                0x0001
+#define TPD_IP_XSUM_SHIFT               9
+#define TPD_TCP_XSUM_MASK               0x0001
+#define TPD_TCP_XSUM_SHIFT              10
+#define TPD_UDP_XSUM_MASK               0x0001
+#define TPD_UDP_XSUM_SHIFT              11
+#define TPD_LSO_EN_MASK                 0x0001
+#define TPD_LSO_EN_SHIFT                12
+#define TPD_LSO_V2_MASK                 0x0001
+#define TPD_LSO_V2_SHIFT                13
+#define TPD_VLTAGGED_MASK               0x0001
+#define TPD_VLTAGGED_SHIFT              14
+#define TPD_INS_VLTAG_MASK              0x0001
+#define TPD_INS_VLTAG_SHIFT             15
+#define TPD_IPV4_MASK                   0x0001
+#define TPD_IPV4_SHIFT                  16
+#define TPD_ETHTYPE_MASK                0x0001
+#define TPD_ETHTYPE_SHIFT               17
+#define TPD_CXSUMOFFSET_MASK            0x00FF
+#define TPD_CXSUMOFFSET_SHIFT           18
+#define TPD_MSS_MASK                    0x1FFF
+#define TPD_MSS_SHIFT                   18
+#define TPD_EOP_MASK                    0x0001
+#define TPD_EOP_SHIFT                   31
+
+#define DESC_GET(_x, _name) ((_x) >> _name##SHIFT & _name##MASK)
+
+/* Receive Free Descriptor */
+struct alx_rfd {
+        __le64 addr;            /* data buffer address, length is
+                                 * declared in register --- every
+                                 * buffer has the same size
+                                 */
+} __packed;
+
+/* Receive Return Descriptor, contains 4 32-bit words.
+ *
+ *   31               16               0
+ *   +----------------+----------------+
+ *   |              Word 0             |
+ *   +----------------+----------------+
+ *   |     Word 1: RSS Hash value      |
+ *   +----------------+----------------+
+ *   |              Word 2             |
+ *   +----------------+----------------+
+ *   |              Word 3             |
+ *   +----------------+----------------+
+ *
+ * Word 0 depiction         &            Word 2 depiction:
+ *
+ *   0--+                                 0--+
+ *   1  |                                 1  |
+ *   2  |                                 2  |
+ *   3  |                                 3  |
+ *   4  |                                 4  |
+ *   5  |                                 5  |
+ *   6  |                                 6  |
+ *   7  |    IP payload checksum          7  |     VLAN tag
+ *   8  |         (15:0)                  8  |      (15:0)
+ *   9  |                                 9  |
+ *   10 |                                 10 |
+ *   11 |                                 11 |
+ *   12 |                                 12 |
+ *   13 |                                 13 |
+ *   14 |                                 14 |
+ *   15-+                                 15-+
+ *   16-+                                 16-+
+ *   17 |     Number of RFDs              17 |
+ *   18 |        (19:16)                  18 |
+ *   19-+                                 19 |     Protocol ID
+ *   20-+                                 20 |      (23:16)
+ *   21 |                                 21 |
+ *   22 |                                 22 |
+ *   23 |                                 23-+
+ *   24 |                                 24 |     Reserved
+ *   25 |     Start index of RFD-ring     25-+
+ *   26 |         (31:20)                 26 |     RSS Q-num (27:25)
+ *   27 |                                 27-+
+ *   28 |                                 28-+
+ *   29 |                                 29 |     RSS Hash algorithm
+ *   30 |                                 30 |      (31:28)
+ *   31-+                                 31-+
+ *
+ * Word 3 depiction:
+ *
+ *   0--+
+ *   1  |
+ *   2  |
+ *   3  |
+ *   4  |
+ *   5  |
+ *   6  |
+ *   7  |    Packet length (include FCS)
+ *   8  |         (13:0)
+ *   9  |
+ *   10 |
+ *   11 |
+ *   12 |
+ *   13-+
+ *   14      L4 Header checksum error
+ *   15      IPv4 checksum error
+ *   16      VLAN tagged
+ *   17-+
+ *   18 |    Protocol ID (19:17)
+ *   19-+
+ *   20      Receive error summary
+ *   21      FCS(CRC) error
+ *   22      Frame alignment error
+ *   23      Truncated packet
+ *   24      Runt packet
+ *   25      Incomplete packet due to insufficient rx-desc
+ *   26      Broadcast packet
+ *   27      Multicast packet
+ *   28      Ethernet type (EII or 802.3)
+ *   29      FIFO overflow
+ *   30      Length error (for 802.3, length field mismatch with actual len)
+ *   31      Updated, indicate to driver that this RRD is refreshed.
+ */
+struct alx_rrd {
+        __le32 word0;
+        __le32 rss_hash;
+        __le32 word2;
+        __le32 word3;
+} __packed;
+
+/* rrd word 0 */
+#define RRD_XSUM_MASK           0xFFFF
+#define RRD_XSUM_SHIFT          0
+#define RRD_NOR_MASK            0x000F
+#define RRD_NOR_SHIFT           16
+#define RRD_SI_MASK             0x0FFF
+#define RRD_SI_SHIFT            20
+
+/* rrd word 2 */
+#define RRD_VLTAG_MASK          0xFFFF
+#define RRD_VLTAG_SHIFT         0
+#define RRD_PID_MASK            0x00FF
+#define RRD_PID_SHIFT           16
+/* non-ip packet */
+#define RRD_PID_NONIP           0
+/* ipv4(only) */
+#define RRD_PID_IPV4            1
+/* tcp/ipv6 */
+#define RRD_PID_IPV6TCP         2
+/* tcp/ipv4 */
+#define RRD_PID_IPV4TCP         3
+/* udp/ipv6 */
+#define RRD_PID_IPV6UDP         4
+/* udp/ipv4 */
+#define RRD_PID_IPV4UDP         5
+/* ipv6(only) */
+#define RRD_PID_IPV6            6
+/* LLDP packet */
+#define RRD_PID_LLDP            7
+/* 1588 packet */
+#define RRD_PID_1588            8
+#define RRD_RSSQ_MASK           0x0007
+#define RRD_RSSQ_SHIFT          25
+#define RRD_RSSALG_MASK         0x000F
+#define RRD_RSSALG_SHIFT        28
+#define RRD_RSSALG_TCPV6        0x1
+#define RRD_RSSALG_IPV6         0x2
+#define RRD_RSSALG_TCPV4        0x4
+#define RRD_RSSALG_IPV4         0x8
+
+/* rrd word 3 */
+#define RRD_PKTLEN_MASK         0x3FFF
+#define RRD_PKTLEN_SHIFT        0
+#define RRD_ERR_L4_MASK         0x0001
+#define RRD_ERR_L4_SHIFT        14
+#define RRD_ERR_IPV4_MASK       0x0001
+#define RRD_ERR_IPV4_SHIFT      15
+#define RRD_VLTAGGED_MASK       0x0001
+#define RRD_VLTAGGED_SHIFT      16
+#define RRD_OLD_PID_MASK        0x0007
+#define RRD_OLD_PID_SHIFT       17
+#define RRD_ERR_RES_MASK        0x0001
+#define RRD_ERR_RES_SHIFT       20
+#define RRD_ERR_FCS_MASK        0x0001
+#define RRD_ERR_FCS_SHIFT       21
+#define RRD_ERR_FAE_MASK        0x0001
+#define RRD_ERR_FAE_SHIFT       22
+#define RRD_ERR_TRUNC_MASK      0x0001
+#define RRD_ERR_TRUNC_SHIFT     23
+#define RRD_ERR_RUNT_MASK       0x0001
+#define RRD_ERR_RUNT_SHIFT      24
+#define RRD_ERR_ICMP_MASK       0x0001
+#define RRD_ERR_ICMP_SHIFT      25
+#define RRD_BCAST_MASK          0x0001
+#define RRD_BCAST_SHIFT         26
+#define RRD_MCAST_MASK          0x0001
+#define RRD_MCAST_SHIFT         27
+#define RRD_ETHTYPE_MASK        0x0001
+#define RRD_ETHTYPE_SHIFT       28
+#define RRD_ERR_FIFOV_MASK      0x0001
+#define RRD_ERR_FIFOV_SHIFT     29
+#define RRD_ERR_LEN_MASK        0x0001
+#define RRD_ERR_LEN_SHIFT       30
+#define RRD_UPDATED_MASK        0x0001
+#define RRD_UPDATED_SHIFT       31
+
+
+#define ALX_MAX_SETUP_LNK_CYCLE 50
+
+/* for FlowControl */
+#define ALX_FC_RX               0x01
+#define ALX_FC_TX               0x02
+#define ALX_FC_ANEG             0x04
+
+/* for sleep control */
+#define ALX_SLEEP_WOL_PHY       0x00000001
+#define ALX_SLEEP_WOL_MAGIC     0x00000002
+#define ALX_SLEEP_CIFS          0x00000004
+#define ALX_SLEEP_ACTIVE        (ALX_SLEEP_WOL_PHY | \
+                                 ALX_SLEEP_WOL_MAGIC | \
+                                 ALX_SLEEP_CIFS)
+
+/* for RSS hash type */
+#define ALX_RSS_HASH_TYPE_IPV4          0x1
+#define ALX_RSS_HASH_TYPE_IPV4_TCP      0x2
+#define ALX_RSS_HASH_TYPE_IPV6          0x4
+#define ALX_RSS_HASH_TYPE_IPV6_TCP      0x8
+#define ALX_RSS_HASH_TYPE_ALL           (ALX_RSS_HASH_TYPE_IPV4 | \
+                                         ALX_RSS_HASH_TYPE_IPV4_TCP | \
+                                         ALX_RSS_HASH_TYPE_IPV6 | \
+                                         ALX_RSS_HASH_TYPE_IPV6_TCP)
+#define ALX_DEF_RXBUF_SIZE      1536
+#define ALX_MAX_JUMBO_PKT_SIZE  (9*1024)
+#define ALX_MAX_TSO_PKT_SIZE    (7*1024)
+#define ALX_MAX_FRAME_SIZE      ALX_MAX_JUMBO_PKT_SIZE
+#define ALX_MIN_FRAME_SIZE      68
+#define ALX_RAW_MTU(_mtu)       (_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
+
+#define ALX_MAX_RX_QUEUES       8
+#define ALX_MAX_TX_QUEUES       4
+#define ALX_MAX_HANDLED_INTRS   5
+
+#define ALX_ISR_MISC            (ALX_ISR_PCIE_LNKDOWN | \
+                                 ALX_ISR_DMAW | \
+                                 ALX_ISR_DMAR | \
+                                 ALX_ISR_SMB | \
+                                 ALX_ISR_MANU | \
+                                 ALX_ISR_TIMER)
+
+#define ALX_ISR_FATAL           (ALX_ISR_PCIE_LNKDOWN | \
+                                 ALX_ISR_DMAW | ALX_ISR_DMAR)
+
+#define ALX_ISR_ALERT           (ALX_ISR_RXF_OV | \
+                                 ALX_ISR_TXF_UR | \
+                                 ALX_ISR_RFD_UR)
+
+#define ALX_ISR_ALL_QUEUES      (ALX_ISR_TX_Q0 | \
+                                 ALX_ISR_TX_Q1 | \
+                                 ALX_ISR_TX_Q2 | \
+                                 ALX_ISR_TX_Q3 | \
+                                 ALX_ISR_RX_Q0 | \
+                                 ALX_ISR_RX_Q1 | \
+                                 ALX_ISR_RX_Q2 | \
+                                 ALX_ISR_RX_Q3 | \
+                                 ALX_ISR_RX_Q4 | \
+                                 ALX_ISR_RX_Q5 | \
+                                 ALX_ISR_RX_Q6 | \
+                                 ALX_ISR_RX_Q7)
+
+/* maximum interrupt vectors for msix */
+#define ALX_MAX_MSIX_INTRS      16
+
+#define ALX_GET_FIELD(_data, _field)                                    \
+        (((_data) >> _field ## _SHIFT) & _field ## _MASK)
+
+#define ALX_SET_FIELD(_data, _field, _value)    do {                    \
+                (_data) &= ~(_field ## _MASK << _field ## _SHIFT);      \
+                (_data) |= ((_value) & _field ## _MASK) << _field ## _SHIFT;\
+        } while (0)
+
+struct alx_hw {
+        struct pci_dev *pdev;
+        u8 __iomem *hw_addr;
+
+        /* current & permanent mac addr */
+        u8 mac_addr[ETH_ALEN];
+        u8 perm_addr[ETH_ALEN];
+
+        u16 mtu;
+        u16 imt;
+        u8 dma_chnl;
+        u8 max_dma_chnl;
+        /* tpd threshold to trig INT */
+        u32 ith_tpd;
+        u32 rx_ctrl;
+        u32 mc_hash[2];
+
+        u32 smb_timer;
+        /* SPEED_* + DUPLEX_*, SPEED_UNKNOWN if link is down */
+        int link_speed;
+
+        /* auto-neg advertisement or force mode config */
+        u32 adv_cfg;
+        u8 flowctrl;
+
+        u32 sleep_ctrl;
+
+        spinlock_t mdio_lock;
+        struct mdio_if_info mdio;
+        u16 phy_id[2];
+
+        /* PHY link patch flag */
+        bool lnk_patch;
+};
+
+static inline int alx_hw_revision(struct alx_hw *hw)
+{
+        return hw->pdev->revision >> ALX_PCI_REVID_SHIFT;
+}
+
+static inline bool alx_hw_with_cr(struct alx_hw *hw)
+{
+        return hw->pdev->revision & 1;
+}
+
+static inline bool alx_hw_giga(struct alx_hw *hw)
+{
+        return hw->pdev->device & 1;
+}
+
+static inline void alx_write_mem8(struct alx_hw *hw, u32 reg, u8 val)
+{
+        writeb(val, hw->hw_addr + reg);
+}
+
+static inline void alx_write_mem16(struct alx_hw *hw, u32 reg, u16 val)
+{
+        writew(val, hw->hw_addr + reg);
+}
+
+static inline u16 alx_read_mem16(struct alx_hw *hw, u32 reg)
+{
+        return readw(hw->hw_addr + reg);
+}
+
+static inline void alx_write_mem32(struct alx_hw *hw, u32 reg, u32 val)
+{
+        writel(val, hw->hw_addr + reg);
+}
+
+static inline u32 alx_read_mem32(struct alx_hw *hw, u32 reg)
+{
+        return readl(hw->hw_addr + reg);
+}
+
+static inline void alx_post_write(struct alx_hw *hw)
+{
+        readl(hw->hw_addr);
+}
+
+int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr);
+void alx_reset_phy(struct alx_hw *hw);
+void alx_reset_pcie(struct alx_hw *hw);
+void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en);
+int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl);
+void alx_post_phy_link(struct alx_hw *hw);
+int alx_pre_suspend(struct alx_hw *hw, int speed);
+int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data);
+int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data);
+int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata);
+int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data);
+int alx_get_phy_link(struct alx_hw *hw, int *speed);
+int alx_clear_phy_intr(struct alx_hw *hw);
+int alx_config_wol(struct alx_hw *hw);
+void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc);
+void alx_start_mac(struct alx_hw *hw);
+int alx_reset_mac(struct alx_hw *hw);
+void alx_set_macaddr(struct alx_hw *hw, const u8 *addr);
+bool alx_phy_configured(struct alx_hw *hw);
+void alx_configure_basic(struct alx_hw *hw);
+void alx_disable_rss(struct alx_hw *hw);
+int alx_select_powersaving_speed(struct alx_hw *hw, int *speed);
+bool alx_get_phy_info(struct alx_hw *hw);
+
+#endif
diff --git a/drivers/net/ethernet/atheros/alx/main.c b/drivers/net/ethernet/atheros/alx/main.c
new file mode 100644
index 000000000000..418de8b13165
--- /dev/null
+++ b/drivers/net/ethernet/atheros/alx/main.c
@@ -0,0 +1,1625 @@
+/*
+ * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
+ *
+ *  This file is free software: you may copy, redistribute and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation, either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  This file is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/ip.h>
+#include <linux/ipv6.h>
+#include <linux/if_vlan.h>
+#include <linux/mdio.h>
+#include <linux/aer.h>
+#include <linux/bitops.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <net/ip6_checksum.h>
+#include <linux/crc32.h>
+#include "alx.h"
+#include "hw.h"
+#include "reg.h"
+
+const char alx_drv_name[] = "alx";
+
+
+static void alx_free_txbuf(struct alx_priv *alx, int entry)
+{
+        struct alx_buffer *txb = &alx->txq.bufs[entry];
+
+        if (dma_unmap_len(txb, size)) {
+                dma_unmap_single(&alx->hw.pdev->dev,
+                                 dma_unmap_addr(txb, dma),
+                                 dma_unmap_len(txb, size),
+                                 DMA_TO_DEVICE);
+                dma_unmap_len_set(txb, size, 0);
+        }
+
+        if (txb->skb) {
+                dev_kfree_skb_any(txb->skb);
+                txb->skb = NULL;
+        }
+}
+
+static int alx_refill_rx_ring(struct alx_priv *alx, gfp_t gfp)
+{
+        struct alx_rx_queue *rxq = &alx->rxq;
+        struct sk_buff *skb;
+        struct alx_buffer *cur_buf;
+        dma_addr_t dma;
+        u16 cur, next, count = 0;
+
+        next = cur = rxq->write_idx;
+        if (++next == alx->rx_ringsz)
+                next = 0;
+        cur_buf = &rxq->bufs[cur];
+
+        while (!cur_buf->skb && next != rxq->read_idx) {
+                struct alx_rfd *rfd = &rxq->rfd[cur];
+
+                skb = __netdev_alloc_skb(alx->dev, alx->rxbuf_size, gfp);
+                if (!skb)
+                        break;
+                dma = dma_map_single(&alx->hw.pdev->dev,
+                                     skb->data, alx->rxbuf_size,
+                                     DMA_FROM_DEVICE);
+                if (dma_mapping_error(&alx->hw.pdev->dev, dma)) {
+                        dev_kfree_skb(skb);
+                        break;
+                }
+
+                /* Unfortunately, RX descriptor buffers must be 4-byte
+                 * aligned, so we can't use IP alignment.
+                 */
+                if (WARN_ON(dma & 3)) {
+                        dev_kfree_skb(skb);
+                        break;
+                }
+
+                cur_buf->skb = skb;
+                dma_unmap_len_set(cur_buf, size, alx->rxbuf_size);
+                dma_unmap_addr_set(cur_buf, dma, dma);
+                rfd->addr = cpu_to_le64(dma);
+
+                cur = next;
+                if (++next == alx->rx_ringsz)
+                        next = 0;
+                cur_buf = &rxq->bufs[cur];
+                count++;
+        }
+
+        if (count) {
+                /* flush all updates before updating hardware */
+                wmb();
+                rxq->write_idx = cur;
+                alx_write_mem16(&alx->hw, ALX_RFD_PIDX, cur);
+        }
+
+        return count;
+}
+
+static inline int alx_tpd_avail(struct alx_priv *alx)
+{
+        struct alx_tx_queue *txq = &alx->txq;
+
+        if (txq->write_idx >= txq->read_idx)
+                return alx->tx_ringsz + txq->read_idx - txq->write_idx - 1;
+        return txq->read_idx - txq->write_idx - 1;
+}
+
+static bool alx_clean_tx_irq(struct alx_priv *alx)
+{
+        struct alx_tx_queue *txq = &alx->txq;
+        u16 hw_read_idx, sw_read_idx;
+        unsigned int total_bytes = 0, total_packets = 0;
+        int budget = ALX_DEFAULT_TX_WORK;
+
+        sw_read_idx = txq->read_idx;
+        hw_read_idx = alx_read_mem16(&alx->hw, ALX_TPD_PRI0_CIDX);
+
+        if (sw_read_idx != hw_read_idx) {
+                while (sw_read_idx != hw_read_idx && budget > 0) {
+                        struct sk_buff *skb;
+
+                        skb = txq->bufs[sw_read_idx].skb;
+                        if (skb) {
+                                total_bytes += skb->len;
+                                total_packets++;
+                                budget--;
+                        }
+
+                        alx_free_txbuf(alx, sw_read_idx);
+
+                        if (++sw_read_idx == alx->tx_ringsz)
+                                sw_read_idx = 0;
+                }
+                txq->read_idx = sw_read_idx;
+
+                netdev_completed_queue(alx->dev, total_packets, total_bytes);
+        }
+
+        if (netif_queue_stopped(alx->dev) && netif_carrier_ok(alx->dev) &&
+            alx_tpd_avail(alx) > alx->tx_ringsz/4)
+                netif_wake_queue(alx->dev);
+
+        return sw_read_idx == hw_read_idx;
+}
+
+static void alx_schedule_link_check(struct alx_priv *alx)
+{
+        schedule_work(&alx->link_check_wk);
+}
+
+static void alx_schedule_reset(struct alx_priv *alx)
+{
+        schedule_work(&alx->reset_wk);
+}
+
+static bool alx_clean_rx_irq(struct alx_priv *alx, int budget)
+{
+        struct alx_rx_queue *rxq = &alx->rxq;
+        struct alx_rrd *rrd;
+        struct alx_buffer *rxb;
+        struct sk_buff *skb;
+        u16 length, rfd_cleaned = 0;
+
+        while (budget > 0) {
+                rrd = &rxq->rrd[rxq->rrd_read_idx];
+                if (!(rrd->word3 & cpu_to_le32(1 << RRD_UPDATED_SHIFT)))
+                        break;
+                rrd->word3 &= ~cpu_to_le32(1 << RRD_UPDATED_SHIFT);
+
+                if (ALX_GET_FIELD(le32_to_cpu(rrd->word0),
+                                  RRD_SI) != rxq->read_idx ||
+                    ALX_GET_FIELD(le32_to_cpu(rrd->word0),
+                                  RRD_NOR) != 1) {
+                        alx_schedule_reset(alx);
+                        return 0;
+                }
+
+                rxb = &rxq->bufs[rxq->read_idx];
+                dma_unmap_single(&alx->hw.pdev->dev,
+                                 dma_unmap_addr(rxb, dma),
+                                 dma_unmap_len(rxb, size),
+                                 DMA_FROM_DEVICE);
+                dma_unmap_len_set(rxb, size, 0);
+                skb = rxb->skb;
+                rxb->skb = NULL;
+
+                if (rrd->word3 & cpu_to_le32(1 << RRD_ERR_RES_SHIFT) ||
+                    rrd->word3 & cpu_to_le32(1 << RRD_ERR_LEN_SHIFT)) {
+                        rrd->word3 = 0;
+                        dev_kfree_skb_any(skb);
+                        goto next_pkt;
+                }
+
+                length = ALX_GET_FIELD(le32_to_cpu(rrd->word3),
+                                       RRD_PKTLEN) - ETH_FCS_LEN;
+                skb_put(skb, length);
+                skb->protocol = eth_type_trans(skb, alx->dev);
+
+                skb_checksum_none_assert(skb);
+                if (alx->dev->features & NETIF_F_RXCSUM &&
+                    !(rrd->word3 & (cpu_to_le32(1 << RRD_ERR_L4_SHIFT) |
+                                    cpu_to_le32(1 << RRD_ERR_IPV4_SHIFT)))) {
+                        switch (ALX_GET_FIELD(le32_to_cpu(rrd->word2),
+                                              RRD_PID)) {
+                        case RRD_PID_IPV6UDP:
+                        case RRD_PID_IPV4UDP:
+                        case RRD_PID_IPV4TCP:
+                        case RRD_PID_IPV6TCP:
+                                skb->ip_summed = CHECKSUM_UNNECESSARY;
+                                break;
+                        }
+                }
+
+                napi_gro_receive(&alx->napi, skb);
+                budget--;
+
+next_pkt:
+                if (++rxq->read_idx == alx->rx_ringsz)
+                        rxq->read_idx = 0;
+                if (++rxq->rrd_read_idx == alx->rx_ringsz)
+                        rxq->rrd_read_idx = 0;
+
+                if (++rfd_cleaned > ALX_RX_ALLOC_THRESH)
+                        rfd_cleaned -= alx_refill_rx_ring(alx, GFP_ATOMIC);
+        }
+
+        if (rfd_cleaned)
+                alx_refill_rx_ring(alx, GFP_ATOMIC);
+
+        return budget > 0;
+}
+
+static int alx_poll(struct napi_struct *napi, int budget)
+{
+        struct alx_priv *alx = container_of(napi, struct alx_priv, napi);
+        struct alx_hw *hw = &alx->hw;
+        bool complete = true;
+        unsigned long flags;
+
+        complete = alx_clean_tx_irq(alx) &&
+                   alx_clean_rx_irq(alx, budget);
+
+        if (!complete)
+                return 1;
+
+        napi_complete(&alx->napi);
+
+        /* enable interrupt */
+        spin_lock_irqsave(&alx->irq_lock, flags);
+        alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
+        alx_write_mem32(hw, ALX_IMR, alx->int_mask);
+        spin_unlock_irqrestore(&alx->irq_lock, flags);
+
+        alx_post_write(hw);
+
+        return 0;
+}
+
+static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr)
+{
+        struct alx_hw *hw = &alx->hw;
+        bool write_int_mask = false;
+
+        spin_lock(&alx->irq_lock);
+
+        /* ACK interrupt */
+        alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS);
+        intr &= alx->int_mask;
+
+        if (intr & ALX_ISR_FATAL) {
+                netif_warn(alx, hw, alx->dev,
+                           "fatal interrupt 0x%x, resetting\n", intr);
+                alx_schedule_reset(alx);
+                goto out;
+        }
+
+        if (intr & ALX_ISR_ALERT)
+                netdev_warn(alx->dev, "alert interrupt: 0x%x\n", intr);
+
+        if (intr & ALX_ISR_PHY) {
+                /* suppress PHY interrupt, because the source
+                 * is from PHY internal. only the internal status
+                 * is cleared, the interrupt status could be cleared.
+                 */
+                alx->int_mask &= ~ALX_ISR_PHY;
+                write_int_mask = true;
+                alx_schedule_link_check(alx);
+        }
+
+        if (intr & (ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0)) {
+                napi_schedule(&alx->napi);
+                /* mask rx/tx interrupt, enable them when napi complete */
+                alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
+                write_int_mask = true;
+        }
+
+        if (write_int_mask)
+                alx_write_mem32(hw, ALX_IMR, alx->int_mask);
+
+        alx_write_mem32(hw, ALX_ISR, 0);
+
+ out:
+        spin_unlock(&alx->irq_lock);
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t alx_intr_msi(int irq, void *data)
+{
+        struct alx_priv *alx = data;
+
+        return alx_intr_handle(alx, alx_read_mem32(&alx->hw, ALX_ISR));
+}
+
+static irqreturn_t alx_intr_legacy(int irq, void *data)
+{
+        struct alx_priv *alx = data;
+        struct alx_hw *hw = &alx->hw;
+        u32 intr;
+
+        intr = alx_read_mem32(hw, ALX_ISR);
+
+        if (intr & ALX_ISR_DIS || !(intr & alx->int_mask))
+                return IRQ_NONE;
+
+        return alx_intr_handle(alx, intr);
+}
+
+static void alx_init_ring_ptrs(struct alx_priv *alx)
+{
+        struct alx_hw *hw = &alx->hw;
+        u32 addr_hi = ((u64)alx->descmem.dma) >> 32;
+
+        alx->rxq.read_idx = 0;
+        alx->rxq.write_idx = 0;
+        alx->rxq.rrd_read_idx = 0;
+        alx_write_mem32(hw, ALX_RX_BASE_ADDR_HI, addr_hi);
+        alx_write_mem32(hw, ALX_RRD_ADDR_LO, alx->rxq.rrd_dma);
+        alx_write_mem32(hw, ALX_RRD_RING_SZ, alx->rx_ringsz);
+        alx_write_mem32(hw, ALX_RFD_ADDR_LO, alx->rxq.rfd_dma);
+        alx_write_mem32(hw, ALX_RFD_RING_SZ, alx->rx_ringsz);
+        alx_write_mem32(hw, ALX_RFD_BUF_SZ, alx->rxbuf_size);
+
+        alx->txq.read_idx = 0;
+        alx->txq.write_idx = 0;
+        alx_write_mem32(hw, ALX_TX_BASE_ADDR_HI, addr_hi);
+        alx_write_mem32(hw, ALX_TPD_PRI0_ADDR_LO, alx->txq.tpd_dma);
+        alx_write_mem32(hw, ALX_TPD_RING_SZ, alx->tx_ringsz);
+
+        /* load these pointers into the chip */
+        alx_write_mem32(hw, ALX_SRAM9, ALX_SRAM_LOAD_PTR);
+}
+
+static void alx_free_txring_buf(struct alx_priv *alx)
+{
+        struct alx_tx_queue *txq = &alx->txq;
+        int i;
+
+        if (!txq->bufs)
+                return;
+
+        for (i = 0; i < alx->tx_ringsz; i++)
+                alx_free_txbuf(alx, i);
+
+        memset(txq->bufs, 0, alx->tx_ringsz * sizeof(struct alx_buffer));
+        memset(txq->tpd, 0, alx->tx_ringsz * sizeof(struct alx_txd));
+        txq->write_idx = 0;
+        txq->read_idx = 0;
+
+        netdev_reset_queue(alx->dev);
+}
+
+static void alx_free_rxring_buf(struct alx_priv *alx)
+{
+        struct alx_rx_queue *rxq = &alx->rxq;
+        struct alx_buffer *cur_buf;
+        u16 i;
+
+        if (rxq == NULL)
+                return;
+
+        for (i = 0; i < alx->rx_ringsz; i++) {
+                cur_buf = rxq->bufs + i;
+                if (cur_buf->skb) {
+                        dma_unmap_single(&alx->hw.pdev->dev,
+                                         dma_unmap_addr(cur_buf, dma),
+                                         dma_unmap_len(cur_buf, size),
+                                         DMA_FROM_DEVICE);
+                        dev_kfree_skb(cur_buf->skb);
+                        cur_buf->skb = NULL;
+                        dma_unmap_len_set(cur_buf, size, 0);
+                        dma_unmap_addr_set(cur_buf, dma, 0);
+                }
+        }
+
+        rxq->write_idx = 0;
+        rxq->read_idx = 0;
+        rxq->rrd_read_idx = 0;
+}
+
+static void alx_free_buffers(struct alx_priv *alx)
+{
+        alx_free_txring_buf(alx);
+        alx_free_rxring_buf(alx);
+}
+
+static int alx_reinit_rings(struct alx_priv *alx)
+{
+        alx_free_buffers(alx);
+
+        alx_init_ring_ptrs(alx);
+
+        if (!alx_refill_rx_ring(alx, GFP_KERNEL))
+                return -ENOMEM;
+
+        return 0;
+}
+
+static void alx_add_mc_addr(struct alx_hw *hw, const u8 *addr, u32 *mc_hash)
+{
+        u32 crc32, bit, reg;
+
+        crc32 = ether_crc(ETH_ALEN, addr);
+        reg = (crc32 >> 31) & 0x1;
+        bit = (crc32 >> 26) & 0x1F;
+
+        mc_hash[reg] |= BIT(bit);
+}
+
+static void __alx_set_rx_mode(struct net_device *netdev)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+        struct alx_hw *hw = &alx->hw;
+        struct netdev_hw_addr *ha;
+        u32 mc_hash[2] = {};
+
+        if (!(netdev->flags & IFF_ALLMULTI)) {
+                netdev_for_each_mc_addr(ha, netdev)
+                        alx_add_mc_addr(hw, ha->addr, mc_hash);
+
+                alx_write_mem32(hw, ALX_HASH_TBL0, mc_hash[0]);
+                alx_write_mem32(hw, ALX_HASH_TBL1, mc_hash[1]);
+        }
+
+        hw->rx_ctrl &= ~(ALX_MAC_CTRL_MULTIALL_EN | ALX_MAC_CTRL_PROMISC_EN);
+        if (netdev->flags & IFF_PROMISC)
+                hw->rx_ctrl |= ALX_MAC_CTRL_PROMISC_EN;
+        if (netdev->flags & IFF_ALLMULTI)
+                hw->rx_ctrl |= ALX_MAC_CTRL_MULTIALL_EN;
+
+        alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
+}
+
+static void alx_set_rx_mode(struct net_device *netdev)
+{
+        __alx_set_rx_mode(netdev);
+}
+
+static int alx_set_mac_address(struct net_device *netdev, void *data)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+        struct alx_hw *hw = &alx->hw;
+        struct sockaddr *addr = data;
+
+        if (!is_valid_ether_addr(addr->sa_data))
+                return -EADDRNOTAVAIL;
+
+        if (netdev->addr_assign_type & NET_ADDR_RANDOM)
+                netdev->addr_assign_type ^= NET_ADDR_RANDOM;
+
+        memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
+        memcpy(hw->mac_addr, addr->sa_data, netdev->addr_len);
+        alx_set_macaddr(hw, hw->mac_addr);
+
+        return 0;
+}
+
+static int alx_alloc_descriptors(struct alx_priv *alx)
+{
+        alx->txq.bufs = kcalloc(alx->tx_ringsz,
+                                sizeof(struct alx_buffer),
+                                GFP_KERNEL);
+        if (!alx->txq.bufs)
+                return -ENOMEM;
+
+        alx->rxq.bufs = kcalloc(alx->rx_ringsz,
+                                sizeof(struct alx_buffer),
+                                GFP_KERNEL);
+        if (!alx->rxq.bufs)
+                goto out_free;
+
+        /* physical tx/rx ring descriptors
+         *
+         * Allocate them as a single chunk because they must not cross a
+         * 4G boundary (hardware has a single register for high 32 bits
+         * of addresses only)
+         */
+        alx->descmem.size = sizeof(struct alx_txd) * alx->tx_ringsz +
+                            sizeof(struct alx_rrd) * alx->rx_ringsz +
+                            sizeof(struct alx_rfd) * alx->rx_ringsz;
+        alx->descmem.virt = dma_zalloc_coherent(&alx->hw.pdev->dev,
+                                                alx->descmem.size,
+                                                &alx->descmem.dma,
+                                                GFP_KERNEL);
+        if (!alx->descmem.virt)
+                goto out_free;
+
+        alx->txq.tpd = (void *)alx->descmem.virt;
+        alx->txq.tpd_dma = alx->descmem.dma;
+
+        /* alignment requirement for next block */
+        BUILD_BUG_ON(sizeof(struct alx_txd) % 8);
+
+        alx->rxq.rrd =
+                (void *)((u8 *)alx->descmem.virt +
+                         sizeof(struct alx_txd) * alx->tx_ringsz);
+        alx->rxq.rrd_dma = alx->descmem.dma +
+                           sizeof(struct alx_txd) * alx->tx_ringsz;
+
+        /* alignment requirement for next block */
+        BUILD_BUG_ON(sizeof(struct alx_rrd) % 8);
+
+        alx->rxq.rfd =
+                (void *)((u8 *)alx->descmem.virt +
+                         sizeof(struct alx_txd) * alx->tx_ringsz +
+                         sizeof(struct alx_rrd) * alx->rx_ringsz);
+        alx->rxq.rfd_dma = alx->descmem.dma +
+                           sizeof(struct alx_txd) * alx->tx_ringsz +
+                           sizeof(struct alx_rrd) * alx->rx_ringsz;
+
+        return 0;
+out_free:
+        kfree(alx->txq.bufs);
+        kfree(alx->rxq.bufs);
+        return -ENOMEM;
+}
+
+static int alx_alloc_rings(struct alx_priv *alx)
+{
+        int err;
+
+        err = alx_alloc_descriptors(alx);
+        if (err)
+                return err;
+
+        alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
+        alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
+        alx->tx_ringsz = alx->tx_ringsz;
+
+        netif_napi_add(alx->dev, &alx->napi, alx_poll, 64);
+
+        alx_reinit_rings(alx);
+        return 0;
+}
+
+static void alx_free_rings(struct alx_priv *alx)
+{
+        netif_napi_del(&alx->napi);
+        alx_free_buffers(alx);
+
+        kfree(alx->txq.bufs);
+        kfree(alx->rxq.bufs);
+
+        dma_free_coherent(&alx->hw.pdev->dev,
+                          alx->descmem.size,
+                          alx->descmem.virt,
+                          alx->descmem.dma);
+}
+
+static void alx_config_vector_mapping(struct alx_priv *alx)
+{
+        struct alx_hw *hw = &alx->hw;
+
+        alx_write_mem32(hw, ALX_MSI_MAP_TBL1, 0);
+        alx_write_mem32(hw, ALX_MSI_MAP_TBL2, 0);
+        alx_write_mem32(hw, ALX_MSI_ID_MAP, 0);
+}
+
+static void alx_irq_enable(struct alx_priv *alx)
+{
+        struct alx_hw *hw = &alx->hw;
+
+        /* level-1 interrupt switch */
+        alx_write_mem32(hw, ALX_ISR, 0);
+        alx_write_mem32(hw, ALX_IMR, alx->int_mask);
+        alx_post_write(hw);
+}
+
+static void alx_irq_disable(struct alx_priv *alx)
+{
+        struct alx_hw *hw = &alx->hw;
+
+        alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS);
+        alx_write_mem32(hw, ALX_IMR, 0);
+        alx_post_write(hw);
+
+        synchronize_irq(alx->hw.pdev->irq);
+}
+
+static int alx_request_irq(struct alx_priv *alx)
+{
+        struct pci_dev *pdev = alx->hw.pdev;
+        struct alx_hw *hw = &alx->hw;
+        int err;
+        u32 msi_ctrl;
+
+        msi_ctrl = (hw->imt >> 1) << ALX_MSI_RETRANS_TM_SHIFT;
+
+        if (!pci_enable_msi(alx->hw.pdev)) {
+                alx->msi = true;
+
+                alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER,
+                                msi_ctrl | ALX_MSI_MASK_SEL_LINE);
+                err = request_irq(pdev->irq, alx_intr_msi, 0,
+                                  alx->dev->name, alx);
+                if (!err)
+                        goto out;
+                /* fall back to legacy interrupt */
+                pci_disable_msi(alx->hw.pdev);
+        }
+
+        alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, 0);
+        err = request_irq(pdev->irq, alx_intr_legacy, IRQF_SHARED,
+                          alx->dev->name, alx);
+out:
+        if (!err)
+                alx_config_vector_mapping(alx);
+        return err;
+}
+
+static void alx_free_irq(struct alx_priv *alx)
+{
+        struct pci_dev *pdev = alx->hw.pdev;
+
+        free_irq(pdev->irq, alx);
+
+        if (alx->msi) {
+                pci_disable_msi(alx->hw.pdev);
+                alx->msi = false;
+        }
+}
+
+static int alx_identify_hw(struct alx_priv *alx)
+{
+        struct alx_hw *hw = &alx->hw;
+        int rev = alx_hw_revision(hw);
+
+        if (rev > ALX_REV_C0)
+                return -EINVAL;
+
+        hw->max_dma_chnl = rev >= ALX_REV_B0 ? 4 : 2;
+
+        return 0;
+}
+
+static int alx_init_sw(struct alx_priv *alx)
+{
+        struct pci_dev *pdev = alx->hw.pdev;
+        struct alx_hw *hw = &alx->hw;
+        int err;
+
+        err = alx_identify_hw(alx);
+        if (err) {
+                dev_err(&pdev->dev, "unrecognized chip, aborting\n");
+                return err;
+        }
+
+        alx->hw.lnk_patch =
+                pdev->device == ALX_DEV_ID_AR8161 &&
+                pdev->subsystem_vendor == PCI_VENDOR_ID_ATTANSIC &&
+                pdev->subsystem_device == 0x0091 &&
+                pdev->revision == 0;
+
+        hw->smb_timer = 400;
+        hw->mtu = alx->dev->mtu;
+        alx->rxbuf_size = ALIGN(ALX_RAW_MTU(hw->mtu), 8);
+        alx->tx_ringsz = 256;
+        alx->rx_ringsz = 512;
+        hw->sleep_ctrl = ALX_SLEEP_WOL_MAGIC | ALX_SLEEP_WOL_PHY;
+        hw->imt = 200;
+        alx->int_mask = ALX_ISR_MISC;
+        hw->dma_chnl = hw->max_dma_chnl;
+        hw->ith_tpd = alx->tx_ringsz / 3;
+        hw->link_speed = SPEED_UNKNOWN;
+        hw->adv_cfg = ADVERTISED_Autoneg |
+                      ADVERTISED_10baseT_Half |
+                      ADVERTISED_10baseT_Full |
+                      ADVERTISED_100baseT_Full |
+                      ADVERTISED_100baseT_Half |
+                      ADVERTISED_1000baseT_Full;
+        hw->flowctrl = ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX;
+
+        hw->rx_ctrl = ALX_MAC_CTRL_WOLSPED_SWEN |
+                      ALX_MAC_CTRL_MHASH_ALG_HI5B |
+                      ALX_MAC_CTRL_BRD_EN |
+                      ALX_MAC_CTRL_PCRCE |
+                      ALX_MAC_CTRL_CRCE |
+                      ALX_MAC_CTRL_RXFC_EN |
+                      ALX_MAC_CTRL_TXFC_EN |
+                      7 << ALX_MAC_CTRL_PRMBLEN_SHIFT;
+
+        return err;
+}
+
+
+static netdev_features_t alx_fix_features(struct net_device *netdev,
+                                          netdev_features_t features)
+{
+        if (netdev->mtu > ALX_MAX_TSO_PKT_SIZE)
+                features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
+
+        return features;
+}
+
+static void alx_netif_stop(struct alx_priv *alx)
+{
+        alx->dev->trans_start = jiffies;
+        if (netif_carrier_ok(alx->dev)) {
+                netif_carrier_off(alx->dev);
+                netif_tx_disable(alx->dev);
+                napi_disable(&alx->napi);
+        }
+}
+
+static void alx_halt(struct alx_priv *alx)
+{
+        struct alx_hw *hw = &alx->hw;
+
+        alx_netif_stop(alx);
+        hw->link_speed = SPEED_UNKNOWN;
+
+        alx_reset_mac(hw);
+
+        /* disable l0s/l1 */
+        alx_enable_aspm(hw, false, false);
+        alx_irq_disable(alx);
+        alx_free_buffers(alx);
+}
+
+static void alx_configure(struct alx_priv *alx)
+{
+        struct alx_hw *hw = &alx->hw;
+
+        alx_configure_basic(hw);
+        alx_disable_rss(hw);
+        __alx_set_rx_mode(alx->dev);
+
+        alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
+}
+
+static void alx_activate(struct alx_priv *alx)
+{
+        /* hardware setting lost, restore it */
+        alx_reinit_rings(alx);
+        alx_configure(alx);
+
+        /* clear old interrupts */
+        alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
+
+        alx_irq_enable(alx);
+
+        alx_schedule_link_check(alx);
+}
+
+static void alx_reinit(struct alx_priv *alx)
+{
+        ASSERT_RTNL();
+
+        alx_halt(alx);
+        alx_activate(alx);
+}
+
+static int alx_change_mtu(struct net_device *netdev, int mtu)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+        int max_frame = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
+
+        if ((max_frame < ALX_MIN_FRAME_SIZE) ||
+            (max_frame > ALX_MAX_FRAME_SIZE))
+                return -EINVAL;
+
+        if (netdev->mtu == mtu)
+                return 0;
+
+        netdev->mtu = mtu;
+        alx->hw.mtu = mtu;
+        alx->rxbuf_size = mtu > ALX_DEF_RXBUF_SIZE ?
+                           ALIGN(max_frame, 8) : ALX_DEF_RXBUF_SIZE;
+        netdev_update_features(netdev);
+        if (netif_running(netdev))
+                alx_reinit(alx);
+        return 0;
+}
+
+static void alx_netif_start(struct alx_priv *alx)
+{
+        netif_tx_wake_all_queues(alx->dev);
+        napi_enable(&alx->napi);
+        netif_carrier_on(alx->dev);
+}
+
+static int __alx_open(struct alx_priv *alx, bool resume)
+{
+        int err;
+
+        if (!resume)
+                netif_carrier_off(alx->dev);
+
+        err = alx_alloc_rings(alx);
+        if (err)
+                return err;
+
+        alx_configure(alx);
+
+        err = alx_request_irq(alx);
+        if (err)
+                goto out_free_rings;
+
+        /* clear old interrupts */
+        alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
+
+        alx_irq_enable(alx);
+
+        if (!resume)
+                netif_tx_start_all_queues(alx->dev);
+
+        alx_schedule_link_check(alx);
+        return 0;
+
+out_free_rings:
+        alx_free_rings(alx);
+        return err;
+}
+
+static void __alx_stop(struct alx_priv *alx)
+{
+        alx_halt(alx);
+        alx_free_irq(alx);
+        alx_free_rings(alx);
+}
+
+static const char *alx_speed_desc(u16 speed)
+{
+        switch (speed) {
+        case SPEED_1000 + DUPLEX_FULL:
+                return "1 Gbps Full";
+        case SPEED_100 + DUPLEX_FULL:
+                return "100 Mbps Full";
+        case SPEED_100 + DUPLEX_HALF:
+                return "100 Mbps Half";
+        case SPEED_10 + DUPLEX_FULL:
+                return "10 Mbps Full";
+        case SPEED_10 + DUPLEX_HALF:
+                return "10 Mbps Half";
+        default:
+                return "Unknown speed";
+        }
+}
+
+static void alx_check_link(struct alx_priv *alx)
+{
+        struct alx_hw *hw = &alx->hw;
+        unsigned long flags;
+        int speed, old_speed;
+        int err;
+
+        /* clear PHY internal interrupt status, otherwise the main
+         * interrupt status will be asserted forever
+         */
+        alx_clear_phy_intr(hw);
+
+        err = alx_get_phy_link(hw, &speed);
+        if (err < 0)
+                goto reset;
+
+        spin_lock_irqsave(&alx->irq_lock, flags);
+        alx->int_mask |= ALX_ISR_PHY;
+        alx_write_mem32(hw, ALX_IMR, alx->int_mask);
+        spin_unlock_irqrestore(&alx->irq_lock, flags);
+
+        old_speed = hw->link_speed;
+
+        if (old_speed == speed)
+                return;
+        hw->link_speed = speed;
+
+        if (speed != SPEED_UNKNOWN) {
+                netif_info(alx, link, alx->dev,
+                           "NIC Up: %s\n", alx_speed_desc(speed));
+                alx_post_phy_link(hw);
+                alx_enable_aspm(hw, true, true);
+                alx_start_mac(hw);
+
+                if (old_speed == SPEED_UNKNOWN)
+                        alx_netif_start(alx);
+        } else {
+                /* link is now down */
+                alx_netif_stop(alx);
+                netif_info(alx, link, alx->dev, "Link Down\n");
+                err = alx_reset_mac(hw);
+                if (err)
+                        goto reset;
+                alx_irq_disable(alx);
+
+                /* MAC reset causes all HW settings to be lost, restore all */
+                err = alx_reinit_rings(alx);
+                if (err)
+                        goto reset;
+                alx_configure(alx);
+                alx_enable_aspm(hw, false, true);
+                alx_post_phy_link(hw);
+                alx_irq_enable(alx);
+        }
+
+        return;
+
+reset:
+        alx_schedule_reset(alx);
+}
+
+static int alx_open(struct net_device *netdev)
+{
+        return __alx_open(netdev_priv(netdev), false);
+}
+
+static int alx_stop(struct net_device *netdev)
+{
+        __alx_stop(netdev_priv(netdev));
+        return 0;
+}
+
+static int __alx_shutdown(struct pci_dev *pdev, bool *wol_en)
+{
+        struct alx_priv *alx = pci_get_drvdata(pdev);
+        struct net_device *netdev = alx->dev;
+        struct alx_hw *hw = &alx->hw;
+        int err, speed;
+
+        netif_device_detach(netdev);
+
+        if (netif_running(netdev))
+                __alx_stop(alx);
+
+#ifdef CONFIG_PM_SLEEP
+        err = pci_save_state(pdev);
+        if (err)
+                return err;
+#endif
+
+        err = alx_select_powersaving_speed(hw, &speed);
+        if (err)
+                return err;
+        err = alx_clear_phy_intr(hw);
+        if (err)
+                return err;
+        err = alx_pre_suspend(hw, speed);
+        if (err)
+                return err;
+        err = alx_config_wol(hw);
+        if (err)
+                return err;
+
+        *wol_en = false;
+        if (hw->sleep_ctrl & ALX_SLEEP_ACTIVE) {
+                netif_info(alx, wol, netdev,
+                           "wol: ctrl=%X, speed=%X\n",
+                           hw->sleep_ctrl, speed);
+                device_set_wakeup_enable(&pdev->dev, true);
+                *wol_en = true;
+        }
+
+        pci_disable_device(pdev);
+
+        return 0;
+}
+
+static void alx_shutdown(struct pci_dev *pdev)
+{
+        int err;
+        bool wol_en;
+
+        err = __alx_shutdown(pdev, &wol_en);
+        if (!err) {
+                pci_wake_from_d3(pdev, wol_en);
+                pci_set_power_state(pdev, PCI_D3hot);
+        } else {
+                dev_err(&pdev->dev, "shutdown fail %d\n", err);
+        }
+}
+
+static void alx_link_check(struct work_struct *work)
+{
+        struct alx_priv *alx;
+
+        alx = container_of(work, struct alx_priv, link_check_wk);
+
+        rtnl_lock();
+        alx_check_link(alx);
+        rtnl_unlock();
+}
+
+static void alx_reset(struct work_struct *work)
+{
+        struct alx_priv *alx = container_of(work, struct alx_priv, reset_wk);
+
+        rtnl_lock();
+        alx_reinit(alx);
+        rtnl_unlock();
+}
+
+static int alx_tx_csum(struct sk_buff *skb, struct alx_txd *first)
+{
+        u8 cso, css;
+
+        if (skb->ip_summed != CHECKSUM_PARTIAL)
+                return 0;
+
+        cso = skb_checksum_start_offset(skb);
+        if (cso & 1)
+                return -EINVAL;
+
+        css = cso + skb->csum_offset;
+        first->word1 |= cpu_to_le32((cso >> 1) << TPD_CXSUMSTART_SHIFT);
+        first->word1 |= cpu_to_le32((css >> 1) << TPD_CXSUMOFFSET_SHIFT);
+        first->word1 |= cpu_to_le32(1 << TPD_CXSUM_EN_SHIFT);
+
+        return 0;
+}
+
+static int alx_map_tx_skb(struct alx_priv *alx, struct sk_buff *skb)
+{
+        struct alx_tx_queue *txq = &alx->txq;
+        struct alx_txd *tpd, *first_tpd;
+        dma_addr_t dma;
+        int maplen, f, first_idx = txq->write_idx;
+
+        first_tpd = &txq->tpd[txq->write_idx];
+        tpd = first_tpd;
+
+        maplen = skb_headlen(skb);
+        dma = dma_map_single(&alx->hw.pdev->dev, skb->data, maplen,
+                             DMA_TO_DEVICE);
+        if (dma_mapping_error(&alx->hw.pdev->dev, dma))
+                goto err_dma;
+
+        dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
+        dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
+
+        tpd->adrl.addr = cpu_to_le64(dma);
+        tpd->len = cpu_to_le16(maplen);
+
+        for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
+                struct skb_frag_struct *frag;
+
+                frag = &skb_shinfo(skb)->frags[f];
+
+                if (++txq->write_idx == alx->tx_ringsz)
+                        txq->write_idx = 0;
+                tpd = &txq->tpd[txq->write_idx];
+
+                tpd->word1 = first_tpd->word1;
+
+                maplen = skb_frag_size(frag);
+                dma = skb_frag_dma_map(&alx->hw.pdev->dev, frag, 0,
+                                       maplen, DMA_TO_DEVICE);
+                if (dma_mapping_error(&alx->hw.pdev->dev, dma))
+                        goto err_dma;
+                dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
+                dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
+
+                tpd->adrl.addr = cpu_to_le64(dma);
+                tpd->len = cpu_to_le16(maplen);
+        }
+
+        /* last TPD, set EOP flag and store skb */
+        tpd->word1 |= cpu_to_le32(1 << TPD_EOP_SHIFT);
+        txq->bufs[txq->write_idx].skb = skb;
+
+        if (++txq->write_idx == alx->tx_ringsz)
+                txq->write_idx = 0;
+
+        return 0;
+
+err_dma:
+        f = first_idx;
+        while (f != txq->write_idx) {
+                alx_free_txbuf(alx, f);
+                if (++f == alx->tx_ringsz)
+                        f = 0;
+        }
+        return -ENOMEM;
+}
+
+static netdev_tx_t alx_start_xmit(struct sk_buff *skb,
+                                  struct net_device *netdev)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+        struct alx_tx_queue *txq = &alx->txq;
+        struct alx_txd *first;
+        int tpdreq = skb_shinfo(skb)->nr_frags + 1;
+
+        if (alx_tpd_avail(alx) < tpdreq) {
+                netif_stop_queue(alx->dev);
+                goto drop;
+        }
+
+        first = &txq->tpd[txq->write_idx];
+        memset(first, 0, sizeof(*first));
+
+        if (alx_tx_csum(skb, first))
+                goto drop;
+
+        if (alx_map_tx_skb(alx, skb) < 0)
+                goto drop;
+
+        netdev_sent_queue(alx->dev, skb->len);
+
+        /* flush updates before updating hardware */
+        wmb();
+        alx_write_mem16(&alx->hw, ALX_TPD_PRI0_PIDX, txq->write_idx);
+
+        if (alx_tpd_avail(alx) < alx->tx_ringsz/8)
+                netif_stop_queue(alx->dev);
+
+        return NETDEV_TX_OK;
+
+drop:
+        dev_kfree_skb(skb);
+        return NETDEV_TX_OK;
+}
+
+static void alx_tx_timeout(struct net_device *dev)
+{
+        struct alx_priv *alx = netdev_priv(dev);
+
+        alx_schedule_reset(alx);
+}
+
+static int alx_mdio_read(struct net_device *netdev,
+                         int prtad, int devad, u16 addr)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+        struct alx_hw *hw = &alx->hw;
+        u16 val;
+        int err;
+
+        if (prtad != hw->mdio.prtad)
+                return -EINVAL;
+
+        if (devad == MDIO_DEVAD_NONE)
+                err = alx_read_phy_reg(hw, addr, &val);
+        else
+                err = alx_read_phy_ext(hw, devad, addr, &val);
+
+        if (err)
+                return err;
+        return val;
+}
+
+static int alx_mdio_write(struct net_device *netdev,
+                          int prtad, int devad, u16 addr, u16 val)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+        struct alx_hw *hw = &alx->hw;
+
+        if (prtad != hw->mdio.prtad)
+                return -EINVAL;
+
+        if (devad == MDIO_DEVAD_NONE)
+                return alx_write_phy_reg(hw, addr, val);
+
+        return alx_write_phy_ext(hw, devad, addr, val);
+}
+
+static int alx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+
+        if (!netif_running(netdev))
+                return -EAGAIN;
+
+        return mdio_mii_ioctl(&alx->hw.mdio, if_mii(ifr), cmd);
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void alx_poll_controller(struct net_device *netdev)
+{
+        struct alx_priv *alx = netdev_priv(netdev);
+
+        if (alx->msi)
+                alx_intr_msi(0, alx);
+        else
+                alx_intr_legacy(0, alx);
+}
+#endif
+
+static const struct net_device_ops alx_netdev_ops = {
+        .ndo_open               = alx_open,
+        .ndo_stop               = alx_stop,
+        .ndo_start_xmit         = alx_start_xmit,
+        .ndo_set_rx_mode        = alx_set_rx_mode,
+        .ndo_validate_addr      = eth_validate_addr,
+        .ndo_set_mac_address    = alx_set_mac_address,
+        .ndo_change_mtu         = alx_change_mtu,
+        .ndo_do_ioctl           = alx_ioctl,
+        .ndo_tx_timeout         = alx_tx_timeout,
+        .ndo_fix_features       = alx_fix_features,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+        .ndo_poll_controller    = alx_poll_controller,
+#endif
+};
+
+static int alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+        struct net_device *netdev;
+        struct alx_priv *alx;
+        struct alx_hw *hw;
+        bool phy_configured;
+        int bars, pm_cap, err;
+
+        err = pci_enable_device_mem(pdev);
+        if (err)
+                return err;
+
+        /* The alx chip can DMA to 64-bit addresses, but it uses a single
+         * shared register for the high 32 bits, so only a single, aligned,
+         * 4 GB physical address range can be used for descriptors.
+         */
+        if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
+            !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
+                dev_dbg(&pdev->dev, "DMA to 64-BIT addresses\n");
+        } else {
+                err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+                if (err) {
+                        err = dma_set_coherent_mask(&pdev->dev,
+                                                    DMA_BIT_MASK(32));
+                        if (err) {
+                                dev_err(&pdev->dev,
+                                        "No usable DMA config, aborting\n");
+                                goto out_pci_disable;
+                        }
+                }
+        }
+
+        bars = pci_select_bars(pdev, IORESOURCE_MEM);
+        err = pci_request_selected_regions(pdev, bars, alx_drv_name);
+        if (err) {
+                dev_err(&pdev->dev,
+                        "pci_request_selected_regions failed(bars:%d)\n", bars);
+                goto out_pci_disable;
+        }
+
+        pci_enable_pcie_error_reporting(pdev);
+        pci_set_master(pdev);
+
+        pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
+        if (pm_cap == 0) {
+                dev_err(&pdev->dev,
+                        "Can't find power management capability, aborting\n");
+                err = -EIO;
+                goto out_pci_release;
+        }
+
+        err = pci_set_power_state(pdev, PCI_D0);
+        if (err)
+                goto out_pci_release;
+
+        netdev = alloc_etherdev(sizeof(*alx));
+        if (!netdev) {
+                err = -ENOMEM;
+                goto out_pci_release;
+        }
+
+        SET_NETDEV_DEV(netdev, &pdev->dev);
+        alx = netdev_priv(netdev);
+        alx->dev = netdev;
+        alx->hw.pdev = pdev;
+        alx->msg_enable = NETIF_MSG_LINK | NETIF_MSG_HW | NETIF_MSG_IFUP |
+                          NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | NETIF_MSG_WOL;
+        hw = &alx->hw;
+        pci_set_drvdata(pdev, alx);
+
+        hw->hw_addr = pci_ioremap_bar(pdev, 0);
+        if (!hw->hw_addr) {
+                dev_err(&pdev->dev, "cannot map device registers\n");
+                err = -EIO;
+                goto out_free_netdev;
+        }
+
+        netdev->netdev_ops = &alx_netdev_ops;
+        SET_ETHTOOL_OPS(netdev, &alx_ethtool_ops);
+        netdev->irq = pdev->irq;
+        netdev->watchdog_timeo = ALX_WATCHDOG_TIME;
+
+        if (ent->driver_data & ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG)
+                pdev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
+
+        err = alx_init_sw(alx);
+        if (err) {
+                dev_err(&pdev->dev, "net device private data init failed\n");
+                goto out_unmap;
+        }
+
+        alx_reset_pcie(hw);
+
+        phy_configured = alx_phy_configured(hw);
+
+        if (!phy_configured)
+                alx_reset_phy(hw);
+
+        err = alx_reset_mac(hw);
+        if (err) {
+                dev_err(&pdev->dev, "MAC Reset failed, error = %d\n", err);
+                goto out_unmap;
+        }
+
+        /* setup link to put it in a known good starting state */
+        if (!phy_configured) {
+                err = alx_setup_speed_duplex(hw, hw->adv_cfg, hw->flowctrl);
+                if (err) {
+                        dev_err(&pdev->dev,
+                                "failed to configure PHY speed/duplex (err=%d)\n",
+                                err);
+                        goto out_unmap;
+                }
+        }
+
+        netdev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
+
+        if (alx_get_perm_macaddr(hw, hw->perm_addr)) {
+                dev_warn(&pdev->dev,
+                         "Invalid permanent address programmed, using random one\n");
+                eth_hw_addr_random(netdev);
+                memcpy(hw->perm_addr, netdev->dev_addr, netdev->addr_len);
+        }
+
+        memcpy(hw->mac_addr, hw->perm_addr, ETH_ALEN);
+        memcpy(netdev->dev_addr, hw->mac_addr, ETH_ALEN);
+        memcpy(netdev->perm_addr, hw->perm_addr, ETH_ALEN);
+
+        hw->mdio.prtad = 0;
+        hw->mdio.mmds = 0;
+        hw->mdio.dev = netdev;
+        hw->mdio.mode_support = MDIO_SUPPORTS_C45 |
+                                MDIO_SUPPORTS_C22 |
+                                MDIO_EMULATE_C22;
+        hw->mdio.mdio_read = alx_mdio_read;
+        hw->mdio.mdio_write = alx_mdio_write;
+
+        if (!alx_get_phy_info(hw)) {
+                dev_err(&pdev->dev, "failed to identify PHY\n");
+                err = -EIO;
+                goto out_unmap;
+        }
+
+        INIT_WORK(&alx->link_check_wk, alx_link_check);
+        INIT_WORK(&alx->reset_wk, alx_reset);
+        spin_lock_init(&alx->hw.mdio_lock);
+        spin_lock_init(&alx->irq_lock);
+
+        netif_carrier_off(netdev);
+
+        err = register_netdev(netdev);
+        if (err) {
+                dev_err(&pdev->dev, "register netdevice failed\n");
+                goto out_unmap;
+        }
+
+        device_set_wakeup_enable(&pdev->dev, hw->sleep_ctrl);
+
+        netdev_info(netdev,
+                    "Qualcomm Atheros AR816x/AR817x Ethernet [%pM]\n",
+                    netdev->dev_addr);
+
+        return 0;
+
+out_unmap:
+        iounmap(hw->hw_addr);
+out_free_netdev:
+        free_netdev(netdev);
+out_pci_release:
+        pci_release_selected_regions(pdev, bars);
+out_pci_disable:
+        pci_disable_device(pdev);
+        return err;
+}
+
+static void alx_remove(struct pci_dev *pdev)
+{
+        struct alx_priv *alx = pci_get_drvdata(pdev);
+        struct alx_hw *hw = &alx->hw;
+
+        cancel_work_sync(&alx->link_check_wk);
+        cancel_work_sync(&alx->reset_wk);
+
+        /* restore permanent mac address */
+        alx_set_macaddr(hw, hw->perm_addr);
+
+        unregister_netdev(alx->dev);
+        iounmap(hw->hw_addr);
+        pci_release_selected_regions(pdev,
+                                     pci_select_bars(pdev, IORESOURCE_MEM));
+
+        pci_disable_pcie_error_reporting(pdev);
+        pci_disable_device(pdev);
+        pci_set_drvdata(pdev, NULL);
+
+        free_netdev(alx->dev);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int alx_suspend(struct device *dev)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+        int err;
+        bool wol_en;
+
+        err = __alx_shutdown(pdev, &wol_en);
+        if (err) {
+                dev_err(&pdev->dev, "shutdown fail in suspend %d\n", err);
+                return err;
+        }
+
+        if (wol_en) {
+                pci_prepare_to_sleep(pdev);
+        } else {
+                pci_wake_from_d3(pdev, false);
+                pci_set_power_state(pdev, PCI_D3hot);
+        }
+
+        return 0;
+}
+
+static int alx_resume(struct device *dev)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+        struct alx_priv *alx = pci_get_drvdata(pdev);
+        struct net_device *netdev = alx->dev;
+        struct alx_hw *hw = &alx->hw;
+        int err;
+
+        pci_set_power_state(pdev, PCI_D0);
+        pci_restore_state(pdev);
+        pci_save_state(pdev);
+
+        pci_enable_wake(pdev, PCI_D3hot, 0);
+        pci_enable_wake(pdev, PCI_D3cold, 0);
+
+        hw->link_speed = SPEED_UNKNOWN;
+        alx->int_mask = ALX_ISR_MISC;
+
+        alx_reset_pcie(hw);
+        alx_reset_phy(hw);
+
+        err = alx_reset_mac(hw);
+        if (err) {
+                netif_err(alx, hw, alx->dev,
+                          "resume:reset_mac fail %d\n", err);
+                return -EIO;
+        }
+
+        err = alx_setup_speed_duplex(hw, hw->adv_cfg, hw->flowctrl);
+        if (err) {
+                netif_err(alx, hw, alx->dev,
+                          "resume:setup_speed_duplex fail %d\n", err);
+                return -EIO;
+        }
+
+        if (netif_running(netdev)) {
+                err = __alx_open(alx, true);
+                if (err)
+                        return err;
+        }
+
+        netif_device_attach(netdev);
+
+        return err;
+}
+#endif
+
+static pci_ers_result_t alx_pci_error_detected(struct pci_dev *pdev,
+                                               pci_channel_state_t state)
+{
+        struct alx_priv *alx = pci_get_drvdata(pdev);
+        struct net_device *netdev = alx->dev;
+        pci_ers_result_t rc = PCI_ERS_RESULT_NEED_RESET;
+
+        dev_info(&pdev->dev, "pci error detected\n");
+
+        rtnl_lock();
+
+        if (netif_running(netdev)) {
+                netif_device_detach(netdev);
+                alx_halt(alx);
+        }
+
+        if (state == pci_channel_io_perm_failure)
+                rc = PCI_ERS_RESULT_DISCONNECT;
+        else
+                pci_disable_device(pdev);
+
+        rtnl_unlock();
+
+        return rc;
+}
+
+static pci_ers_result_t alx_pci_error_slot_reset(struct pci_dev *pdev)
+{
+        struct alx_priv *alx = pci_get_drvdata(pdev);
+        struct alx_hw *hw = &alx->hw;
+        pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
+
+        dev_info(&pdev->dev, "pci error slot reset\n");
+
+        rtnl_lock();
+
+        if (pci_enable_device(pdev)) {
+                dev_err(&pdev->dev, "Failed to re-enable PCI device after reset\n");
+                goto out;
+        }
+
+        pci_set_master(pdev);
+        pci_enable_wake(pdev, PCI_D3hot, 0);
+        pci_enable_wake(pdev, PCI_D3cold, 0);
+
+        alx_reset_pcie(hw);
+        if (!alx_reset_mac(hw))
+                rc = PCI_ERS_RESULT_RECOVERED;
+out:
+        pci_cleanup_aer_uncorrect_error_status(pdev);
+
+        rtnl_unlock();
+
+        return rc;
+}
+
+static void alx_pci_error_resume(struct pci_dev *pdev)
+{
+        struct alx_priv *alx = pci_get_drvdata(pdev);
+        struct net_device *netdev = alx->dev;
+
+        dev_info(&pdev->dev, "pci error resume\n");
+
+        rtnl_lock();
+
+        if (netif_running(netdev)) {
+                alx_activate(alx);
+                netif_device_attach(netdev);
+        }
+
+        rtnl_unlock();
+}
+
+static const struct pci_error_handlers alx_err_handlers = {
+        .error_detected = alx_pci_error_detected,
+        .slot_reset     = alx_pci_error_slot_reset,
+        .resume         = alx_pci_error_resume,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static SIMPLE_DEV_PM_OPS(alx_pm_ops, alx_suspend, alx_resume);
+#define ALX_PM_OPS      (&alx_pm_ops)
+#else
+#define ALX_PM_OPS      NULL
+#endif
+
+static DEFINE_PCI_DEVICE_TABLE(alx_pci_tbl) = {
+        { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8161),
+          .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
+        { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2200),
+          .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
+        { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8162),
+          .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
+        { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8171) },
+        { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8172) },
+        {}
+};
+
+static struct pci_driver alx_driver = {
+        .name        = alx_drv_name,
+        .id_table    = alx_pci_tbl,
+        .probe       = alx_probe,
+        .remove      = alx_remove,
+        .shutdown    = alx_shutdown,
+        .err_handler = &alx_err_handlers,
+        .driver.pm   = ALX_PM_OPS,
+};
+
+module_pci_driver(alx_driver);
+MODULE_DEVICE_TABLE(pci, alx_pci_tbl);
+MODULE_AUTHOR("Johannes Berg <johannes@sipsolutions.net>");
+MODULE_AUTHOR("Qualcomm Corporation, <nic-devel@qualcomm.com>");
+MODULE_DESCRIPTION(
+        "Qualcomm Atheros(R) AR816x/AR817x PCI-E Ethernet Network Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/atheros/alx/reg.h b/drivers/net/ethernet/atheros/alx/reg.h
new file mode 100644
index 000000000000..e4358c98bc4e
--- /dev/null
+++ b/drivers/net/ethernet/atheros/alx/reg.h
@@ -0,0 +1,810 @@
+/*
+ * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
+ *
+ *  This file is free software: you may copy, redistribute and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation, either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  This file is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef ALX_REG_H
+#define ALX_REG_H
+
+#define ALX_DEV_ID_AR8161                               0x1091
+#define ALX_DEV_ID_E2200                                0xe091
+#define ALX_DEV_ID_AR8162                               0x1090
+#define ALX_DEV_ID_AR8171                               0x10A1
+#define ALX_DEV_ID_AR8172                               0x10A0
+
+/* rev definition,
+ * bit(0): with xD support
+ * bit(1): with Card Reader function
+ * bit(7:2): real revision
+ */
+#define ALX_PCI_REVID_SHIFT                             3
+#define ALX_REV_A0                                      0
+#define ALX_REV_A1                                      1
+#define ALX_REV_B0                                      2
+#define ALX_REV_C0                                      3
+
+#define ALX_DEV_CTRL                                    0x0060
+#define ALX_DEV_CTRL_MAXRRS_MIN                         2
+
+#define ALX_MSIX_MASK                                   0x0090
+
+#define ALX_UE_SVRT                                     0x010C
+#define ALX_UE_SVRT_FCPROTERR                           BIT(13)
+#define ALX_UE_SVRT_DLPROTERR                           BIT(4)
+
+/* eeprom & flash load register */
+#define ALX_EFLD                                        0x0204
+#define ALX_EFLD_F_EXIST                                BIT(10)
+#define ALX_EFLD_E_EXIST                                BIT(9)
+#define ALX_EFLD_STAT                                   BIT(5)
+#define ALX_EFLD_START                                  BIT(0)
+
+/* eFuse load register */
+#define ALX_SLD                                         0x0218
+#define ALX_SLD_STAT                                    BIT(12)
+#define ALX_SLD_START                                   BIT(11)
+#define ALX_SLD_MAX_TO                                  100
+
+#define ALX_PDLL_TRNS1                                  0x1104
+#define ALX_PDLL_TRNS1_D3PLLOFF_EN                      BIT(11)
+
+#define ALX_PMCTRL                                      0x12F8
+#define ALX_PMCTRL_HOTRST_WTEN                          BIT(31)
+/* bit30: L0s/L1 controlled by MAC based on throughput(setting in 15A0) */
+#define ALX_PMCTRL_ASPM_FCEN                            BIT(30)
+#define ALX_PMCTRL_SADLY_EN                             BIT(29)
+#define ALX_PMCTRL_LCKDET_TIMER_MASK                    0xF
+#define ALX_PMCTRL_LCKDET_TIMER_SHIFT                   24
+#define ALX_PMCTRL_LCKDET_TIMER_DEF                     0xC
+/* bit[23:20] if pm_request_l1 time > @, then enter L0s not L1 */
+#define ALX_PMCTRL_L1REQ_TO_MASK                        0xF
+#define ALX_PMCTRL_L1REQ_TO_SHIFT                       20
+#define ALX_PMCTRL_L1REG_TO_DEF                         0xF
+#define ALX_PMCTRL_TXL1_AFTER_L0S                       BIT(19)
+#define ALX_PMCTRL_L1_TIMER_MASK                        0x7
+#define ALX_PMCTRL_L1_TIMER_SHIFT                       16
+#define ALX_PMCTRL_L1_TIMER_16US                        4
+#define ALX_PMCTRL_RCVR_WT_1US                          BIT(15)
+/* bit13: enable pcie clk switch in L1 state */
+#define ALX_PMCTRL_L1_CLKSW_EN                          BIT(13)
+#define ALX_PMCTRL_L0S_EN                               BIT(12)
+#define ALX_PMCTRL_RXL1_AFTER_L0S                       BIT(11)
+#define ALX_PMCTRL_L1_BUFSRX_EN                         BIT(7)
+/* bit6: power down serdes RX */
+#define ALX_PMCTRL_L1_SRDSRX_PWD                        BIT(6)
+#define ALX_PMCTRL_L1_SRDSPLL_EN                        BIT(5)
+#define ALX_PMCTRL_L1_SRDS_EN                           BIT(4)
+#define ALX_PMCTRL_L1_EN                                BIT(3)
+
+/*******************************************************/
+/* following registers are mapped only to memory space */
+/*******************************************************/
+
+#define ALX_MASTER                                      0x1400
+/* bit12: 1:alwys select pclk from serdes, not sw to 25M */
+#define ALX_MASTER_PCLKSEL_SRDS                         BIT(12)
+/* bit11: irq moduration for rx */
+#define ALX_MASTER_IRQMOD2_EN                           BIT(11)
+/* bit10: irq moduration for tx/rx */
+#define ALX_MASTER_IRQMOD1_EN                           BIT(10)
+#define ALX_MASTER_SYSALVTIMER_EN                       BIT(7)
+#define ALX_MASTER_OOB_DIS                              BIT(6)
+/* bit5: wakeup without pcie clk */
+#define ALX_MASTER_WAKEN_25M                            BIT(5)
+/* bit0: MAC & DMA reset */
+#define ALX_MASTER_DMA_MAC_RST                          BIT(0)
+#define ALX_DMA_MAC_RST_TO                              50
+
+#define ALX_IRQ_MODU_TIMER                              0x1408
+#define ALX_IRQ_MODU_TIMER1_MASK                        0xFFFF
+#define ALX_IRQ_MODU_TIMER1_SHIFT                       0
+
+#define ALX_PHY_CTRL                                    0x140C
+#define ALX_PHY_CTRL_100AB_EN                           BIT(17)
+/* bit14: affect MAC & PHY, go to low power sts */
+#define ALX_PHY_CTRL_POWER_DOWN                         BIT(14)
+/* bit13: 1:pll always ON, 0:can switch in lpw */
+#define ALX_PHY_CTRL_PLL_ON                             BIT(13)
+#define ALX_PHY_CTRL_RST_ANALOG                         BIT(12)
+#define ALX_PHY_CTRL_HIB_PULSE                          BIT(11)
+#define ALX_PHY_CTRL_HIB_EN                             BIT(10)
+#define ALX_PHY_CTRL_IDDQ                               BIT(7)
+#define ALX_PHY_CTRL_GATE_25M                           BIT(5)
+#define ALX_PHY_CTRL_LED_MODE                           BIT(2)
+/* bit0: out of dsp RST state */
+#define ALX_PHY_CTRL_DSPRST_OUT                         BIT(0)
+#define ALX_PHY_CTRL_DSPRST_TO                          80
+#define ALX_PHY_CTRL_CLS        (ALX_PHY_CTRL_LED_MODE | \
+                                 ALX_PHY_CTRL_100AB_EN | \
+                                 ALX_PHY_CTRL_PLL_ON)
+
+#define ALX_MAC_STS                                     0x1410
+#define ALX_MAC_STS_TXQ_BUSY                            BIT(3)
+#define ALX_MAC_STS_RXQ_BUSY                            BIT(2)
+#define ALX_MAC_STS_TXMAC_BUSY                          BIT(1)
+#define ALX_MAC_STS_RXMAC_BUSY                          BIT(0)
+#define ALX_MAC_STS_IDLE        (ALX_MAC_STS_TXQ_BUSY | \
+                                 ALX_MAC_STS_RXQ_BUSY | \
+                                 ALX_MAC_STS_TXMAC_BUSY | \
+                                 ALX_MAC_STS_RXMAC_BUSY)
+
+#define ALX_MDIO                                        0x1414
+#define ALX_MDIO_MODE_EXT                               BIT(30)
+#define ALX_MDIO_BUSY                                   BIT(27)
+#define ALX_MDIO_CLK_SEL_MASK                           0x7
+#define ALX_MDIO_CLK_SEL_SHIFT                          24
+#define ALX_MDIO_CLK_SEL_25MD4                          0
+#define ALX_MDIO_CLK_SEL_25MD128                        7
+#define ALX_MDIO_START                                  BIT(23)
+#define ALX_MDIO_SPRES_PRMBL                            BIT(22)
+/* bit21: 1:read,0:write */
+#define ALX_MDIO_OP_READ                                BIT(21)
+#define ALX_MDIO_REG_MASK                               0x1F
+#define ALX_MDIO_REG_SHIFT                              16
+#define ALX_MDIO_DATA_MASK                              0xFFFF
+#define ALX_MDIO_DATA_SHIFT                             0
+#define ALX_MDIO_MAX_AC_TO                              120
+
+#define ALX_MDIO_EXTN                                   0x1448
+#define ALX_MDIO_EXTN_DEVAD_MASK                        0x1F
+#define ALX_MDIO_EXTN_DEVAD_SHIFT                       16
+#define ALX_MDIO_EXTN_REG_MASK                          0xFFFF
+#define ALX_MDIO_EXTN_REG_SHIFT                         0
+
+#define ALX_SERDES                                      0x1424
+#define ALX_SERDES_PHYCLK_SLWDWN                        BIT(18)
+#define ALX_SERDES_MACCLK_SLWDWN                        BIT(17)
+
+#define ALX_LPI_CTRL                                    0x1440
+#define ALX_LPI_CTRL_EN                                 BIT(0)
+
+/* for B0+, bit[13..] for C0+ */
+#define ALX_HRTBT_EXT_CTRL                              0x1AD0
+#define L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_MASK             0x3F
+#define L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_SHIFT            24
+#define L1F_HRTBT_EXT_CTRL_SWOI_STARTUP_PKT_EN          BIT(23)
+#define L1F_HRTBT_EXT_CTRL_IOAC_2_FRAGMENTED            BIT(22)
+#define L1F_HRTBT_EXT_CTRL_IOAC_1_FRAGMENTED            BIT(21)
+#define L1F_HRTBT_EXT_CTRL_IOAC_1_KEEPALIVE_EN          BIT(20)
+#define L1F_HRTBT_EXT_CTRL_IOAC_1_HAS_VLAN              BIT(19)
+#define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_8023               BIT(18)
+#define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_IPV6               BIT(17)
+#define L1F_HRTBT_EXT_CTRL_IOAC_2_KEEPALIVE_EN          BIT(16)
+#define L1F_HRTBT_EXT_CTRL_IOAC_2_HAS_VLAN              BIT(15)
+#define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_8023               BIT(14)
+#define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_IPV6               BIT(13)
+#define ALX_HRTBT_EXT_CTRL_NS_EN                        BIT(12)
+#define ALX_HRTBT_EXT_CTRL_FRAG_LEN_MASK                0xFF
+#define ALX_HRTBT_EXT_CTRL_FRAG_LEN_SHIFT               4
+#define ALX_HRTBT_EXT_CTRL_IS_8023                      BIT(3)
+#define ALX_HRTBT_EXT_CTRL_IS_IPV6                      BIT(2)
+#define ALX_HRTBT_EXT_CTRL_WAKEUP_EN                    BIT(1)
+#define ALX_HRTBT_EXT_CTRL_ARP_EN                       BIT(0)
+
+#define ALX_HRTBT_REM_IPV4_ADDR                         0x1AD4
+#define ALX_HRTBT_HOST_IPV4_ADDR                        0x1478
+#define ALX_HRTBT_REM_IPV6_ADDR3                        0x1AD8
+#define ALX_HRTBT_REM_IPV6_ADDR2                        0x1ADC
+#define ALX_HRTBT_REM_IPV6_ADDR1                        0x1AE0
+#define ALX_HRTBT_REM_IPV6_ADDR0                        0x1AE4
+
+/* 1B8C ~ 1B94 for C0+ */
+#define ALX_SWOI_ACER_CTRL                              0x1B8C
+#define ALX_SWOI_ORIG_ACK_NAK_EN                        BIT(20)
+#define ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_MASK              0XFF
+#define ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_SHIFT             12
+#define ALX_SWOI_ORIG_ACK_ADDR_MASK                     0XFFF
+#define ALX_SWOI_ORIG_ACK_ADDR_SHIFT                    0
+
+#define ALX_SWOI_IOAC_CTRL_2                            0x1B90
+#define ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_MASK       0xFF
+#define ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_SHIFT      24
+#define ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_MASK        0xFFF
+#define ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_SHIFT       12
+#define ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_MASK       0xFFF
+#define ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_SHIFT      0
+
+#define ALX_SWOI_IOAC_CTRL_3                            0x1B94
+#define ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_MASK       0xFF
+#define ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_SHIFT      24
+#define ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_MASK        0xFFF
+#define ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_SHIFT       12
+#define ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_MASK       0xFFF
+#define ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_SHIFT      0
+
+/* for B0 */
+#define ALX_IDLE_DECISN_TIMER                           0x1474
+/* 1ms */
+#define ALX_IDLE_DECISN_TIMER_DEF                       0x400
+
+#define ALX_MAC_CTRL                                    0x1480
+#define ALX_MAC_CTRL_FAST_PAUSE                         BIT(31)
+#define ALX_MAC_CTRL_WOLSPED_SWEN                       BIT(30)
+/* bit29: 1:legacy(hi5b), 0:marvl(lo5b)*/
+#define ALX_MAC_CTRL_MHASH_ALG_HI5B                     BIT(29)
+#define ALX_MAC_CTRL_BRD_EN                             BIT(26)
+#define ALX_MAC_CTRL_MULTIALL_EN                        BIT(25)
+#define ALX_MAC_CTRL_SPEED_MASK                         0x3
+#define ALX_MAC_CTRL_SPEED_SHIFT                        20
+#define ALX_MAC_CTRL_SPEED_10_100                       1
+#define ALX_MAC_CTRL_SPEED_1000                         2
+#define ALX_MAC_CTRL_PROMISC_EN                         BIT(15)
+#define ALX_MAC_CTRL_VLANSTRIP                          BIT(14)
+#define ALX_MAC_CTRL_PRMBLEN_MASK                       0xF
+#define ALX_MAC_CTRL_PRMBLEN_SHIFT                      10
+#define ALX_MAC_CTRL_PCRCE                              BIT(7)
+#define ALX_MAC_CTRL_CRCE                               BIT(6)
+#define ALX_MAC_CTRL_FULLD                              BIT(5)
+#define ALX_MAC_CTRL_RXFC_EN                            BIT(3)
+#define ALX_MAC_CTRL_TXFC_EN                            BIT(2)
+#define ALX_MAC_CTRL_RX_EN                              BIT(1)
+#define ALX_MAC_CTRL_TX_EN                              BIT(0)
+
+#define ALX_STAD0                                       0x1488
+#define ALX_STAD1                                       0x148C
+
+#define ALX_HASH_TBL0                                   0x1490
+#define ALX_HASH_TBL1                                   0x1494
+
+#define ALX_MTU                                         0x149C
+#define ALX_MTU_JUMBO_TH                                1514
+#define ALX_MTU_STD_ALGN                                1536
+
+#define ALX_SRAM5                                       0x1524
+#define ALX_SRAM_RXF_LEN_MASK                           0xFFF
+#define ALX_SRAM_RXF_LEN_SHIFT                          0
+#define ALX_SRAM_RXF_LEN_8K                             (8*1024)
+
+#define ALX_SRAM9                                       0x1534
+#define ALX_SRAM_LOAD_PTR                               BIT(0)
+
+#define ALX_RX_BASE_ADDR_HI                             0x1540
+
+#define ALX_TX_BASE_ADDR_HI                             0x1544
+
+#define ALX_RFD_ADDR_LO                                 0x1550
+#define ALX_RFD_RING_SZ                                 0x1560
+#define ALX_RFD_BUF_SZ                                  0x1564
+
+#define ALX_RRD_ADDR_LO                                 0x1568
+#define ALX_RRD_RING_SZ                                 0x1578
+
+/* pri3: highest, pri0: lowest */
+#define ALX_TPD_PRI3_ADDR_LO                            0x14E4
+#define ALX_TPD_PRI2_ADDR_LO                            0x14E0
+#define ALX_TPD_PRI1_ADDR_LO                            0x157C
+#define ALX_TPD_PRI0_ADDR_LO                            0x1580
+
+/* producer index is 16bit */
+#define ALX_TPD_PRI3_PIDX                               0x1618
+#define ALX_TPD_PRI2_PIDX                               0x161A
+#define ALX_TPD_PRI1_PIDX                               0x15F0
+#define ALX_TPD_PRI0_PIDX                               0x15F2
+
+/* consumer index is 16bit */
+#define ALX_TPD_PRI3_CIDX                               0x161C
+#define ALX_TPD_PRI2_CIDX                               0x161E
+#define ALX_TPD_PRI1_CIDX                               0x15F4
+#define ALX_TPD_PRI0_CIDX                               0x15F6
+
+#define ALX_TPD_RING_SZ                                 0x1584
+
+#define ALX_TXQ0                                        0x1590
+#define ALX_TXQ0_TXF_BURST_PREF_MASK                    0xFFFF
+#define ALX_TXQ0_TXF_BURST_PREF_SHIFT                   16
+#define ALX_TXQ_TXF_BURST_PREF_DEF                      0x200
+#define ALX_TXQ0_LSO_8023_EN                            BIT(7)
+#define ALX_TXQ0_MODE_ENHANCE                           BIT(6)
+#define ALX_TXQ0_EN                                     BIT(5)
+#define ALX_TXQ0_SUPT_IPOPT                             BIT(4)
+#define ALX_TXQ0_TPD_BURSTPREF_MASK                     0xF
+#define ALX_TXQ0_TPD_BURSTPREF_SHIFT                    0
+#define ALX_TXQ_TPD_BURSTPREF_DEF                       5
+
+#define ALX_TXQ1                                        0x1594
+/* bit11:  drop large packet, len > (rfd buf) */
+#define ALX_TXQ1_ERRLGPKT_DROP_EN                       BIT(11)
+#define ALX_TXQ1_JUMBO_TSO_TH                           (7*1024)
+
+#define ALX_RXQ0                                        0x15A0
+#define ALX_RXQ0_EN                                     BIT(31)
+#define ALX_RXQ0_RSS_HASH_EN                            BIT(29)
+#define ALX_RXQ0_RSS_MODE_MASK                          0x3
+#define ALX_RXQ0_RSS_MODE_SHIFT                         26
+#define ALX_RXQ0_RSS_MODE_DIS                           0
+#define ALX_RXQ0_RSS_MODE_MQMI                          3
+#define ALX_RXQ0_NUM_RFD_PREF_MASK                      0x3F
+#define ALX_RXQ0_NUM_RFD_PREF_SHIFT                     20
+#define ALX_RXQ0_NUM_RFD_PREF_DEF                       8
+#define ALX_RXQ0_IDT_TBL_SIZE_MASK                      0x1FF
+#define ALX_RXQ0_IDT_TBL_SIZE_SHIFT                     8
+#define ALX_RXQ0_IDT_TBL_SIZE_DEF                       0x100
+#define ALX_RXQ0_IDT_TBL_SIZE_NORMAL                    128
+#define ALX_RXQ0_IPV6_PARSE_EN                          BIT(7)
+#define ALX_RXQ0_RSS_HSTYP_MASK                         0xF
+#define ALX_RXQ0_RSS_HSTYP_SHIFT                        2
+#define ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN                  BIT(5)
+#define ALX_RXQ0_RSS_HSTYP_IPV6_EN                      BIT(4)
+#define ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN                  BIT(3)
+#define ALX_RXQ0_RSS_HSTYP_IPV4_EN                      BIT(2)
+#define ALX_RXQ0_RSS_HSTYP_ALL          (ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN | \
+                                         ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN | \
+                                         ALX_RXQ0_RSS_HSTYP_IPV6_EN | \
+                                         ALX_RXQ0_RSS_HSTYP_IPV4_EN)
+#define ALX_RXQ0_ASPM_THRESH_MASK                       0x3
+#define ALX_RXQ0_ASPM_THRESH_SHIFT                      0
+#define ALX_RXQ0_ASPM_THRESH_100M                       3
+
+#define ALX_RXQ2                                        0x15A8
+#define ALX_RXQ2_RXF_XOFF_THRESH_MASK                   0xFFF
+#define ALX_RXQ2_RXF_XOFF_THRESH_SHIFT                  16
+#define ALX_RXQ2_RXF_XON_THRESH_MASK                    0xFFF
+#define ALX_RXQ2_RXF_XON_THRESH_SHIFT                   0
+/* Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) +
+ *        rx-packet(1522) + delay-of-link(64)
+ *      = 3212.
+ */
+#define ALX_RXQ2_RXF_FLOW_CTRL_RSVD                     3212
+
+#define ALX_DMA                                         0x15C0
+#define ALX_DMA_RCHNL_SEL_MASK                          0x3
+#define ALX_DMA_RCHNL_SEL_SHIFT                         26
+#define ALX_DMA_WDLY_CNT_MASK                           0xF
+#define ALX_DMA_WDLY_CNT_SHIFT                          16
+#define ALX_DMA_WDLY_CNT_DEF                            4
+#define ALX_DMA_RDLY_CNT_MASK                           0x1F
+#define ALX_DMA_RDLY_CNT_SHIFT                          11
+#define ALX_DMA_RDLY_CNT_DEF                            15
+/* bit10: 0:tpd with pri, 1: data */
+#define ALX_DMA_RREQ_PRI_DATA                           BIT(10)
+#define ALX_DMA_RREQ_BLEN_MASK                          0x7
+#define ALX_DMA_RREQ_BLEN_SHIFT                         4
+#define ALX_DMA_RORDER_MODE_MASK                        0x7
+#define ALX_DMA_RORDER_MODE_SHIFT                       0
+#define ALX_DMA_RORDER_MODE_OUT                         4
+
+#define ALX_WOL0                                        0x14A0
+#define ALX_WOL0_PME_LINK                               BIT(5)
+#define ALX_WOL0_LINK_EN                                BIT(4)
+#define ALX_WOL0_PME_MAGIC_EN                           BIT(3)
+#define ALX_WOL0_MAGIC_EN                               BIT(2)
+
+#define ALX_RFD_PIDX                                    0x15E0
+
+#define ALX_RFD_CIDX                                    0x15F8
+
+/* MIB */
+#define ALX_MIB_BASE                                    0x1700
+#define ALX_MIB_RX_OK                                   (ALX_MIB_BASE + 0)
+#define ALX_MIB_RX_ERRADDR                              (ALX_MIB_BASE + 92)
+#define ALX_MIB_TX_OK                                   (ALX_MIB_BASE + 96)
+#define ALX_MIB_TX_MCCNT                                (ALX_MIB_BASE + 192)
+
+#define ALX_RX_STATS_BIN                                ALX_MIB_RX_OK
+#define ALX_RX_STATS_END                                ALX_MIB_RX_ERRADDR
+#define ALX_TX_STATS_BIN                                ALX_MIB_TX_OK
+#define ALX_TX_STATS_END                                ALX_MIB_TX_MCCNT
+
+#define ALX_ISR                                         0x1600
+#define ALX_ISR_DIS                                     BIT(31)
+#define ALX_ISR_RX_Q7                                   BIT(30)
+#define ALX_ISR_RX_Q6                                   BIT(29)
+#define ALX_ISR_RX_Q5                                   BIT(28)
+#define ALX_ISR_RX_Q4                                   BIT(27)
+#define ALX_ISR_PCIE_LNKDOWN                            BIT(26)
+#define ALX_ISR_RX_Q3                                   BIT(19)
+#define ALX_ISR_RX_Q2                                   BIT(18)
+#define ALX_ISR_RX_Q1                                   BIT(17)
+#define ALX_ISR_RX_Q0                                   BIT(16)
+#define ALX_ISR_TX_Q0                                   BIT(15)
+#define ALX_ISR_PHY                                     BIT(12)
+#define ALX_ISR_DMAW                                    BIT(10)
+#define ALX_ISR_DMAR                                    BIT(9)
+#define ALX_ISR_TXF_UR                                  BIT(8)
+#define ALX_ISR_TX_Q3                                   BIT(7)
+#define ALX_ISR_TX_Q2                                   BIT(6)
+#define ALX_ISR_TX_Q1                                   BIT(5)
+#define ALX_ISR_RFD_UR                                  BIT(4)
+#define ALX_ISR_RXF_OV                                  BIT(3)
+#define ALX_ISR_MANU                                    BIT(2)
+#define ALX_ISR_TIMER                                   BIT(1)
+#define ALX_ISR_SMB                                     BIT(0)
+
+#define ALX_IMR                                         0x1604
+
+/* re-send assert msg if SW no response */
+#define ALX_INT_RETRIG                                  0x1608
+/* 40ms */
+#define ALX_INT_RETRIG_TO                               20000
+
+#define ALX_SMB_TIMER                                   0x15C4
+
+#define ALX_TINT_TPD_THRSHLD                            0x15C8
+
+#define ALX_TINT_TIMER                                  0x15CC
+
+#define ALX_CLK_GATE                                    0x1814
+#define ALX_CLK_GATE_RXMAC                              BIT(5)
+#define ALX_CLK_GATE_TXMAC                              BIT(4)
+#define ALX_CLK_GATE_RXQ                                BIT(3)
+#define ALX_CLK_GATE_TXQ                                BIT(2)
+#define ALX_CLK_GATE_DMAR                               BIT(1)
+#define ALX_CLK_GATE_DMAW                               BIT(0)
+#define ALX_CLK_GATE_ALL                (ALX_CLK_GATE_RXMAC | \
+                                         ALX_CLK_GATE_TXMAC | \
+                                         ALX_CLK_GATE_RXQ | \
+                                         ALX_CLK_GATE_TXQ | \
+                                         ALX_CLK_GATE_DMAR | \
+                                         ALX_CLK_GATE_DMAW)
+
+/* interop between drivers */
+#define ALX_DRV                                         0x1804
+#define ALX_DRV_PHY_AUTO                                BIT(28)
+#define ALX_DRV_PHY_1000                                BIT(27)
+#define ALX_DRV_PHY_100                                 BIT(26)
+#define ALX_DRV_PHY_10                                  BIT(25)
+#define ALX_DRV_PHY_DUPLEX                              BIT(24)
+/* bit23: adv Pause */
+#define ALX_DRV_PHY_PAUSE                               BIT(23)
+/* bit22: adv Asym Pause */
+#define ALX_DRV_PHY_MASK                                0xFF
+#define ALX_DRV_PHY_SHIFT                               21
+#define ALX_DRV_PHY_UNKNOWN                             0
+
+/* flag of phy inited */
+#define ALX_PHY_INITED                                  0x003F
+
+/* reg 1830 ~ 186C for C0+, 16 bit map patterns and wake packet detection */
+#define ALX_WOL_CTRL2                                   0x1830
+#define ALX_WOL_CTRL2_DATA_STORE                        BIT(3)
+#define ALX_WOL_CTRL2_PTRN_EVT                          BIT(2)
+#define ALX_WOL_CTRL2_PME_PTRN_EN                       BIT(1)
+#define ALX_WOL_CTRL2_PTRN_EN                           BIT(0)
+
+#define ALX_WOL_CTRL3                                   0x1834
+#define ALX_WOL_CTRL3_PTRN_ADDR_MASK                    0xFFFFF
+#define ALX_WOL_CTRL3_PTRN_ADDR_SHIFT                   0
+
+#define ALX_WOL_CTRL4                                   0x1838
+#define ALX_WOL_CTRL4_PT15_MATCH                        BIT(31)
+#define ALX_WOL_CTRL4_PT14_MATCH                        BIT(30)
+#define ALX_WOL_CTRL4_PT13_MATCH                        BIT(29)
+#define ALX_WOL_CTRL4_PT12_MATCH                        BIT(28)
+#define ALX_WOL_CTRL4_PT11_MATCH                        BIT(27)
+#define ALX_WOL_CTRL4_PT10_MATCH                        BIT(26)
+#define ALX_WOL_CTRL4_PT9_MATCH                         BIT(25)
+#define ALX_WOL_CTRL4_PT8_MATCH                         BIT(24)
+#define ALX_WOL_CTRL4_PT7_MATCH                         BIT(23)
+#define ALX_WOL_CTRL4_PT6_MATCH                         BIT(22)
+#define ALX_WOL_CTRL4_PT5_MATCH                         BIT(21)
+#define ALX_WOL_CTRL4_PT4_MATCH                         BIT(20)
+#define ALX_WOL_CTRL4_PT3_MATCH                         BIT(19)
+#define ALX_WOL_CTRL4_PT2_MATCH                         BIT(18)
+#define ALX_WOL_CTRL4_PT1_MATCH                         BIT(17)
+#define ALX_WOL_CTRL4_PT0_MATCH                         BIT(16)
+#define ALX_WOL_CTRL4_PT15_EN                           BIT(15)
+#define ALX_WOL_CTRL4_PT14_EN                           BIT(14)
+#define ALX_WOL_CTRL4_PT13_EN                           BIT(13)
+#define ALX_WOL_CTRL4_PT12_EN                           BIT(12)
+#define ALX_WOL_CTRL4_PT11_EN                           BIT(11)
+#define ALX_WOL_CTRL4_PT10_EN                           BIT(10)
+#define ALX_WOL_CTRL4_PT9_EN                            BIT(9)
+#define ALX_WOL_CTRL4_PT8_EN                            BIT(8)
+#define ALX_WOL_CTRL4_PT7_EN                            BIT(7)
+#define ALX_WOL_CTRL4_PT6_EN                            BIT(6)
+#define ALX_WOL_CTRL4_PT5_EN                            BIT(5)
+#define ALX_WOL_CTRL4_PT4_EN                            BIT(4)
+#define ALX_WOL_CTRL4_PT3_EN                            BIT(3)
+#define ALX_WOL_CTRL4_PT2_EN                            BIT(2)
+#define ALX_WOL_CTRL4_PT1_EN                            BIT(1)
+#define ALX_WOL_CTRL4_PT0_EN                            BIT(0)
+
+#define ALX_WOL_CTRL5                                   0x183C
+#define ALX_WOL_CTRL5_PT3_LEN_MASK                      0xFF
+#define ALX_WOL_CTRL5_PT3_LEN_SHIFT                     24
+#define ALX_WOL_CTRL5_PT2_LEN_MASK                      0xFF
+#define ALX_WOL_CTRL5_PT2_LEN_SHIFT                     16
+#define ALX_WOL_CTRL5_PT1_LEN_MASK                      0xFF
+#define ALX_WOL_CTRL5_PT1_LEN_SHIFT                     8
+#define ALX_WOL_CTRL5_PT0_LEN_MASK                      0xFF
+#define ALX_WOL_CTRL5_PT0_LEN_SHIFT                     0
+
+#define ALX_WOL_CTRL6                                   0x1840
+#define ALX_WOL_CTRL5_PT7_LEN_MASK                      0xFF
+#define ALX_WOL_CTRL5_PT7_LEN_SHIFT                     24
+#define ALX_WOL_CTRL5_PT6_LEN_MASK                      0xFF
+#define ALX_WOL_CTRL5_PT6_LEN_SHIFT                     16
+#define ALX_WOL_CTRL5_PT5_LEN_MASK                      0xFF
+#define ALX_WOL_CTRL5_PT5_LEN_SHIFT                     8
+#define ALX_WOL_CTRL5_PT4_LEN_MASK                      0xFF
+#define ALX_WOL_CTRL5_PT4_LEN_SHIFT                     0
+
+#define ALX_WOL_CTRL7                                   0x1844
+#define ALX_WOL_CTRL5_PT11_LEN_MASK                     0xFF
+#define ALX_WOL_CTRL5_PT11_LEN_SHIFT                    24
+#define ALX_WOL_CTRL5_PT10_LEN_MASK                     0xFF
+#define ALX_WOL_CTRL5_PT10_LEN_SHIFT                    16
+#define ALX_WOL_CTRL5_PT9_LEN_MASK                      0xFF
+#define ALX_WOL_CTRL5_PT9_LEN_SHIFT                     8
+#define ALX_WOL_CTRL5_PT8_LEN_MASK                      0xFF
+#define ALX_WOL_CTRL5_PT8_LEN_SHIFT                     0
+
+#define ALX_WOL_CTRL8                                   0x1848
+#define ALX_WOL_CTRL5_PT15_LEN_MASK                     0xFF
+#define ALX_WOL_CTRL5_PT15_LEN_SHIFT                    24
+#define ALX_WOL_CTRL5_PT14_LEN_MASK                     0xFF
+#define ALX_WOL_CTRL5_PT14_LEN_SHIFT                    16
+#define ALX_WOL_CTRL5_PT13_LEN_MASK                     0xFF
+#define ALX_WOL_CTRL5_PT13_LEN_SHIFT                    8
+#define ALX_WOL_CTRL5_PT12_LEN_MASK                     0xFF
+#define ALX_WOL_CTRL5_PT12_LEN_SHIFT                    0
+
+#define ALX_ACER_FIXED_PTN0                             0x1850
+#define ALX_ACER_FIXED_PTN0_MASK                        0xFFFFFFFF
+#define ALX_ACER_FIXED_PTN0_SHIFT                       0
+
+#define ALX_ACER_FIXED_PTN1                             0x1854
+#define ALX_ACER_FIXED_PTN1_MASK                        0xFFFF
+#define ALX_ACER_FIXED_PTN1_SHIFT                       0
+
+#define ALX_ACER_RANDOM_NUM0                            0x1858
+#define ALX_ACER_RANDOM_NUM0_MASK                       0xFFFFFFFF
+#define ALX_ACER_RANDOM_NUM0_SHIFT                      0
+
+#define ALX_ACER_RANDOM_NUM1                            0x185C
+#define ALX_ACER_RANDOM_NUM1_MASK                       0xFFFFFFFF
+#define ALX_ACER_RANDOM_NUM1_SHIFT                      0
+
+#define ALX_ACER_RANDOM_NUM2                            0x1860
+#define ALX_ACER_RANDOM_NUM2_MASK                       0xFFFFFFFF
+#define ALX_ACER_RANDOM_NUM2_SHIFT                      0
+
+#define ALX_ACER_RANDOM_NUM3                            0x1864
+#define ALX_ACER_RANDOM_NUM3_MASK                       0xFFFFFFFF
+#define ALX_ACER_RANDOM_NUM3_SHIFT                      0
+
+#define ALX_ACER_MAGIC                                  0x1868
+#define ALX_ACER_MAGIC_EN                               BIT(31)
+#define ALX_ACER_MAGIC_PME_EN                           BIT(30)
+#define ALX_ACER_MAGIC_MATCH                            BIT(29)
+#define ALX_ACER_MAGIC_FF_CHECK                         BIT(10)
+#define ALX_ACER_MAGIC_RAN_LEN_MASK                     0x1F
+#define ALX_ACER_MAGIC_RAN_LEN_SHIFT                    5
+#define ALX_ACER_MAGIC_FIX_LEN_MASK                     0x1F
+#define ALX_ACER_MAGIC_FIX_LEN_SHIFT                    0
+
+#define ALX_ACER_TIMER                                  0x186C
+#define ALX_ACER_TIMER_EN                               BIT(31)
+#define ALX_ACER_TIMER_PME_EN                           BIT(30)
+#define ALX_ACER_TIMER_MATCH                            BIT(29)
+#define ALX_ACER_TIMER_THRES_MASK                       0x1FFFF
+#define ALX_ACER_TIMER_THRES_SHIFT                      0
+#define ALX_ACER_TIMER_THRES_DEF                        1
+
+/* RSS definitions */
+#define ALX_RSS_KEY0                                    0x14B0
+#define ALX_RSS_KEY1                                    0x14B4
+#define ALX_RSS_KEY2                                    0x14B8
+#define ALX_RSS_KEY3                                    0x14BC
+#define ALX_RSS_KEY4                                    0x14C0
+#define ALX_RSS_KEY5                                    0x14C4
+#define ALX_RSS_KEY6                                    0x14C8
+#define ALX_RSS_KEY7                                    0x14CC
+#define ALX_RSS_KEY8                                    0x14D0
+#define ALX_RSS_KEY9                                    0x14D4
+
+#define ALX_RSS_IDT_TBL0                                0x1B00
+
+#define ALX_MSI_MAP_TBL1                                0x15D0
+#define ALX_MSI_MAP_TBL1_TXQ1_SHIFT                     20
+#define ALX_MSI_MAP_TBL1_TXQ0_SHIFT                     16
+#define ALX_MSI_MAP_TBL1_RXQ3_SHIFT                     12
+#define ALX_MSI_MAP_TBL1_RXQ2_SHIFT                     8
+#define ALX_MSI_MAP_TBL1_RXQ1_SHIFT                     4
+#define ALX_MSI_MAP_TBL1_RXQ0_SHIFT                     0
+
+#define ALX_MSI_MAP_TBL2                                0x15D8
+#define ALX_MSI_MAP_TBL2_TXQ3_SHIFT                     20
+#define ALX_MSI_MAP_TBL2_TXQ2_SHIFT                     16
+#define ALX_MSI_MAP_TBL2_RXQ7_SHIFT                     12
+#define ALX_MSI_MAP_TBL2_RXQ6_SHIFT                     8
+#define ALX_MSI_MAP_TBL2_RXQ5_SHIFT                     4
+#define ALX_MSI_MAP_TBL2_RXQ4_SHIFT                     0
+
+#define ALX_MSI_ID_MAP                                  0x15D4
+
+#define ALX_MSI_RETRANS_TIMER                           0x1920
+/* bit16: 1:line,0:standard */
+#define ALX_MSI_MASK_SEL_LINE                           BIT(16)
+#define ALX_MSI_RETRANS_TM_MASK                         0xFFFF
+#define ALX_MSI_RETRANS_TM_SHIFT                        0
+
+/* CR DMA ctrl */
+
+/* TX QoS */
+#define ALX_WRR                                         0x1938
+#define ALX_WRR_PRI_MASK                                0x3
+#define ALX_WRR_PRI_SHIFT                               29
+#define ALX_WRR_PRI_RESTRICT_NONE                       3
+#define ALX_WRR_PRI3_MASK                               0x1F
+#define ALX_WRR_PRI3_SHIFT                              24
+#define ALX_WRR_PRI2_MASK                               0x1F
+#define ALX_WRR_PRI2_SHIFT                              16
+#define ALX_WRR_PRI1_MASK                               0x1F
+#define ALX_WRR_PRI1_SHIFT                              8
+#define ALX_WRR_PRI0_MASK                               0x1F
+#define ALX_WRR_PRI0_SHIFT                              0
+
+#define ALX_HQTPD                                       0x193C
+#define ALX_HQTPD_BURST_EN                              BIT(31)
+#define ALX_HQTPD_Q3_NUMPREF_MASK                       0xF
+#define ALX_HQTPD_Q3_NUMPREF_SHIFT                      8
+#define ALX_HQTPD_Q2_NUMPREF_MASK                       0xF
+#define ALX_HQTPD_Q2_NUMPREF_SHIFT                      4
+#define ALX_HQTPD_Q1_NUMPREF_MASK                       0xF
+#define ALX_HQTPD_Q1_NUMPREF_SHIFT                      0
+
+#define ALX_MISC                                        0x19C0
+#define ALX_MISC_PSW_OCP_MASK                           0x7
+#define ALX_MISC_PSW_OCP_SHIFT                          21
+#define ALX_MISC_PSW_OCP_DEF                            0x7
+#define ALX_MISC_ISO_EN                                 BIT(12)
+#define ALX_MISC_INTNLOSC_OPEN                          BIT(3)
+
+#define ALX_MSIC2                                       0x19C8
+#define ALX_MSIC2_CALB_START                            BIT(0)
+
+#define ALX_MISC3                                       0x19CC
+/* bit1: 1:Software control 25M */
+#define ALX_MISC3_25M_BY_SW                             BIT(1)
+/* bit0: 25M switch to intnl OSC */
+#define ALX_MISC3_25M_NOTO_INTNL                        BIT(0)
+
+/* MSIX tbl in memory space */
+#define ALX_MSIX_ENTRY_BASE                             0x2000
+
+/********************* PHY regs definition ***************************/
+
+/* PHY Specific Status Register */
+#define ALX_MII_GIGA_PSSR                               0x11
+#define ALX_GIGA_PSSR_SPD_DPLX_RESOLVED                 0x0800
+#define ALX_GIGA_PSSR_DPLX                              0x2000
+#define ALX_GIGA_PSSR_SPEED                             0xC000
+#define ALX_GIGA_PSSR_10MBS                             0x0000
+#define ALX_GIGA_PSSR_100MBS                            0x4000
+#define ALX_GIGA_PSSR_1000MBS                           0x8000
+
+/* PHY Interrupt Enable Register */
+#define ALX_MII_IER                                     0x12
+#define ALX_IER_LINK_UP                                 0x0400
+#define ALX_IER_LINK_DOWN                               0x0800
+
+/* PHY Interrupt Status Register */
+#define ALX_MII_ISR                                     0x13
+
+#define ALX_MII_DBG_ADDR                                0x1D
+#define ALX_MII_DBG_DATA                                0x1E
+
+/***************************** debug port *************************************/
+
+#define ALX_MIIDBG_ANACTRL                              0x00
+#define ALX_ANACTRL_DEF                                 0x02EF
+
+#define ALX_MIIDBG_SYSMODCTRL                           0x04
+/* en half bias */
+#define ALX_SYSMODCTRL_IECHOADJ_DEF                     0xBB8B
+
+#define ALX_MIIDBG_SRDSYSMOD                            0x05
+#define ALX_SRDSYSMOD_DEEMP_EN                          0x0040
+#define ALX_SRDSYSMOD_DEF                               0x2C46
+
+#define ALX_MIIDBG_HIBNEG                               0x0B
+#define ALX_HIBNEG_PSHIB_EN                             0x8000
+#define ALX_HIBNEG_HIB_PSE                              0x1000
+#define ALX_HIBNEG_DEF                                  0xBC40
+#define ALX_HIBNEG_NOHIB        (ALX_HIBNEG_DEF & \
+                                 ~(ALX_HIBNEG_PSHIB_EN | ALX_HIBNEG_HIB_PSE))
+
+#define ALX_MIIDBG_TST10BTCFG                           0x12
+#define ALX_TST10BTCFG_DEF                              0x4C04
+
+#define ALX_MIIDBG_AZ_ANADECT                           0x15
+#define ALX_AZ_ANADECT_DEF                              0x3220
+#define ALX_AZ_ANADECT_LONG                             0x3210
+
+#define ALX_MIIDBG_MSE16DB                              0x18
+#define ALX_MSE16DB_UP                                  0x05EA
+#define ALX_MSE16DB_DOWN                                0x02EA
+
+#define ALX_MIIDBG_MSE20DB                              0x1C
+#define ALX_MSE20DB_TH_MASK                             0x7F
+#define ALX_MSE20DB_TH_SHIFT                            2
+#define ALX_MSE20DB_TH_DEF                              0x2E
+#define ALX_MSE20DB_TH_HI                               0x54
+
+#define ALX_MIIDBG_AGC                                  0x23
+#define ALX_AGC_2_VGA_MASK                              0x3FU
+#define ALX_AGC_2_VGA_SHIFT                             8
+#define ALX_AGC_LONG1G_LIMT                             40
+#define ALX_AGC_LONG100M_LIMT                           44
+
+#define ALX_MIIDBG_LEGCYPS                              0x29
+#define ALX_LEGCYPS_EN                                  0x8000
+#define ALX_LEGCYPS_DEF                                 0x129D
+
+#define ALX_MIIDBG_TST100BTCFG                          0x36
+#define ALX_TST100BTCFG_DEF                             0xE12C
+
+#define ALX_MIIDBG_GREENCFG                             0x3B
+#define ALX_GREENCFG_DEF                                0x7078
+
+#define ALX_MIIDBG_GREENCFG2                            0x3D
+#define ALX_GREENCFG2_BP_GREEN                          0x8000
+#define ALX_GREENCFG2_GATE_DFSE_EN                      0x0080
+
+/******* dev 3 *********/
+#define ALX_MIIEXT_PCS                                  3
+
+#define ALX_MIIEXT_CLDCTRL3                             0x8003
+#define ALX_CLDCTRL3_BP_CABLE1TH_DET_GT                 0x8000
+
+#define ALX_MIIEXT_CLDCTRL5                             0x8005
+#define ALX_CLDCTRL5_BP_VD_HLFBIAS                      0x4000
+
+#define ALX_MIIEXT_CLDCTRL6                             0x8006
+#define ALX_CLDCTRL6_CAB_LEN_MASK                       0xFF
+#define ALX_CLDCTRL6_CAB_LEN_SHIFT                      0
+#define ALX_CLDCTRL6_CAB_LEN_SHORT1G                    116
+#define ALX_CLDCTRL6_CAB_LEN_SHORT100M                  152
+
+#define ALX_MIIEXT_VDRVBIAS                             0x8062
+#define ALX_VDRVBIAS_DEF                                0x3
+
+/********* dev 7 **********/
+#define ALX_MIIEXT_ANEG                                 7
+
+#define ALX_MIIEXT_LOCAL_EEEADV                         0x3C
+#define ALX_LOCAL_EEEADV_1000BT                         0x0004
+#define ALX_LOCAL_EEEADV_100BT                          0x0002
+
+#define ALX_MIIEXT_AFE                                  0x801A
+#define ALX_AFE_10BT_100M_TH                            0x0040
+
+#define ALX_MIIEXT_S3DIG10                              0x8023
+/* bit0: 1:bypass 10BT rx fifo, 0:original 10BT rx */
+#define ALX_MIIEXT_S3DIG10_SL                           0x0001
+#define ALX_MIIEXT_S3DIG10_DEF                          0
+
+#define ALX_MIIEXT_NLP78                                0x8027
+#define ALX_MIIEXT_NLP78_120M_DEF                       0x8A05
+
+#endif
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
index be59ec4b2c30..638e55435b04 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
@@ -3192,11 +3192,11 @@ static u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
                 rc |= XMIT_CSUM_TCP;
 
         if (skb_is_gso_v6(skb)) {
-                rc |= (XMIT_GSO_V6 | XMIT_CSUM_TCP | XMIT_CSUM_V6);
+                rc |= (XMIT_GSO_V6 | XMIT_CSUM_TCP);
                 if (rc & XMIT_CSUM_ENC)
                         rc |= XMIT_GSO_ENC_V6;
         } else if (skb_is_gso(skb)) {
-                rc |= (XMIT_GSO_V4 | XMIT_CSUM_V4 | XMIT_CSUM_TCP);
+                rc |= (XMIT_GSO_V4 | XMIT_CSUM_TCP);
                 if (rc & XMIT_CSUM_ENC)
                         rc |= XMIT_GSO_ENC_V4;
         }
@@ -3483,19 +3483,18 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
 {
         u16 hlen_w = 0;
         u8 outerip_off, outerip_len = 0;
+
         /* from outer IP to transport */
         hlen_w = (skb_inner_transport_header(skb) -
                   skb_network_header(skb)) >> 1;
 
         /* transport len */
-        if (xmit_type & XMIT_CSUM_TCP)
-                hlen_w += inner_tcp_hdrlen(skb) >> 1;
-        else
-                hlen_w += sizeof(struct udphdr) >> 1;
+        hlen_w += inner_tcp_hdrlen(skb) >> 1;
 
         pbd2->fw_ip_hdr_to_payload_w = hlen_w;
 
-        if (xmit_type & XMIT_CSUM_ENC_V4) {
+        /* outer IP header info */
+        if (xmit_type & XMIT_CSUM_V4) {
                 struct iphdr *iph = ip_hdr(skb);
                 pbd2->fw_ip_csum_wo_len_flags_frag =
                         bswab16(csum_fold((~iph->check) -
@@ -3818,8 +3817,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
                         bnx2x_set_pbd_gso_e2(skb, &pbd_e2_parsing_data,
                                              xmit_type);
                 else
-                        bnx2x_set_pbd_gso(skb, pbd_e1x, tx_start_bd,
-                                          xmit_type);
+                        bnx2x_set_pbd_gso(skb, pbd_e1x, first_bd, xmit_type);
         }
 
         /* Set the PBD's parsing_data field if not zero
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 1f2dd928888a..a13463e8a2c3 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -744,6 +744,9 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
                 status = tg3_ape_read32(tp, gnt + off);
                 if (status == bit)
                         break;
+                if (pci_channel_offline(tp->pdev))
+                        break;
+
                 udelay(10);
         }
 
@@ -1635,6 +1638,9 @@ static void tg3_wait_for_event_ack(struct tg3 *tp)
         for (i = 0; i < delay_cnt; i++) {
                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
                         break;
+                if (pci_channel_offline(tp->pdev))
+                        break;
+
                 udelay(8);
         }
 }
@@ -1800,6 +1806,9 @@ static int tg3_poll_fw(struct tg3 *tp)
         int i;
         u32 val;
 
+        if (tg3_flag(tp, NO_FWARE_REPORTED))
+                return 0;
+
         if (tg3_flag(tp, IS_SSB_CORE)) {
                 /* We don't use firmware. */
                 return 0;
@@ -1810,6 +1819,9 @@ static int tg3_poll_fw(struct tg3 *tp)
                 for (i = 0; i < 200; i++) {
                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
                                 return 0;
+                        if (pci_channel_offline(tp->pdev))
+                                return -ENODEV;
+
                         udelay(100);
                 }
                 return -ENODEV;
@@ -1820,6 +1832,15 @@ static int tg3_poll_fw(struct tg3 *tp)
                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
                         break;
+                if (pci_channel_offline(tp->pdev)) {
+                        if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
+                                tg3_flag_set(tp, NO_FWARE_REPORTED);
+                                netdev_info(tp->dev, "No firmware running\n");
+                        }
+
+                        break;
+                }
+
                 udelay(10);
         }
 
@@ -3517,6 +3538,8 @@ static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
                 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
                         break;
+                if (pci_channel_offline(tp->pdev))
+                        return -EBUSY;
         }
 
         return (i == iters) ? -EBUSY : 0;
@@ -8586,6 +8609,14 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, boo
         tw32_f(ofs, val);
 
         for (i = 0; i < MAX_WAIT_CNT; i++) {
+                if (pci_channel_offline(tp->pdev)) {
+                        dev_err(&tp->pdev->dev,
+                                "tg3_stop_block device offline, "
+                                "ofs=%lx enable_bit=%x\n",
+                                ofs, enable_bit);
+                        return -ENODEV;
+                }
+
                 udelay(100);
                 val = tr32(ofs);
                 if ((val & enable_bit) == 0)
@@ -8609,6 +8640,13 @@ static int tg3_abort_hw(struct tg3 *tp, bool silent)
 
         tg3_disable_ints(tp);
 
+        if (pci_channel_offline(tp->pdev)) {
+                tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
+                tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
+                err = -ENODEV;
+                goto err_no_dev;
+        }
+
         tp->rx_mode &= ~RX_MODE_ENABLE;
         tw32_f(MAC_RX_MODE, tp->rx_mode);
         udelay(10);
@@ -8657,6 +8695,7 @@ static int tg3_abort_hw(struct tg3 *tp, bool silent)
         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
 
+err_no_dev:
         for (i = 0; i < tp->irq_cnt; i++) {
                 struct tg3_napi *tnapi = &tp->napi[i];
                 if (tnapi->hw_status)
@@ -9468,6 +9507,14 @@ static void tg3_rss_write_indir_tbl(struct tg3 *tp)
         }
 }
 
+static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
+{
+        if (tg3_asic_rev(tp) == ASIC_REV_5719)
+                return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
+        else
+                return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
+}
+
 /* tp->lock is held. */
 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
 {
@@ -10153,16 +10200,17 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
         tw32_f(RDMAC_MODE, rdmac_mode);
         udelay(40);
 
-        if (tg3_asic_rev(tp) == ASIC_REV_5719) {
+        if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
+            tg3_asic_rev(tp) == ASIC_REV_5720) {
                 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
                         if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
                                 break;
                 }
                 if (i < TG3_NUM_RDMA_CHANNELS) {
                         val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
-                        val |= TG3_LSO_RD_DMA_TX_LENGTH_WA;
+                        val |= tg3_lso_rd_dma_workaround_bit(tp);
                         tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
-                        tg3_flag_set(tp, 5719_RDMA_BUG);
+                        tg3_flag_set(tp, 5719_5720_RDMA_BUG);
                 }
         }
 
@@ -10395,6 +10443,13 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
  */
 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
 {
+        /* Chip may have been just powered on. If so, the boot code may still
+         * be running initialization. Wait for it to finish to avoid races in
+         * accessing the hardware.
+         */
+        tg3_enable_register_access(tp);
+        tg3_poll_fw(tp);
+
         tg3_switch_clocks(tp);
 
         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
@@ -10526,15 +10581,15 @@ static void tg3_periodic_fetch_stats(struct tg3 *tp)
         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
-        if (unlikely(tg3_flag(tp, 5719_RDMA_BUG) &&
+        if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
                      (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
                       sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
                 u32 val;
 
                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
-                val &= ~TG3_LSO_RD_DMA_TX_LENGTH_WA;
+                val &= ~tg3_lso_rd_dma_workaround_bit(tp);
                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
-                tg3_flag_clear(tp, 5719_RDMA_BUG);
+                tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
         }
 
         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h
index 9b2d3ac2474a..ff6e30eeae35 100644
--- a/drivers/net/ethernet/broadcom/tg3.h
+++ b/drivers/net/ethernet/broadcom/tg3.h
@@ -1422,7 +1422,8 @@
 #define TG3_LSO_RD_DMA_CRPTEN_CTRL      0x00004910
 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K    0x00030000
 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K   0x000c0000
-#define TG3_LSO_RD_DMA_TX_LENGTH_WA      0x02000000
+#define TG3_LSO_RD_DMA_TX_LENGTH_WA_5719         0x02000000
+#define TG3_LSO_RD_DMA_TX_LENGTH_WA_5720         0x00200000
 /* 0x4914 --> 0x4be0 unused */
 
 #define TG3_NUM_RDMA_CHANNELS           4
@@ -3059,7 +3060,7 @@ enum TG3_FLAGS {
         TG3_FLAG_APE_HAS_NCSI,
         TG3_FLAG_TX_TSTAMP_EN,
         TG3_FLAG_4K_FIFO_LIMIT,
-        TG3_FLAG_5719_RDMA_BUG,
+        TG3_FLAG_5719_5720_RDMA_BUG,
         TG3_FLAG_RESET_TASK_PENDING,
         TG3_FLAG_PTP_CAPABLE,
         TG3_FLAG_5705_PLUS,
diff --git a/drivers/net/ethernet/brocade/bna/bnad_debugfs.c b/drivers/net/ethernet/brocade/bna/bnad_debugfs.c
index 6e8bc9d88c41..94d957d203a6 100644
--- a/drivers/net/ethernet/brocade/bna/bnad_debugfs.c
+++ b/drivers/net/ethernet/brocade/bna/bnad_debugfs.c
@@ -244,7 +244,7 @@ bnad_debugfs_lseek(struct file *file, loff_t offset, int orig)
                 file->f_pos += offset;
                 break;
         case 2:
-                file->f_pos = debug->buffer_len - offset;
+                file->f_pos = debug->buffer_len + offset;
                 break;
         default:
                 return -EINVAL;
diff --git a/drivers/net/ethernet/dec/tulip/interrupt.c b/drivers/net/ethernet/dec/tulip/interrupt.c
index 28a5e425fecf..92306b320840 100644
--- a/drivers/net/ethernet/dec/tulip/interrupt.c
+++ b/drivers/net/ethernet/dec/tulip/interrupt.c
@@ -76,6 +76,12 @@ int tulip_refill_rx(struct net_device *dev)
 
                         mapping = pci_map_single(tp->pdev, skb->data, PKT_BUF_SZ,
                                                  PCI_DMA_FROMDEVICE);
+                        if (dma_mapping_error(&tp->pdev->dev, mapping)) {
+                                dev_kfree_skb(skb);
+                                tp->rx_buffers[entry].skb = NULL;
+                                break;
+                        }
+
                         tp->rx_buffers[entry].mapping = mapping;
 
                         tp->rx_ring[entry].buffer1 = cpu_to_le32(mapping);
diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h
index f544b297c9ab..0a510684e468 100644
--- a/drivers/net/ethernet/emulex/benet/be.h
+++ b/drivers/net/ethernet/emulex/benet/be.h
@@ -262,6 +262,7 @@ struct be_rx_compl_info {
         u8 ipv6;
         u8 vtm;
         u8 pkt_type;
+        u8 ip_frag;
 };
 
 struct be_rx_obj {
diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c
index a236ecd27cf3..1db2df61b8af 100644
--- a/drivers/net/ethernet/emulex/benet/be_cmds.c
+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c
@@ -562,7 +562,7 @@ int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 
         resource_error = lancer_provisioning_error(adapter);
         if (resource_error)
-                return -1;
+                return -EAGAIN;
 
         status = lancer_wait_ready(adapter);
         if (!status) {
@@ -590,8 +590,8 @@ int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
          * when PF provisions resources.
          */
         resource_error = lancer_provisioning_error(adapter);
-        if (status == -1 && !resource_error)
-                adapter->eeh_error = true;
+        if (resource_error)
+                status = -EAGAIN;
 
         return status;
 }
diff --git a/drivers/net/ethernet/emulex/benet/be_hw.h b/drivers/net/ethernet/emulex/benet/be_hw.h
index 3c1099b47f2a..8780183c6d1c 100644
--- a/drivers/net/ethernet/emulex/benet/be_hw.h
+++ b/drivers/net/ethernet/emulex/benet/be_hw.h
@@ -356,7 +356,7 @@ struct amap_eth_rx_compl_v0 {
         u8 ip_version;          /* dword 1 */
         u8 macdst[6];           /* dword 1 */
         u8 vtp;                 /* dword 1 */
-        u8 rsvd0;               /* dword 1 */
+        u8 ip_frag;             /* dword 1 */
         u8 fragndx[10];         /* dword 1 */
         u8 ct[2];               /* dword 1 */
         u8 sw;                  /* dword 1 */
diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c
index ca2967b0f18b..a0b4be51f0d1 100644
--- a/drivers/net/ethernet/emulex/benet/be_main.c
+++ b/drivers/net/ethernet/emulex/benet/be_main.c
@@ -1599,6 +1599,8 @@ static void be_parse_rx_compl_v0(struct be_eth_rx_compl *compl,
                                                compl);
         }
         rxcp->port = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, port, compl);
+        rxcp->ip_frag = AMAP_GET_BITS(struct amap_eth_rx_compl_v0,
+                                      ip_frag, compl);
 }
 
 static struct be_rx_compl_info *be_rx_compl_get(struct be_rx_obj *rxo)
@@ -1620,6 +1622,9 @@ static struct be_rx_compl_info *be_rx_compl_get(struct be_rx_obj *rxo)
         else
                 be_parse_rx_compl_v0(compl, rxcp);
 
+        if (rxcp->ip_frag)
+                rxcp->l4_csum = 0;
+
         if (rxcp->vlanf) {
                 /* vlanf could be wrongly set in some cards.
                  * ignore if vtm is not set */
@@ -2168,7 +2173,7 @@ static irqreturn_t be_msix(int irq, void *dev)
 
 static inline bool do_gro(struct be_rx_compl_info *rxcp)
 {
-        return (rxcp->tcpf && !rxcp->err) ? true : false;
+        return (rxcp->tcpf && !rxcp->err && rxcp->l4_csum) ? true : false;
 }
 
 static int be_process_rx(struct be_rx_obj *rxo, struct napi_struct *napi,
@@ -4093,6 +4098,7 @@ static int be_get_initial_config(struct be_adapter *adapter)
 
 static int lancer_recover_func(struct be_adapter *adapter)
 {
+        struct device *dev = &adapter->pdev->dev;
         int status;
 
         status = lancer_test_and_set_rdy_state(adapter);
@@ -4104,8 +4110,7 @@ static int lancer_recover_func(struct be_adapter *adapter)
 
         be_clear(adapter);
 
-        adapter->hw_error = false;
-        adapter->fw_timeout = false;
+        be_clear_all_error(adapter);
 
         status = be_setup(adapter);
         if (status)
@@ -4117,13 +4122,13 @@ static int lancer_recover_func(struct be_adapter *adapter)
                         goto err;
         }
 
-        dev_err(&adapter->pdev->dev,
-                "Adapter SLIPORT recovery succeeded\n");
+        dev_err(dev, "Error recovery successful\n");
         return 0;
 err:
-        if (adapter->eeh_error)
-                dev_err(&adapter->pdev->dev,
-                        "Adapter SLIPORT recovery failed\n");
+        if (status == -EAGAIN)
+                dev_err(dev, "Waiting for resource provisioning\n");
+        else
+                dev_err(dev, "Error recovery failed\n");
 
         return status;
 }
@@ -4132,28 +4137,27 @@ static void be_func_recovery_task(struct work_struct *work)
 {
         struct be_adapter *adapter =
                 container_of(work, struct be_adapter,  func_recovery_work.work);
-        int status;
+        int status = 0;
 
         be_detect_error(adapter);
 
         if (adapter->hw_error && lancer_chip(adapter)) {
 
-                if (adapter->eeh_error)
-                        goto out;
-
                 rtnl_lock();
                 netif_device_detach(adapter->netdev);
                 rtnl_unlock();
 
                 status = lancer_recover_func(adapter);
-
                 if (!status)
                         netif_device_attach(adapter->netdev);
         }
 
-out:
-        schedule_delayed_work(&adapter->func_recovery_work,
-                              msecs_to_jiffies(1000));
+        /* In Lancer, for all errors other than provisioning error (-EAGAIN),
+         * no need to attempt further recovery.
+         */
+        if (!status || status == -EAGAIN)
+                schedule_delayed_work(&adapter->func_recovery_work,
+                                      msecs_to_jiffies(1000));
 }
 
 static void be_worker(struct work_struct *work)
@@ -4258,6 +4262,9 @@ static int be_probe(struct pci_dev *pdev, const struct pci_device_id *pdev_id)
                 netdev->features |= NETIF_F_HIGHDMA;
         } else {
                 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+                if (!status)
+                        status = dma_set_coherent_mask(&pdev->dev,
+                                                       DMA_BIT_MASK(32));
                 if (status) {
                         dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
                         goto free_netdev;
@@ -4436,20 +4443,19 @@ static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
 
         dev_err(&adapter->pdev->dev, "EEH error detected\n");
 
-        adapter->eeh_error = true;
+        if (!adapter->eeh_error) {
+                adapter->eeh_error = true;
 
-        cancel_delayed_work_sync(&adapter->func_recovery_work);
-
-        rtnl_lock();
-        netif_device_detach(netdev);
-        rtnl_unlock();
+                cancel_delayed_work_sync(&adapter->func_recovery_work);
 
-        if (netif_running(netdev)) {
                 rtnl_lock();
-                be_close(netdev);
+                netif_device_detach(netdev);
+                if (netif_running(netdev))
+                        be_close(netdev);
                 rtnl_unlock();
+
+                be_clear(adapter);
         }
-        be_clear(adapter);
 
         if (state == pci_channel_io_perm_failure)
                 return PCI_ERS_RESULT_DISCONNECT;
@@ -4474,7 +4480,6 @@ static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
         int status;
 
         dev_info(&adapter->pdev->dev, "EEH reset\n");
-        be_clear_all_error(adapter);
 
         status = pci_enable_device(pdev);
         if (status)
@@ -4492,6 +4497,7 @@ static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
                 return PCI_ERS_RESULT_DISCONNECT;
 
         pci_cleanup_aer_uncorrect_error_status(pdev);
+        be_clear_all_error(adapter);
         return PCI_ERS_RESULT_RECOVERED;
 }
 
diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index 85a06037b242..d48099f03b7f 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -516,6 +516,7 @@ fec_restart(struct net_device *ndev, int duplex)
         /* Set MII speed */
         writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
 
+#if !defined(CONFIG_M5272)
         /* set RX checksum */
         val = readl(fep->hwp + FEC_RACC);
         if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
@@ -523,6 +524,7 @@ fec_restart(struct net_device *ndev, int duplex)
         else
                 val &= ~FEC_RACC_OPTIONS;
         writel(val, fep->hwp + FEC_RACC);
+#endif
 
         /*
          * The phy interface and speed need to get configured
@@ -575,6 +577,7 @@ fec_restart(struct net_device *ndev, int duplex)
 #endif
         }
 
+#if !defined(CONFIG_M5272)
         /* enable pause frame*/
         if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
             ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
@@ -592,6 +595,7 @@ fec_restart(struct net_device *ndev, int duplex)
         } else {
                 rcntl &= ~FEC_ENET_FCE;
         }
+#endif /* !defined(CONFIG_M5272) */
 
         writel(rcntl, fep->hwp + FEC_R_CNTRL);
 
@@ -1038,6 +1042,18 @@ static void fec_get_mac(struct net_device *ndev)
                 iap = &tmpaddr[0];
         }
 
+        /*
+         * 5) random mac address
+         */
+        if (!is_valid_ether_addr(iap)) {
+                /* Report it and use a random ethernet address instead */
+                netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
+                eth_hw_addr_random(ndev);
+                netdev_info(ndev, "Using random MAC address: %pM\n",
+                            ndev->dev_addr);
+                return;
+        }
+
         memcpy(ndev->dev_addr, iap, ETH_ALEN);
 
         /* Adjust MAC if using macaddr */
@@ -1193,7 +1209,9 @@ static int fec_enet_mii_probe(struct net_device *ndev)
         /* mask with MAC supported features */
         if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
                 phy_dev->supported &= PHY_GBIT_FEATURES;
+#if !defined(CONFIG_M5272)
                 phy_dev->supported |= SUPPORTED_Pause;
+#endif
         }
         else
                 phy_dev->supported &= PHY_BASIC_FEATURES;
@@ -1378,6 +1396,8 @@ static int fec_enet_get_ts_info(struct net_device *ndev,
         }
 }
 
+#if !defined(CONFIG_M5272)
+
 static void fec_enet_get_pauseparam(struct net_device *ndev,
                                     struct ethtool_pauseparam *pause)
 {
@@ -1424,9 +1444,13 @@ static int fec_enet_set_pauseparam(struct net_device *ndev,
         return 0;
 }
 
+#endif /* !defined(CONFIG_M5272) */
+
 static const struct ethtool_ops fec_enet_ethtool_ops = {
+#if !defined(CONFIG_M5272)
         .get_pauseparam         = fec_enet_get_pauseparam,
         .set_pauseparam         = fec_enet_set_pauseparam,
+#endif
         .get_settings           = fec_enet_get_settings,
         .set_settings           = fec_enet_set_settings,
         .get_drvinfo            = fec_enet_get_drvinfo,
@@ -1862,10 +1886,12 @@ fec_probe(struct platform_device *pdev)
         /* setup board info structure */
         fep = netdev_priv(ndev);
 
+#if !defined(CONFIG_M5272)
         /* default enable pause frame auto negotiation */
         if (pdev->id_entry &&
             (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
                 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
+#endif
 
         fep->hwp = devm_request_and_ioremap(&pdev->dev, r);
         fep->pdev = pdev;
diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 2ad1494efbb3..d1cbfb12c1ca 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -1757,7 +1757,7 @@ static int rxq_init(struct mv643xx_eth_private *mp, int index)
         memset(rxq->rx_desc_area, 0, size);
 
         rxq->rx_desc_area_size = size;
-        rxq->rx_skb = kmalloc_array(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
+        rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
                                     GFP_KERNEL);
         if (rxq->rx_skb == NULL)
                 goto out_free;
diff --git a/drivers/net/ethernet/marvell/pxa168_eth.c b/drivers/net/ethernet/marvell/pxa168_eth.c
index 339bb323cb0c..1c8af8ba08d9 100644
--- a/drivers/net/ethernet/marvell/pxa168_eth.c
+++ b/drivers/net/ethernet/marvell/pxa168_eth.c
@@ -1015,7 +1015,7 @@ static int rxq_init(struct net_device *dev)
         int rx_desc_num = pep->rx_ring_size;
 
         /* Allocate RX skb rings */
-        pep->rx_skb = kmalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size,
+        pep->rx_skb = kzalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size,
                              GFP_KERNEL);
         if (!pep->rx_skb)
                 return -ENOMEM;
@@ -1076,7 +1076,7 @@ static int txq_init(struct net_device *dev)
         int size = 0, i = 0;
         int tx_desc_num = pep->tx_ring_size;
 
-        pep->tx_skb = kmalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size,
+        pep->tx_skb = kzalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size,
                              GFP_KERNEL);
         if (!pep->tx_skb)
                 return -ENOMEM;
diff --git a/drivers/net/ethernet/mellanox/mlx4/cmd.c b/drivers/net/ethernet/mellanox/mlx4/cmd.c
index 1df56cc50ee9..0e572a527154 100644
--- a/drivers/net/ethernet/mellanox/mlx4/cmd.c
+++ b/drivers/net/ethernet/mellanox/mlx4/cmd.c
@@ -222,8 +222,6 @@ static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
                  * FLR process. The only non-zero result in the RESET command
                  * is MLX4_DELAY_RESET_SLAVE*/
                 if ((MLX4_COMM_CMD_RESET == cmd)) {
-                        mlx4_warn(dev, "Got slave FLRed from Communication"
-                                  " channel (ret:0x%x)\n", ret_from_pending);
                         err = MLX4_DELAY_RESET_SLAVE;
                 } else {
                         mlx4_warn(dev, "Communication channel timed out\n");
diff --git a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
index b35f94700093..89c47ea84b50 100644
--- a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
+++ b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
@@ -1323,6 +1323,7 @@ static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
                         priv->last_moder_time[ring] = moder_time;
                         cq = &priv->rx_cq[ring];
                         cq->moder_time = moder_time;
+                        cq->moder_cnt = priv->rx_frames;
                         err = mlx4_en_set_cq_moder(priv, cq);
                         if (err)
                                 en_err(priv, "Failed modifying moderation for cq:%d\n",
@@ -2118,6 +2119,7 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
         struct mlx4_en_priv *priv;
         int i;
         int err;
+        u64 mac_u64;
 
         dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
                                  MAX_TX_RINGS, MAX_RX_RINGS);
@@ -2191,10 +2193,17 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
         dev->addr_len = ETH_ALEN;
         mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
         if (!is_valid_ether_addr(dev->dev_addr)) {
-                en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
-                       priv->port, dev->dev_addr);
-                err = -EINVAL;
-                goto out;
+                if (mlx4_is_slave(priv->mdev->dev)) {
+                        eth_hw_addr_random(dev);
+                        en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
+                        mac_u64 = mlx4_en_mac_to_u64(dev->dev_addr);
+                        mdev->dev->caps.def_mac[priv->port] = mac_u64;
+                } else {
+                        en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
+                               priv->port, dev->dev_addr);
+                        err = -EINVAL;
+                        goto out;
+                }
         }
 
         memcpy(priv->prev_mac, dev->dev_addr, sizeof(priv->prev_mac));
diff --git a/drivers/net/ethernet/mellanox/mlx4/fw.c b/drivers/net/ethernet/mellanox/mlx4/fw.c
index 58a8e535d698..2c97901c6a6d 100644
--- a/drivers/net/ethernet/mellanox/mlx4/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx4/fw.c
@@ -840,12 +840,16 @@ int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
                            MLX4_CMD_NATIVE);
 
         if (!err && dev->caps.function != slave) {
-                /* set slave default_mac address */
-                MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
-                def_mac += slave << 8;
                 /* if config MAC in DB use it */
                 if (priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac)
                         def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
+                else {
+                        /* set slave default_mac address */
+                        MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
+                        def_mac += slave << 8;
+                        priv->mfunc.master.vf_admin[slave].vport[vhcr->in_modifier].mac = def_mac;
+                }
+
                 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
 
                 /* get port type - currently only eth is enabled */
diff --git a/drivers/net/ethernet/mellanox/mlx4/main.c b/drivers/net/ethernet/mellanox/mlx4/main.c
index 0d32a82458bf..8a434997a0df 100644
--- a/drivers/net/ethernet/mellanox/mlx4/main.c
+++ b/drivers/net/ethernet/mellanox/mlx4/main.c
@@ -632,6 +632,9 @@ static int mlx4_slave_cap(struct mlx4_dev *dev)
                 dev->caps.cqe_size   = 32;
         }
 
+        dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
+        mlx4_warn(dev, "Timestamping is not supported in slave mode.\n");
+
         slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
 
         return 0;
@@ -1290,7 +1293,6 @@ static int mlx4_init_slave(struct mlx4_dev *dev)
 {
         struct mlx4_priv *priv = mlx4_priv(dev);
         u64 dma = (u64) priv->mfunc.vhcr_dma;
-        int num_of_reset_retries = NUM_OF_RESET_RETRIES;
         int ret_from_reset = 0;
         u32 slave_read;
         u32 cmd_channel_ver;
@@ -1304,18 +1306,10 @@ static int mlx4_init_slave(struct mlx4_dev *dev)
          * NUM_OF_RESET_RETRIES times before leaving.*/
         if (ret_from_reset) {
                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
-                        msleep(SLEEP_TIME_IN_RESET);
-                        while (ret_from_reset && num_of_reset_retries) {
-                                mlx4_warn(dev, "slave is currently in the"
-                                          "middle of FLR. retrying..."
-                                          "(try num:%d)\n",
-                                          (NUM_OF_RESET_RETRIES -
-                                           num_of_reset_retries  + 1));
-                                ret_from_reset =
-                                        mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
-                                                      0, MLX4_COMM_TIME);
-                                num_of_reset_retries = num_of_reset_retries - 1;
-                        }
+                        mlx4_warn(dev, "slave is currently in the "
+                                  "middle of FLR. Deferring probe.\n");
+                        mutex_unlock(&priv->cmd.slave_cmd_mutex);
+                        return -EPROBE_DEFER;
                 } else
                         goto err;
         }
@@ -1526,7 +1520,8 @@ static int mlx4_init_hca(struct mlx4_dev *dev)
         } else {
                 err = mlx4_init_slave(dev);
                 if (err) {
-                        mlx4_err(dev, "Failed to initialize slave\n");
+                        if (err != -EPROBE_DEFER)
+                                mlx4_err(dev, "Failed to initialize slave\n");
                         return err;
                 }
 
diff --git a/drivers/net/ethernet/octeon/octeon_mgmt.c b/drivers/net/ethernet/octeon/octeon_mgmt.c
index 921729f9c85c..91a8a5d28037 100644
--- a/drivers/net/ethernet/octeon/octeon_mgmt.c
+++ b/drivers/net/ethernet/octeon/octeon_mgmt.c
@@ -46,17 +46,25 @@
 union mgmt_port_ring_entry {
         u64 d64;
         struct {
-                u64    reserved_62_63:2;
+#define RING_ENTRY_CODE_DONE 0xf
+#define RING_ENTRY_CODE_MORE 0x10
+#ifdef __BIG_ENDIAN_BITFIELD
+                u64 reserved_62_63:2;
                 /* Length of the buffer/packet in bytes */
-                u64    len:14;
+                u64 len:14;
                 /* For TX, signals that the packet should be timestamped */
-                u64    tstamp:1;
+                u64 tstamp:1;
                 /* The RX error code */
-                u64    code:7;
-#define RING_ENTRY_CODE_DONE 0xf
-#define RING_ENTRY_CODE_MORE 0x10
+                u64 code:7;
                 /* Physical address of the buffer */
-                u64    addr:40;
+                u64 addr:40;
+#else
+                u64 addr:40;
+                u64 code:7;
+                u64 tstamp:1;
+                u64 len:14;
+                u64 reserved_62_63:2;
+#endif
         } s;
 };
 
@@ -1141,10 +1149,13 @@ static int octeon_mgmt_open(struct net_device *netdev)
                 /* For compensation state to lock. */
                 ndelay(1040 * NS_PER_PHY_CLK);
 
-                /* Some Ethernet switches cannot handle standard
-                 * Interframe Gap, increase to 16 bytes.
+                /* Default Interframe Gaps are too small.  Recommended
+                 * workaround is.
+                 *
+                 * AGL_GMX_TX_IFG[IFG1]=14
+                 * AGL_GMX_TX_IFG[IFG2]=10
                  */
-                cvmx_write_csr(CVMX_AGL_GMX_TX_IFG, 0x88);
+                cvmx_write_csr(CVMX_AGL_GMX_TX_IFG, 0xae);
         }
 
         octeon_mgmt_rx_fill_ring(netdev);
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c
index 43562c256379..6acf82b9f018 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c
@@ -642,7 +642,7 @@ void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter)
                                 qlcnic_83xx_config_intrpt(adapter, 0);
                 }
                 /* Allow dma queues to drain after context reset */
-                msleep(20);
+                mdelay(20);
         }
 }
 
diff --git a/drivers/net/ethernet/qlogic/qlge/qlge_main.c b/drivers/net/ethernet/qlogic/qlge/qlge_main.c
index 50235d201592..f87cc216045b 100644
--- a/drivers/net/ethernet/qlogic/qlge/qlge_main.c
+++ b/drivers/net/ethernet/qlogic/qlge/qlge_main.c
@@ -4717,6 +4717,7 @@ static int qlge_probe(struct pci_dev *pdev,
                 dev_err(&pdev->dev, "net device registration failed.\n");
                 ql_release_all(pdev);
                 pci_disable_device(pdev);
+                free_netdev(ndev);
                 return err;
         }
         /* Start up the timer to trigger EEH if
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index 42e9dd05c936..e29fe8dbd226 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -380,8 +380,9 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
         .eesipr_value   = 0x01ff009f,
 
         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
-        .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
-                          EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
+        .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
+                          EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
+                          EESR_ECI,
         .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 
         .apr            = 1,
@@ -427,8 +428,9 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
 
         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
-        .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
-                          EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
+        .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
+                          EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
+                          EESR_ECI,
         .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 
         .apr            = 1,
@@ -478,8 +480,9 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
         .rmcr_value     = 0x00000001,
 
         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
-        .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
-                          EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
+        .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
+                          EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
+                          EESR_ECI,
         .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 
         .apr            = 1,
@@ -592,9 +595,9 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 
         .tx_check       = EESR_TC1 | EESR_FTC,
-        .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
-                          EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
-                          EESR_ECI,
+        .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
+                          EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
+                          EESR_TDE | EESR_ECI,
         .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
                           EESR_TFE,
         .fdr_value      = 0x0000072f,
@@ -674,9 +677,9 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 
         .tx_check       = EESR_TC1 | EESR_FTC,
-        .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
-                          EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
-                          EESR_ECI,
+        .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
+                          EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
+                          EESR_TDE | EESR_ECI,
         .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
                           EESR_TFE,
 
@@ -811,9 +814,9 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 
         .tx_check       = EESR_TC1 | EESR_FTC,
-        .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
-                          EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
-                          EESR_ECI,
+        .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
+                          EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
+                          EESR_TDE | EESR_ECI,
         .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
                           EESR_TFE,
 
@@ -897,8 +900,8 @@ static int sh_eth_check_reset(struct net_device *ndev)
                 mdelay(1);
                 cnt--;
         }
-        if (cnt < 0) {
-                pr_err("Device reset fail\n");
+        if (cnt <= 0) {
+                pr_err("Device reset failed\n");
                 ret = -ETIMEDOUT;
         }
         return ret;
@@ -1401,16 +1404,23 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
                 pkt_len = rxdesc->frame_length;
 
-#if defined(CONFIG_ARCH_R8A7740)
-                desc_status >>= 16;
-#endif
-
                 if (--boguscnt < 0)
                         break;
 
                 if (!(desc_status & RDFEND))
                         ndev->stats.rx_length_errors++;
 
+#if defined(CONFIG_ARCH_R8A7740)
+                /*
+                 * In case of almost all GETHER/ETHERs, the Receive Frame State
+                 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
+                 * bit 0. However, in case of the R8A7740's GETHER, the RFS
+                 * bits are from bit 25 to bit 16. So, the driver needs right
+                 * shifting by 16.
+                 */
+                desc_status >>= 16;
+#endif
+
                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
                         ndev->stats.rx_errors++;
@@ -1542,11 +1552,12 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
 
 ignore_link:
         if (intr_status & EESR_TWB) {
-                /* Write buck end. unused write back interrupt */
-                if (intr_status & EESR_TABT)    /* Transmit Abort int */
+                /* Unused write back interrupt */
+                if (intr_status & EESR_TABT) {  /* Transmit Abort int */
                         ndev->stats.tx_aborted_errors++;
                         if (netif_msg_tx_err(mdp))
                                 dev_err(&ndev->dev, "Transmit Abort\n");
+                }
         }
 
         if (intr_status & EESR_RABT) {
diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
index 1ddc9f235bcb..62689a5823be 100644
--- a/drivers/net/ethernet/renesas/sh_eth.h
+++ b/drivers/net/ethernet/renesas/sh_eth.h
@@ -253,7 +253,7 @@ enum EESR_BIT {
 
 #define DEFAULT_TX_CHECK        (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
                                  EESR_RTO)
-#define DEFAULT_EESR_ERR_CHECK  (EESR_TWB | EESR_TABT | EESR_RABT | \
+#define DEFAULT_EESR_ERR_CHECK  (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \
                                  EESR_RDE | EESR_RFRMER | EESR_ADE | \
                                  EESR_TFE | EESR_TDE | EESR_ECI)
 #define DEFAULT_TX_ERROR_CHECK  (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
diff --git a/drivers/net/ethernet/sfc/efx.c b/drivers/net/ethernet/sfc/efx.c
index 39e4cb39de29..4a14a940c65e 100644
--- a/drivers/net/ethernet/sfc/efx.c
+++ b/drivers/net/ethernet/sfc/efx.c
@@ -2139,7 +2139,7 @@ show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
         return sprintf(buf, "%d\n", efx->phy_type);
 }
-static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL);
+static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL);
 
 static int efx_register_netdev(struct efx_nic *efx)
 {
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 7788fbe44f0a..95176979b2d2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -297,8 +297,8 @@ struct dma_features {
 #define MAC_RNABLE_RX           0x00000004      /* Receiver Enable */
 
 /* Default LPI timers */
-#define STMMAC_DEFAULT_LIT_LS_TIMER     0x3E8
-#define STMMAC_DEFAULT_TWT_LS_TIMER     0x0
+#define STMMAC_DEFAULT_LIT_LS   0x3E8
+#define STMMAC_DEFAULT_TWT_LS   0x0
 
 #define STMMAC_CHAIN_MODE       0x1
 #define STMMAC_RING_MODE        0x2
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 618446ae1ec1..e9eab29db7be 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -130,7 +130,7 @@ static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
-#define STMMAC_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
+#define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 
 /* By default the driver will use the ring mode to manage tx and rx descriptors
  * but passing this value so user can force to use the chain instead of the ring
@@ -288,7 +288,7 @@ static void stmmac_eee_ctrl_timer(unsigned long arg)
         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 
         stmmac_enable_eee_mode(priv);
-        mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
+        mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 }
 
 /**
@@ -304,22 +304,34 @@ bool stmmac_eee_init(struct stmmac_priv *priv)
 {
         bool ret = false;
 
+        /* Using PCS we cannot dial with the phy registers at this stage
+         * so we do not support extra feature like EEE.
+         */
+        if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
+            (priv->pcs == STMMAC_PCS_RTBI))
+                goto out;
+
         /* MAC core supports the EEE feature. */
         if (priv->dma_cap.eee) {
                 /* Check if the PHY supports EEE */
                 if (phy_init_eee(priv->phydev, 1))
                         goto out;
 
-                priv->eee_active = 1;
-                init_timer(&priv->eee_ctrl_timer);
-                priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
-                priv->eee_ctrl_timer.data = (unsigned long)priv;
-                priv->eee_ctrl_timer.expires = STMMAC_LPI_TIMER(eee_timer);
-                add_timer(&priv->eee_ctrl_timer);
-
-                priv->hw->mac->set_eee_timer(priv->ioaddr,
-                                             STMMAC_DEFAULT_LIT_LS_TIMER,
-                                             priv->tx_lpi_timer);
+                if (!priv->eee_active) {
+                        priv->eee_active = 1;
+                        init_timer(&priv->eee_ctrl_timer);
+                        priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
+                        priv->eee_ctrl_timer.data = (unsigned long)priv;
+                        priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
+                        add_timer(&priv->eee_ctrl_timer);
+
+                        priv->hw->mac->set_eee_timer(priv->ioaddr,
+                                                     STMMAC_DEFAULT_LIT_LS,
+                                                     priv->tx_lpi_timer);
+                } else
+                        /* Set HW EEE according to the speed */
+                        priv->hw->mac->set_eee_pls(priv->ioaddr,
+                                                   priv->phydev->link);
 
                 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
 
@@ -329,20 +341,6 @@ out:
         return ret;
 }
 
-/**
- * stmmac_eee_adjust: adjust HW EEE according to the speed
- * @priv: driver private structure
- * Description:
- *      When the EEE has been already initialised we have to
- *      modify the PLS bit in the LPI ctrl & status reg according
- *      to the PHY link status. For this reason.
- */
-static void stmmac_eee_adjust(struct stmmac_priv *priv)
-{
-        if (priv->eee_enabled)
-                priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link);
-}
-
 /* stmmac_get_tx_hwtstamp: get HW TX timestamps
  * @priv: driver private structure
  * @entry : descriptor index to be used.
@@ -769,7 +767,10 @@ static void stmmac_adjust_link(struct net_device *dev)
         if (new_state && netif_msg_link(priv))
                 phy_print_status(phydev);
 
-        stmmac_eee_adjust(priv);
+        /* At this stage, it could be needed to setup the EEE or adjust some
+         * MAC related HW registers.
+         */
+        priv->eee_enabled = stmmac_eee_init(priv);
 
         spin_unlock_irqrestore(&priv->lock, flags);
 
@@ -1277,7 +1278,7 @@ static void stmmac_tx_clean(struct stmmac_priv *priv)
 
         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
                 stmmac_enable_eee_mode(priv);
-                mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
+                mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
         }
         spin_unlock(&priv->tx_lock);
 }
@@ -1671,14 +1672,9 @@ static int stmmac_open(struct net_device *dev)
         if (priv->phydev)
                 phy_start(priv->phydev);
 
-        priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS_TIMER;
+        priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
 
-        /* Using PCS we cannot dial with the phy registers at this stage
-         * so we do not support extra feature like EEE.
-         */
-        if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
-            priv->pcs != STMMAC_PCS_RTBI)
-                priv->eee_enabled = stmmac_eee_init(priv);
+        priv->eee_enabled = stmmac_eee_init(priv);
 
         stmmac_init_tx_coalesce(priv);
 
@@ -1899,7 +1895,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
 
 #ifdef STMMAC_XMIT_DEBUG
         if (netif_msg_pktdata(priv)) {
-                pr_info("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d"
+                pr_info("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
                         __func__, (priv->cur_tx % txsize),
                         (priv->dirty_tx % txsize), entry, first, nfrags);
                 if (priv->extend_desc)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 21a5b291b4b3..d1a769f35f9d 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1679,7 +1679,7 @@ static int cpsw_probe(struct platform_device *pdev)
         priv->rx_packet_max = max(rx_packet_max, 128);
         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
         priv->irq_enabled = true;
-        if (!ndev) {
+        if (!priv->cpts) {
                 pr_err("error allocating cpts\n");
                 goto clean_ndev_ret;
         }
@@ -1973,9 +1973,12 @@ static int cpsw_suspend(struct device *dev)
 {
         struct platform_device  *pdev = to_platform_device(dev);
         struct net_device       *ndev = platform_get_drvdata(pdev);
+        struct cpsw_priv        *priv = netdev_priv(ndev);
 
         if (netif_running(ndev))
                 cpsw_ndo_stop(ndev);
+        soft_reset("sliver 0", &priv->slaves[0].sliver->soft_reset);
+        soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset);
         pm_runtime_put_sync(&pdev->dev);
 
         return 0;
diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c b/drivers/net/ethernet/ti/davinci_cpdma.c
index 49dfd592ac1e..053c84fd0853 100644
--- a/drivers/net/ethernet/ti/davinci_cpdma.c
+++ b/drivers/net/ethernet/ti/davinci_cpdma.c
@@ -705,6 +705,13 @@ int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
         }
 
         buffer = dma_map_single(ctlr->dev, data, len, chan->dir);
+        ret = dma_mapping_error(ctlr->dev, buffer);
+        if (ret) {
+                cpdma_desc_free(ctlr->pool, desc, 1);
+                ret = -EINVAL;
+                goto unlock_ret;
+        }
+
         mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
         cpdma_desc_to_port(chan, mode, directed);
 
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
index 12aec173564c..c47f0dbcebb5 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -449,10 +449,9 @@ static int davinci_mdio_suspend(struct device *dev)
         __raw_writel(ctrl, &data->regs->control);
         wait_for_idle(data);
 
-        pm_runtime_put_sync(data->dev);
-
         data->suspended = true;
         spin_unlock(&data->lock);
+        pm_runtime_put_sync(data->dev);
 
         return 0;
 }
@@ -460,15 +459,12 @@ static int davinci_mdio_suspend(struct device *dev)
 static int davinci_mdio_resume(struct device *dev)
 {
         struct davinci_mdio_data *data = dev_get_drvdata(dev);
-        u32 ctrl;
 
-        spin_lock(&data->lock);
         pm_runtime_get_sync(data->dev);
 
+        spin_lock(&data->lock);
         /* restart the scan state machine */
-        ctrl = __raw_readl(&data->regs->control);
-        ctrl |= CONTROL_ENABLE;
-        __raw_writel(ctrl, &data->regs->control);
+        __davinci_mdio_reset(data);
 
         data->suspended = false;
         spin_unlock(&data->lock);
@@ -477,8 +473,8 @@ static int davinci_mdio_resume(struct device *dev)
 }
 
 static const struct dev_pm_ops davinci_mdio_pm_ops = {
-        .suspend        = davinci_mdio_suspend,
-        .resume         = davinci_mdio_resume,
+        .suspend_late   = davinci_mdio_suspend,
+        .resume_early   = davinci_mdio_resume,
 };
 
 static const struct of_device_id davinci_mdio_of_mtable[] = {
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index 919b983114e9..b7268b3dae77 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -946,7 +946,8 @@ static int xemaclite_open(struct net_device *dev)
                 phy_write(lp->phy_dev, MII_CTRL1000, 0);
 
                 /* Advertise only 10 and 100mbps full/half duplex speeds */
-                phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL);
+                phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL |
+                          ADVERTISE_CSMA);
 
                 /* Restart auto negotiation */
                 bmcr = phy_read(lp->phy_dev, MII_BMCR);
diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c
index 088c55496191..4dccead586be 100644
--- a/drivers/net/hyperv/netvsc_drv.c
+++ b/drivers/net/hyperv/netvsc_drv.c
@@ -31,6 +31,7 @@
 #include <linux/inetdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
+#include <linux/if_vlan.h>
 #include <linux/in.h>
 #include <linux/slab.h>
 #include <net/arp.h>
@@ -284,7 +285,9 @@ int netvsc_recv_callback(struct hv_device *device_obj,
 
         skb->protocol = eth_type_trans(skb, net);
         skb->ip_summed = CHECKSUM_NONE;
-        skb->vlan_tci = packet->vlan_tci;
+        if (packet->vlan_tci & VLAN_TAG_PRESENT)
+                __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
+                                       packet->vlan_tci);
 
         net->stats.rx_packets++;
         net->stats.rx_bytes += packet->total_data_buflen;
diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c
index 1c502bb0c916..6e91931a1c2c 100644
--- a/drivers/net/macvlan.c
+++ b/drivers/net/macvlan.c
@@ -853,18 +853,24 @@ static int macvlan_changelink(struct net_device *dev,
                 struct nlattr *tb[], struct nlattr *data[])
 {
         struct macvlan_dev *vlan = netdev_priv(dev);
-        if (data && data[IFLA_MACVLAN_MODE])
-                vlan->mode = nla_get_u32(data[IFLA_MACVLAN_MODE]);
+
         if (data && data[IFLA_MACVLAN_FLAGS]) {
                 __u16 flags = nla_get_u16(data[IFLA_MACVLAN_FLAGS]);
                 bool promisc = (flags ^ vlan->flags) & MACVLAN_FLAG_NOPROMISC;
-
-                if (promisc && (flags & MACVLAN_FLAG_NOPROMISC))
-                        dev_set_promiscuity(vlan->lowerdev, -1);
-                else if (promisc && !(flags & MACVLAN_FLAG_NOPROMISC))
-                        dev_set_promiscuity(vlan->lowerdev, 1);
+                if (vlan->port->passthru && promisc) {
+                        int err;
+
+                        if (flags & MACVLAN_FLAG_NOPROMISC)
+                                err = dev_set_promiscuity(vlan->lowerdev, -1);
+                        else
+                                err = dev_set_promiscuity(vlan->lowerdev, 1);
+                        if (err < 0)
+                                return err;
+                }
                 vlan->flags = flags;
         }
+        if (data && data[IFLA_MACVLAN_MODE])
+                vlan->mode = nla_get_u32(data[IFLA_MACVLAN_MODE]);
         return 0;
 }
 
diff --git a/drivers/net/macvtap.c b/drivers/net/macvtap.c
index 59e9605de316..b6dd6a75919a 100644
--- a/drivers/net/macvtap.c
+++ b/drivers/net/macvtap.c
@@ -524,8 +524,10 @@ static int zerocopy_sg_from_iovec(struct sk_buff *skb, const struct iovec *from,
                         return -EMSGSIZE;
                 num_pages = get_user_pages_fast(base, size, 0, &page[i]);
                 if (num_pages != size) {
-                        for (i = 0; i < num_pages; i++)
-                                put_page(page[i]);
+                        int j;
+
+                        for (j = 0; j < num_pages; j++)
+                                put_page(page[i + j]);
                         return -EFAULT;
                 }
                 truesize = size * PAGE_SIZE;
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index c14f14741b3f..38f0b312ff85 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -1044,7 +1044,7 @@ int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable)
                 adv = mmd_eee_adv_to_ethtool_adv_t(eee_adv);
                 lp = mmd_eee_adv_to_ethtool_adv_t(eee_lp);
                 idx = phy_find_setting(phydev->speed, phydev->duplex);
-                if ((lp & adv & settings[idx].setting))
+                if (!(lp & adv & settings[idx].setting))
                         goto eee_exit;
 
                 if (clk_stop_enable) {
diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c
index 7c43261975bd..b3051052f3ad 100644
--- a/drivers/net/team/team.c
+++ b/drivers/net/team/team.c
@@ -1092,8 +1092,8 @@ static int team_port_add(struct team *team, struct net_device *port_dev)
         }
 
         port->index = -1;
-        team_port_enable(team, port);
         list_add_tail_rcu(&port->list, &team->port_list);
+        team_port_enable(team, port);
         __team_compute_features(team);
         __team_port_change_port_added(port, !!netif_carrier_ok(port_dev));
         __team_options_change_check(team);
@@ -2374,7 +2374,8 @@ static int team_nl_send_port_list_get(struct team *team, u32 portid, u32 seq,
         bool incomplete;
         int i;
 
-        port = list_first_entry(&team->port_list, struct team_port, list);
+        port = list_first_entry_or_null(&team->port_list,
+                                        struct team_port, list);
 
 start_again:
         err = __send_and_alloc_skb(&skb, team, portid, send_func);
@@ -2402,8 +2403,8 @@ start_again:
                 err = team_nl_fill_one_port_get(skb, one_port);
                 if (err)
                         goto errout;
-        } else {
-                list_for_each_entry(port, &team->port_list, list) {
+        } else if (port) {
+                list_for_each_entry_from(port, &team->port_list, list) {
                         err = team_nl_fill_one_port_get(skb, port);
                         if (err) {
                                 if (err == -EMSGSIZE) {
diff --git a/drivers/net/team/team_mode_random.c b/drivers/net/team/team_mode_random.c
index 5ca14d463ba7..7f032e211343 100644
--- a/drivers/net/team/team_mode_random.c
+++ b/drivers/net/team/team_mode_random.c
@@ -28,6 +28,8 @@ static bool rnd_transmit(struct team *team, struct sk_buff *skb)
 
         port_index = random_N(team->en_port_count);
         port = team_get_port_by_index_rcu(team, port_index);
+        if (unlikely(!port))
+                goto drop;
         port = team_get_first_port_txable_rcu(team, port);
         if (unlikely(!port))
                 goto drop;
diff --git a/drivers/net/team/team_mode_roundrobin.c b/drivers/net/team/team_mode_roundrobin.c
index d268e4de781b..472623f8ce3d 100644
--- a/drivers/net/team/team_mode_roundrobin.c
+++ b/drivers/net/team/team_mode_roundrobin.c
@@ -32,6 +32,8 @@ static bool rr_transmit(struct team *team, struct sk_buff *skb)
 
         port_index = rr_priv(team)->sent_packets++ % team->en_port_count;
         port = team_get_port_by_index_rcu(team, port_index);
+        if (unlikely(!port))
+                goto drop;
         port = team_get_first_port_txable_rcu(team, port);
         if (unlikely(!port))
                 goto drop;
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index f042b0373e5d..9c61f8734a40 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -352,7 +352,7 @@ static u16 tun_select_queue(struct net_device *dev, struct sk_buff *skb)
         u32 numqueues = 0;
 
         rcu_read_lock();
-        numqueues = tun->numqueues;
+        numqueues = ACCESS_ONCE(tun->numqueues);
 
         txq = skb_get_rxhash(skb);
         if (txq) {
@@ -1010,8 +1010,10 @@ static int zerocopy_sg_from_iovec(struct sk_buff *skb, const struct iovec *from,
                         return -EMSGSIZE;
                 num_pages = get_user_pages_fast(base, size, 0, &page[i]);
                 if (num_pages != size) {
-                        for (i = 0; i < num_pages; i++)
-                                put_page(page[i]);
+                        int j;
+
+                        for (j = 0; j < num_pages; j++)
+                                put_page(page[i + j]);
                         return -EFAULT;
                 }
                 truesize = size * PAGE_SIZE;
@@ -1585,6 +1587,10 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr)
                 else
                         return -EINVAL;
 
+                if (!!(ifr->ifr_flags & IFF_MULTI_QUEUE) !=
+                    !!(tun->flags & TUN_TAP_MQ))
+                        return -EINVAL;
+
                 if (tun_not_capable(tun))
                         return -EPERM;
                 err = security_tun_dev_open(tun->security);
@@ -2155,6 +2161,8 @@ static int tun_chr_open(struct inode *inode, struct file * file)
         set_bit(SOCK_EXTERNALLY_ALLOCATED, &tfile->socket.flags);
         INIT_LIST_HEAD(&tfile->next);
 
+        sock_set_flag(&tfile->sk, SOCK_ZEROCOPY);
+
         return 0;
 }
 
diff --git a/drivers/net/usb/cdc_ether.c b/drivers/net/usb/cdc_ether.c
index 078795fe6e31..04ee044dde51 100644
--- a/drivers/net/usb/cdc_ether.c
+++ b/drivers/net/usb/cdc_ether.c
@@ -627,6 +627,12 @@ static const struct usb_device_id	products [] = {
         .driver_info = 0,
 },
 
+/* Huawei E1820 - handled by qmi_wwan */
+{
+        USB_DEVICE_INTERFACE_NUMBER(HUAWEI_VENDOR_ID, 0x14ac, 1),
+        .driver_info = 0,
+},
+
 /* Realtek RTL8152 Based USB 2.0 Ethernet Adapters */
 #if defined(CONFIG_USB_RTL8152) || defined(CONFIG_USB_RTL8152_MODULE)
 {
diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
index 86adfa0a912e..56459215a22b 100644
--- a/drivers/net/usb/qmi_wwan.c
+++ b/drivers/net/usb/qmi_wwan.c
@@ -519,6 +519,7 @@ static const struct usb_device_id products[] = {
         /* 3. Combined interface devices matching on interface number */
         {QMI_FIXED_INTF(0x0408, 0xea42, 4)},    /* Yota / Megafon M100-1 */
         {QMI_FIXED_INTF(0x12d1, 0x140c, 1)},    /* Huawei E173 */
+        {QMI_FIXED_INTF(0x12d1, 0x14ac, 1)},    /* Huawei E1820 */
         {QMI_FIXED_INTF(0x19d2, 0x0002, 1)},
         {QMI_FIXED_INTF(0x19d2, 0x0012, 1)},
         {QMI_FIXED_INTF(0x19d2, 0x0017, 3)},
@@ -589,7 +590,13 @@ static const struct usb_device_id products[] = {
         {QMI_GOBI1K_DEVICE(0x03f0, 0x1f1d)},    /* HP un2400 Gobi Modem Device */
         {QMI_GOBI1K_DEVICE(0x04da, 0x250d)},    /* Panasonic Gobi Modem device */
         {QMI_GOBI1K_DEVICE(0x413c, 0x8172)},    /* Dell Gobi Modem device */
-        {QMI_GOBI1K_DEVICE(0x1410, 0xa001)},    /* Novatel Gobi Modem device */
+        {QMI_GOBI1K_DEVICE(0x1410, 0xa001)},    /* Novatel/Verizon USB-1000 */
+        {QMI_GOBI1K_DEVICE(0x1410, 0xa002)},    /* Novatel Gobi Modem device */
+        {QMI_GOBI1K_DEVICE(0x1410, 0xa003)},    /* Novatel Gobi Modem device */
+        {QMI_GOBI1K_DEVICE(0x1410, 0xa004)},    /* Novatel Gobi Modem device */
+        {QMI_GOBI1K_DEVICE(0x1410, 0xa005)},    /* Novatel Gobi Modem device */
+        {QMI_GOBI1K_DEVICE(0x1410, 0xa006)},    /* Novatel Gobi Modem device */
+        {QMI_GOBI1K_DEVICE(0x1410, 0xa007)},    /* Novatel Gobi Modem device */
         {QMI_GOBI1K_DEVICE(0x0b05, 0x1776)},    /* Asus Gobi Modem device */
         {QMI_GOBI1K_DEVICE(0x19d2, 0xfff3)},    /* ONDA Gobi Modem device */
         {QMI_GOBI1K_DEVICE(0x05c6, 0x9001)},    /* Generic Gobi Modem device */
diff --git a/drivers/net/vxlan.c b/drivers/net/vxlan.c
index 3b1d2ee7156b..57325f356d4f 100644
--- a/drivers/net/vxlan.c
+++ b/drivers/net/vxlan.c
@@ -565,18 +565,22 @@ skip:
 
 /* Watch incoming packets to learn mapping between Ethernet address
  * and Tunnel endpoint.
+ * Return true if packet is bogus and should be droppped.
  */
-static void vxlan_snoop(struct net_device *dev,
+static bool vxlan_snoop(struct net_device *dev,
                         __be32 src_ip, const u8 *src_mac)
 {
         struct vxlan_dev *vxlan = netdev_priv(dev);
         struct vxlan_fdb *f;
-        int err;
 
         f = vxlan_find_mac(vxlan, src_mac);
         if (likely(f)) {
                 if (likely(f->remote.remote_ip == src_ip))
-                        return;
+                        return false;
+
+                /* Don't migrate static entries, drop packets */
+                if (f->state & NUD_NOARP)
+                        return true;
 
                 if (net_ratelimit())
                         netdev_info(dev,
@@ -588,14 +592,19 @@ static void vxlan_snoop(struct net_device *dev,
         } else {
                 /* learned new entry */
                 spin_lock(&vxlan->hash_lock);
-                err = vxlan_fdb_create(vxlan, src_mac, src_ip,
-                                       NUD_REACHABLE,
-                                       NLM_F_EXCL|NLM_F_CREATE,
-                                       vxlan->dst_port,
-                                       vxlan->default_dst.remote_vni,
-                                       0, NTF_SELF);
+
+                /* close off race between vxlan_flush and incoming packets */
+                if (netif_running(dev))
+                        vxlan_fdb_create(vxlan, src_mac, src_ip,
+                                         NUD_REACHABLE,
+                                         NLM_F_EXCL|NLM_F_CREATE,
+                                         vxlan->dst_port,
+                                         vxlan->default_dst.remote_vni,
+                                         0, NTF_SELF);
                 spin_unlock(&vxlan->hash_lock);
         }
+
+        return false;
 }
 
 
@@ -727,8 +736,9 @@ static int vxlan_udp_encap_recv(struct sock *sk, struct sk_buff *skb)
                                vxlan->dev->dev_addr) == 0)
                 goto drop;
 
-        if (vxlan->flags & VXLAN_F_LEARN)
-                vxlan_snoop(skb->dev, oip->saddr, eth_hdr(skb)->h_source);
+        if ((vxlan->flags & VXLAN_F_LEARN) &&
+            vxlan_snoop(skb->dev, oip->saddr, eth_hdr(skb)->h_source))
+                goto drop;
 
         __skb_tunnel_rx(skb, vxlan->dev);
         skb_reset_network_header(skb);
@@ -1151,9 +1161,11 @@ static netdev_tx_t vxlan_xmit(struct sk_buff *skb, struct net_device *dev)
                 struct sk_buff *skb1;
 
                 skb1 = skb_clone(skb, GFP_ATOMIC);
-                rc1 = vxlan_xmit_one(skb1, dev, rdst, did_rsc);
-                if (rc == NETDEV_TX_OK)
-                        rc = rc1;
+                if (skb1) {
+                        rc1 = vxlan_xmit_one(skb1, dev, rdst, did_rsc);
+                        if (rc == NETDEV_TX_OK)
+                                rc = rc1;
+                }
         }
 
         rc1 = vxlan_xmit_one(skb, dev, rdst0, did_rsc);
diff --git a/drivers/net/wan/dlci.c b/drivers/net/wan/dlci.c
index 147614ed86aa..6a8a382c5f4c 100644
--- a/drivers/net/wan/dlci.c
+++ b/drivers/net/wan/dlci.c
@@ -384,21 +384,37 @@ static int dlci_del(struct dlci_add *dlci)
         struct frad_local       *flp;
         struct net_device       *master, *slave;
         int                     err;
+        bool                    found = false;
+
+        rtnl_lock();
 
         /* validate slave device */
         master = __dev_get_by_name(&init_net, dlci->devname);
-        if (!master)
-                return -ENODEV;
+        if (!master) {
+                err = -ENODEV;
+                goto out;
+        }
+
+        list_for_each_entry(dlp, &dlci_devs, list) {
+                if (dlp->master == master) {
+                        found = true;
+                        break;
+                }
+        }
+        if (!found) {
+                err = -ENODEV;
+                goto out;
+        }
 
         if (netif_running(master)) {
-                return -EBUSY;
+                err = -EBUSY;
+                goto out;
         }
 
         dlp = netdev_priv(master);
         slave = dlp->slave;
         flp = netdev_priv(slave);
 
-        rtnl_lock();
         err = (*flp->deassoc)(slave, master);
         if (!err) {
                 list_del(&dlp->list);
@@ -407,8 +423,8 @@ static int dlci_del(struct dlci_add *dlci)
 
                 dev_put(slave);
         }
+out:
         rtnl_unlock();
-
         return err;
 }
 
diff --git a/drivers/net/wireless/ath/ath9k/Kconfig b/drivers/net/wireless/ath/ath9k/Kconfig
index f3dc124c60c7..3c2cbc9d6295 100644
--- a/drivers/net/wireless/ath/ath9k/Kconfig
+++ b/drivers/net/wireless/ath/ath9k/Kconfig
@@ -92,13 +92,17 @@ config ATH9K_MAC_DEBUG
           This option enables collection of statistics for Rx/Tx status
           data and some other MAC related statistics
 
-config ATH9K_RATE_CONTROL
+config ATH9K_LEGACY_RATE_CONTROL
         bool "Atheros ath9k rate control"
         depends on ATH9K
-        default y
+        default n
         ---help---
           Say Y, if you want to use the ath9k specific rate control
-          module instead of minstrel_ht.
+          module instead of minstrel_ht. Be warned that there are various
+          issues with the ath9k RC and minstrel is a more robust algorithm.
+          Note that even if this option is selected, "ath9k_rate_control"
+          has to be passed to mac80211 using the module parameter,
+          ieee80211_default_rc_algo.
 
 config ATH9K_HTC
        tristate "Atheros HTC based wireless cards support"
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index 2ad8f9474ba1..75ee9e7704ce 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -8,7 +8,7 @@ ath9k-y +=	beacon.o \
                 antenna.o
 
 ath9k-$(CONFIG_ATH9K_BTCOEX_SUPPORT) += mci.o
-ath9k-$(CONFIG_ATH9K_RATE_CONTROL) += rc.o
+ath9k-$(CONFIG_ATH9K_LEGACY_RATE_CONTROL) += rc.o
 ath9k-$(CONFIG_ATH9K_PCI) += pci.o
 ath9k-$(CONFIG_ATH9K_AHB) += ahb.o
 ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index db5ffada2217..7546b9a7dcbf 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -958,11 +958,11 @@ static const u32 ar9300Common_rx_gain_table_2p2[][2] = {
         {0x0000a074, 0x00000000},
         {0x0000a078, 0x00000000},
         {0x0000a07c, 0x00000000},
-        {0x0000a080, 0x1a1a1a1a},
-        {0x0000a084, 0x1a1a1a1a},
-        {0x0000a088, 0x1a1a1a1a},
-        {0x0000a08c, 0x1a1a1a1a},
-        {0x0000a090, 0x171a1a1a},
+        {0x0000a080, 0x22222229},
+        {0x0000a084, 0x1d1d1d1d},
+        {0x0000a088, 0x1d1d1d1d},
+        {0x0000a08c, 0x1d1d1d1d},
+        {0x0000a090, 0x171d1d1d},
         {0x0000a094, 0x11111717},
         {0x0000a098, 0x00030311},
         {0x0000a09c, 0x00000000},
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
index 54ba42f4108a..874f6570bd1c 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -68,13 +68,16 @@
 #define AR9300_BASE_ADDR 0x3ff
 #define AR9300_BASE_ADDR_512 0x1ff
 
-#define AR9300_OTP_BASE                 (AR_SREV_9340(ah) ? 0x30000 : 0x14000)
-#define AR9300_OTP_STATUS               (AR_SREV_9340(ah) ? 0x30018 : 0x15f18)
+#define AR9300_OTP_BASE \
+                ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30000 : 0x14000)
+#define AR9300_OTP_STATUS \
+                ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30018 : 0x15f18)
 #define AR9300_OTP_STATUS_TYPE          0x7
 #define AR9300_OTP_STATUS_VALID         0x4
 #define AR9300_OTP_STATUS_ACCESS_BUSY   0x2
 #define AR9300_OTP_STATUS_SM_BUSY       0x1
-#define AR9300_OTP_READ_DATA            (AR_SREV_9340(ah) ? 0x3001c : 0x15f1c)
+#define AR9300_OTP_READ_DATA \
+                ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x3001c : 0x15f1c)
 
 enum targetPowerHTRates {
         HT_TARGET_RATE_0_8_16,
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 2bf6548dd143..e1714d7c9eeb 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -334,7 +334,8 @@ static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 
-        if (REG_READ_FIELD(ah, AR_PHY_MODE,
+        if (!AR_SREV_9340(ah) &&
+            REG_READ_FIELD(ah, AR_PHY_MODE,
                            AR_PHY_MODE_DYNAMIC) == 0x1)
                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 366002f266f8..42b03dc39d14 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -251,10 +251,9 @@ struct ath_atx_tid {
         int tidno;
         int baw_head;   /* first un-acked tx buffer */
         int baw_tail;   /* next unused tx buffer slot */
-        int sched;
-        int paused;
-        u8 state;
-        bool stop_cb;
+        bool sched;
+        bool paused;
+        bool active;
 };
 
 struct ath_node {
@@ -275,10 +274,6 @@ struct ath_node {
 #endif
 };
 
-#define AGGR_CLEANUP         BIT(1)
-#define AGGR_ADDBA_COMPLETE  BIT(2)
-#define AGGR_ADDBA_PROGRESS  BIT(3)
-
 struct ath_tx_control {
         struct ath_txq *txq;
         struct ath_node *an;
@@ -352,8 +347,7 @@ void ath_tx_tasklet(struct ath_softc *sc);
 void ath_tx_edma_tasklet(struct ath_softc *sc);
 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
                       u16 tid, u16 *ssn);
-bool ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid,
-                      bool flush);
+void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 
 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
index 0743a47cef8f..62f1b7636c92 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
@@ -1174,7 +1174,7 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
                 mutex_lock(&priv->htc_pm_lock);
 
                 priv->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
-                if (priv->ps_idle)
+                if (!priv->ps_idle)
                         chip_reset = true;
 
                 mutex_unlock(&priv->htc_pm_lock);
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 7f25da8444fe..15dfefcf2d0f 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1172,6 +1172,7 @@ u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
+        int txbuf_size;
 
         ENABLE_REGWRITE_BUFFER(ah);
 
@@ -1225,13 +1226,17 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
                  * So set the usable tx buf size also to half to
                  * avoid data/delimiter underruns
                  */
-                REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
-                          AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
-        } else if (!AR_SREV_9271(ah)) {
-                REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
-                          AR_PCU_TXBUF_CTRL_USABLE_SIZE);
+                txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
+        } else if (AR_SREV_9340_13_OR_LATER(ah)) {
+                /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
+                txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
+        } else {
+                txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
         }
 
+        if (!AR_SREV_9271(ah))
+                REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
+
         REGWRITE_BUFFER_FLUSH(ah);
 
         if (AR_SREV_9300_20_OR_LATER(ah))
@@ -1306,9 +1311,13 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
         } else {
                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
-                if (tmpReg &
-                    (AR_INTR_SYNC_LOCAL_TIMEOUT |
-                     AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
+                if (AR_SREV_9340(ah))
+                        tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
+                else
+                        tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
+                                  AR_INTR_SYNC_RADM_CPL_TIMEOUT;
+
+                if (tmpReg) {
                         u32 val;
                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
 
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index aba415103f94..2ba494567777 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -787,8 +787,7 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
         hw->wiphy->iface_combinations = if_comb;
         hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
 
-        if (AR_SREV_5416(sc->sc_ah))
-                hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
+        hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
 
         hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
@@ -830,10 +829,6 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
         sc->ant_rx = hw->wiphy->available_antennas_rx;
         sc->ant_tx = hw->wiphy->available_antennas_tx;
 
-#ifdef CONFIG_ATH9K_RATE_CONTROL
-        hw->rate_control_algorithm = "ath9k_rate_control";
-#endif
-
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
                         &sc->sbands[IEEE80211_BAND_2GHZ];
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 498fee04afa0..566109a40fb3 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -410,7 +410,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
 
         REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
 
-        if (AR_SREV_9340(ah))
+        if (AR_SREV_9340(ah) && !AR_SREV_9340_13_OR_LATER(ah))
                 REG_WRITE(ah, AR_DMISC(q),
                           AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
         else
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 2382d1262e7f..5092ecae7706 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -1709,7 +1709,8 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
                 flush = true;
         case IEEE80211_AMPDU_TX_STOP_CONT:
                 ath9k_ps_wakeup(sc);
-                if (ath_tx_aggr_stop(sc, sta, tid, flush))
+                ath_tx_aggr_stop(sc, sta, tid);
+                if (!flush)
                         ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
                 ath9k_ps_restore(sc);
                 break;
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index aa4d368d8d3d..7eb1f4b458e4 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -1227,10 +1227,7 @@ static bool ath_tx_aggr_check(struct ath_softc *sc, struct ieee80211_sta *sta,
                 return false;
 
         txtid = ATH_AN_2_TID(an, tidno);
-
-        if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
-                        return true;
-        return false;
+        return !txtid->active;
 }
 
 
diff --git a/drivers/net/wireless/ath/ath9k/rc.h b/drivers/net/wireless/ath/ath9k/rc.h
index 267dbfcfaa96..b9a87383cb43 100644
--- a/drivers/net/wireless/ath/ath9k/rc.h
+++ b/drivers/net/wireless/ath/ath9k/rc.h
@@ -231,7 +231,7 @@ static inline void ath_debug_stat_retries(struct ath_rate_priv *rc, int rix,
 }
 #endif
 
-#ifdef CONFIG_ATH9K_RATE_CONTROL
+#ifdef CONFIG_ATH9K_LEGACY_RATE_CONTROL
 int ath_rate_control_register(void);
 void ath_rate_control_unregister(void);
 #else
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 5c4ab5026dca..f7c90cc58d56 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -798,6 +798,10 @@
 #define AR_SREV_REVISION_9485_10        0
 #define AR_SREV_REVISION_9485_11        1
 #define AR_SREV_VERSION_9340            0x300
+#define AR_SREV_REVISION_9340_10        0
+#define AR_SREV_REVISION_9340_11        1
+#define AR_SREV_REVISION_9340_12        2
+#define AR_SREV_REVISION_9340_13        3
 #define AR_SREV_VERSION_9580            0x1C0
 #define AR_SREV_REVISION_9580_10        4 /* AR9580 1.0 */
 #define AR_SREV_VERSION_9462            0x280
@@ -897,6 +901,10 @@
 #define AR_SREV_9340(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))
 
+#define AR_SREV_9340_13_OR_LATER(_ah) \
+        (AR_SREV_9340((_ah)) && \
+         ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9340_13))
+
 #define AR_SREV_9285E_20(_ah) \
     (AR_SREV_9285_12_OR_LATER(_ah) && \
      ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
@@ -1007,6 +1015,8 @@ enum {
                                 AR_INTR_SYNC_LOCAL_TIMEOUT |
                                 AR_INTR_SYNC_MAC_SLEEP_ACCESS),
 
+        AR9340_INTR_SYNC_LOCAL_TIMEOUT = 0x00000010,
+
         AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF,
 
 };
@@ -1881,6 +1891,7 @@ enum {
 #define AR_PCU_TXBUF_CTRL_SIZE_MASK     0x7FF
 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE   0x700
 #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE   0x380
+#define AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE   0x500
 
 #define AR_PCU_MISC_MODE2               0x8344
 #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE           0x00000002
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 14bb3354ea64..83ab6be3fe6d 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -125,24 +125,6 @@ static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
         list_add_tail(&ac->list, &txq->axq_acq);
 }
 
-static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
-{
-        struct ath_txq *txq = tid->ac->txq;
-
-        WARN_ON(!tid->paused);
-
-        ath_txq_lock(sc, txq);
-        tid->paused = false;
-
-        if (skb_queue_empty(&tid->buf_q))
-                goto unlock;
-
-        ath_tx_queue_tid(txq, tid);
-        ath_txq_schedule(sc, txq);
-unlock:
-        ath_txq_unlock_complete(sc, txq);
-}
-
 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
 {
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
@@ -164,20 +146,7 @@ static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
                                ARRAY_SIZE(bf->rates));
 }
 
-static void ath_tx_clear_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
-{
-        tid->state &= ~AGGR_ADDBA_COMPLETE;
-        tid->state &= ~AGGR_CLEANUP;
-        if (!tid->stop_cb)
-                return;
-
-        ieee80211_start_tx_ba_cb_irqsafe(tid->an->vif, tid->an->sta->addr,
-                                         tid->tidno);
-        tid->stop_cb = false;
-}
-
-static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid,
-                             bool flush_packets)
+static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
 {
         struct ath_txq *txq = tid->ac->txq;
         struct sk_buff *skb;
@@ -194,15 +163,16 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid,
         while ((skb = __skb_dequeue(&tid->buf_q))) {
                 fi = get_frame_info(skb);
                 bf = fi->bf;
-                if (!bf && !flush_packets)
-                        bf = ath_tx_setup_buffer(sc, txq, tid, skb);
 
                 if (!bf) {
-                        ieee80211_free_txskb(sc->hw, skb);
-                        continue;
+                        bf = ath_tx_setup_buffer(sc, txq, tid, skb);
+                        if (!bf) {
+                                ieee80211_free_txskb(sc->hw, skb);
+                                continue;
+                        }
                 }
 
-                if (fi->retries || flush_packets) {
+                if (fi->retries) {
                         list_add_tail(&bf->list, &bf_head);
                         ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
@@ -213,10 +183,7 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid,
                 }
         }
 
-        if (tid->baw_head == tid->baw_tail)
-                ath_tx_clear_tid(sc, tid);
-
-        if (sendbar && !flush_packets) {
+        if (sendbar) {
                 ath_txq_unlock(sc, txq);
                 ath_send_bar(tid, tid->seq_start);
                 ath_txq_lock(sc, txq);
@@ -499,19 +466,19 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 tx_info = IEEE80211_SKB_CB(skb);
                 fi = get_frame_info(skb);
 
-                if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
+                if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
+                        /*
+                         * Outside of the current BlockAck window,
+                         * maybe part of a previous session
+                         */
+                        txfail = 1;
+                } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
                         /* transmit completion, subframe is
                          * acked by block ack */
                         acked_cnt++;
                 } else if (!isaggr && txok) {
                         /* transmit completion */
                         acked_cnt++;
-                } else if (tid->state & AGGR_CLEANUP) {
-                        /*
-                         * cleanup in progress, just fail
-                         * the un-acked sub-frames
-                         */
-                        txfail = 1;
                 } else if (flush) {
                         txpending = 1;
                 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
@@ -535,7 +502,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 if (bf_next != NULL || !bf_last->bf_stale)
                         list_move_tail(&bf->list, &bf_head);
 
-                if (!txpending || (tid->state & AGGR_CLEANUP)) {
+                if (!txpending) {
                         /*
                          * complete the acked-ones/xretried ones; update
                          * block-ack window
@@ -609,9 +576,6 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 ath_txq_lock(sc, txq);
         }
 
-        if (tid->state & AGGR_CLEANUP)
-                ath_tx_flush_tid(sc, tid, false);
-
         rcu_read_unlock();
 
         if (needreset)
@@ -1244,9 +1208,6 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
         an = (struct ath_node *)sta->drv_priv;
         txtid = ATH_AN_2_TID(an, tid);
 
-        if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
-                return -EAGAIN;
-
         /* update ampdu factor/density, they may have changed. This may happen
          * in HT IBSS when a beacon with HT-info is received after the station
          * has already been added.
@@ -1258,7 +1219,7 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
                 an->mpdudensity = density;
         }
 
-        txtid->state |= AGGR_ADDBA_PROGRESS;
+        txtid->active = true;
         txtid->paused = true;
         *ssn = txtid->seq_start = txtid->seq_next;
         txtid->bar_index = -1;
@@ -1269,45 +1230,17 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
         return 0;
 }
 
-bool ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid,
-                      bool flush)
+void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
 {
         struct ath_node *an = (struct ath_node *)sta->drv_priv;
         struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
         struct ath_txq *txq = txtid->ac->txq;
-        bool ret = !flush;
-
-        if (flush)
-                txtid->stop_cb = false;
-
-        if (txtid->state & AGGR_CLEANUP)
-                return false;
-
-        if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
-                txtid->state &= ~AGGR_ADDBA_PROGRESS;
-                return ret;
-        }
 
         ath_txq_lock(sc, txq);
+        txtid->active = false;
         txtid->paused = true;
-
-        /*
-         * If frames are still being transmitted for this TID, they will be
-         * cleaned up during tx completion. To prevent race conditions, this
-         * TID can only be reused after all in-progress subframes have been
-         * completed.
-         */
-        if (txtid->baw_head != txtid->baw_tail) {
-                txtid->state |= AGGR_CLEANUP;
-                ret = false;
-                txtid->stop_cb = !flush;
-        } else {
-                txtid->state &= ~AGGR_ADDBA_COMPLETE;
-        }
-
-        ath_tx_flush_tid(sc, txtid, flush);
+        ath_tx_flush_tid(sc, txtid);
         ath_txq_unlock_complete(sc, txq);
-        return ret;
 }
 
 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
@@ -1371,18 +1304,28 @@ void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
         }
 }
 
-void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
+void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
+                        u16 tidno)
 {
-        struct ath_atx_tid *txtid;
+        struct ath_atx_tid *tid;
         struct ath_node *an;
+        struct ath_txq *txq;
 
         an = (struct ath_node *)sta->drv_priv;
+        tid = ATH_AN_2_TID(an, tidno);
+        txq = tid->ac->txq;
 
-        txtid = ATH_AN_2_TID(an, tid);
-        txtid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
-        txtid->state |= AGGR_ADDBA_COMPLETE;
-        txtid->state &= ~AGGR_ADDBA_PROGRESS;
-        ath_tx_resume_tid(sc, txtid);
+        ath_txq_lock(sc, txq);
+
+        tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
+        tid->paused = false;
+
+        if (!skb_queue_empty(&tid->buf_q)) {
+                ath_tx_queue_tid(txq, tid);
+                ath_txq_schedule(sc, txq);
+        }
+
+        ath_txq_unlock_complete(sc, txq);
 }
 
 /********************/
@@ -1627,6 +1570,8 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
             txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
                 return;
 
+        rcu_read_lock();
+
         ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
         last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
 
@@ -1665,8 +1610,10 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
 
                 if (ac == last_ac ||
                     txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
-                        return;
+                        break;
         }
+
+        rcu_read_unlock();
 }
 
 /***********/
@@ -2431,13 +2378,10 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
                 tid->baw_head  = tid->baw_tail = 0;
                 tid->sched     = false;
                 tid->paused    = false;
-                tid->state &= ~AGGR_CLEANUP;
+                tid->active        = false;
                 __skb_queue_head_init(&tid->buf_q);
                 acno = TID_TO_WME_AC(tidno);
                 tid->ac = &an->ac[acno];
-                tid->state &= ~AGGR_ADDBA_COMPLETE;
-                tid->state &= ~AGGR_ADDBA_PROGRESS;
-                tid->stop_cb = false;
         }
 
         for (acno = 0, ac = &an->ac[acno];
@@ -2474,7 +2418,7 @@ void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
                 }
 
                 ath_tid_drain(sc, txq, tid);
-                ath_tx_clear_tid(sc, tid);
+                tid->active = false;
 
                 ath_txq_unlock(sc, txq);
         }
diff --git a/drivers/net/wireless/atmel.c b/drivers/net/wireless/atmel.c
index 830bb1d1f957..b827d51c30a3 100644
--- a/drivers/net/wireless/atmel.c
+++ b/drivers/net/wireless/atmel.c
@@ -1624,7 +1624,7 @@ struct net_device *init_atmel_card(unsigned short irq, unsigned long port,
 
         netif_carrier_off(dev);
 
-        if (!proc_create_data("driver/atmel", 0, NULL, &atmel_proc_fops, priv));
+        if (!proc_create_data("driver/atmel", 0, NULL, &atmel_proc_fops, priv))
                 printk(KERN_WARNING "atmel: unable to create /proc entry.\n");
 
         printk(KERN_INFO "%s: Atmel at76c50x. Version %d.%d. MAC %pM\n",
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index 6dd07e2ec595..a95b77ab360e 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -2458,7 +2458,7 @@ static void b43_request_firmware(struct work_struct *work)
         for (i = 0; i < B43_NR_FWTYPES; i++) {
                 errmsg = ctx->errors[i];
                 if (strlen(errmsg))
-                        b43err(dev->wl, errmsg);
+                        b43err(dev->wl, "%s", errmsg);
         }
         b43_print_fw_helptext(dev->wl, 1);
         goto out;
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
index be0787cab24f..9431af2465f3 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
@@ -27,7 +27,6 @@
 #include "tracepoint.h"
 
 #define PKTFILTER_BUF_SIZE              128
-#define BRCMF_ARPOL_MODE                0xb     /* agent|snoop|peer_autoreply */
 #define BRCMF_DEFAULT_BCN_TIMEOUT       3
 #define BRCMF_DEFAULT_SCAN_CHANNEL_TIME 40
 #define BRCMF_DEFAULT_SCAN_UNASSOC_TIME 40
@@ -338,23 +337,6 @@ int brcmf_c_preinit_dcmds(struct brcmf_if *ifp)
                 goto done;
         }
 
-        /* Try to set and enable ARP offload feature, this may fail */
-        err = brcmf_fil_iovar_int_set(ifp, "arp_ol", BRCMF_ARPOL_MODE);
-        if (err) {
-                brcmf_dbg(TRACE, "failed to set ARP offload mode to 0x%x, err = %d\n",
-                          BRCMF_ARPOL_MODE, err);
-                err = 0;
-        } else {
-                err = brcmf_fil_iovar_int_set(ifp, "arpoe", 1);
-                if (err) {
-                        brcmf_dbg(TRACE, "failed to enable ARP offload err = %d\n",
-                                  err);
-                        err = 0;
-                } else
-                        brcmf_dbg(TRACE, "successfully enabled ARP offload to 0x%x\n",
-                                  BRCMF_ARPOL_MODE);
-        }
-
         /* Setup packet filter */
         brcmf_c_pktfilter_offload_set(ifp, BRCMF_DEFAULT_PACKET_FILTER);
         brcmf_c_pktfilter_offload_enable(ifp, BRCMF_DEFAULT_PACKET_FILTER,
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
index 59c25463e428..2c593570497c 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
@@ -653,10 +653,13 @@ int brcmf_net_attach(struct brcmf_if *ifp, bool rtnl_locked)
 
         brcmf_dbg(INFO, "%s: Broadcom Dongle Host Driver\n", ndev->name);
 
+        ndev->destructor = free_netdev;
         return 0;
 
 fail:
+        drvr->iflist[ifp->bssidx] = NULL;
         ndev->netdev_ops = NULL;
+        free_netdev(ndev);
         return -EBADE;
 }
 
@@ -720,6 +723,9 @@ static int brcmf_net_p2p_attach(struct brcmf_if *ifp)
         return 0;
 
 fail:
+        ifp->drvr->iflist[ifp->bssidx] = NULL;
+        ndev->netdev_ops = NULL;
+        free_netdev(ndev);
         return -EBADE;
 }
 
@@ -788,6 +794,7 @@ void brcmf_del_if(struct brcmf_pub *drvr, s32 bssidx)
         struct brcmf_if *ifp;
 
         ifp = drvr->iflist[bssidx];
+        drvr->iflist[bssidx] = NULL;
         if (!ifp) {
                 brcmf_err("Null interface, idx=%d\n", bssidx);
                 return;
@@ -808,15 +815,13 @@ void brcmf_del_if(struct brcmf_pub *drvr, s32 bssidx)
                         cancel_work_sync(&ifp->setmacaddr_work);
                         cancel_work_sync(&ifp->multicast_work);
                 }
-
+                /* unregister will take care of freeing it */
                 unregister_netdev(ifp->ndev);
                 if (bssidx == 0)
                         brcmf_cfg80211_detach(drvr->config);
-                free_netdev(ifp->ndev);
         } else {
                 kfree(ifp);
         }
-        drvr->iflist[bssidx] = NULL;
 }
 
 int brcmf_attach(uint bus_hdrlen, struct device *dev)
@@ -925,8 +930,10 @@ fail:
                         brcmf_fws_del_interface(ifp);
                         brcmf_fws_deinit(drvr);
                 }
-                free_netdev(ifp->ndev);
-                drvr->iflist[0] = NULL;
+                if (drvr->iflist[0]) {
+                        free_netdev(ifp->ndev);
+                        drvr->iflist[0] = NULL;
+                }
                 if (p2p_ifp) {
                         free_netdev(p2p_ifp->ndev);
                         drvr->iflist[1] = NULL;
@@ -934,7 +941,8 @@ fail:
                 return ret;
         }
         if ((brcmf_p2p_enable) && (p2p_ifp))
-                brcmf_net_p2p_attach(p2p_ifp);
+                if (brcmf_net_p2p_attach(p2p_ifp) < 0)
+                        brcmf_p2p_enable = 0;
 
         return 0;
 }
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/fweh.c b/drivers/net/wireless/brcm80211/brcmfmac/fweh.c
index 5a64280e6485..83ee53a7c76e 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/fweh.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/fweh.c
@@ -202,7 +202,8 @@ static void brcmf_fweh_handle_if_event(struct brcmf_pub *drvr,
                         return;
                 brcmf_fws_add_interface(ifp);
                 if (!drvr->fweh.evt_handler[BRCMF_E_IF])
-                        err = brcmf_net_attach(ifp, false);
+                        if (brcmf_net_attach(ifp, false) < 0)
+                                return;
         }
 
         if (ifevent->action == BRCMF_E_IF_CHANGE)
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h b/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h
index 0f2c83bc95dc..665ef69e974b 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h
+++ b/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h
@@ -23,6 +23,12 @@
 
 #define BRCMF_FIL_ACTION_FRAME_SIZE     1800
 
+/* ARP Offload feature flags for arp_ol iovar */
+#define BRCMF_ARP_OL_AGENT              0x00000001
+#define BRCMF_ARP_OL_SNOOP              0x00000002
+#define BRCMF_ARP_OL_HOST_AUTO_REPLY    0x00000004
+#define BRCMF_ARP_OL_PEER_AUTO_REPLY    0x00000008
+
 
 enum brcmf_fil_p2p_if_types {
         BRCMF_FIL_P2P_IF_CLIENT,
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/p2p.c b/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
index e7a1a4770996..79555f006d53 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
@@ -47,6 +47,7 @@
 #define IS_P2P_SOCIAL_CHANNEL(channel) ((channel == SOCIAL_CHAN_1) || \
                                          (channel == SOCIAL_CHAN_2) || \
                                          (channel == SOCIAL_CHAN_3))
+#define BRCMF_P2P_TEMP_CHAN     SOCIAL_CHAN_3
 #define SOCIAL_CHAN_CNT         3
 #define AF_PEER_SEARCH_CNT      2
 
@@ -1954,21 +1955,21 @@ s32 brcmf_p2p_attach(struct brcmf_cfg80211_info *cfg)
                 err = brcmf_fil_iovar_int_set(pri_ifp, "p2p_disc", 1);
                 if (err < 0) {
                         brcmf_err("set p2p_disc error\n");
-                        brcmf_free_vif(p2p_vif);
+                        brcmf_free_vif(cfg, p2p_vif);
                         goto exit;
                 }
                 /* obtain bsscfg index for P2P discovery */
                 err = brcmf_fil_iovar_int_get(pri_ifp, "p2p_dev", &bssidx);
                 if (err < 0) {
                         brcmf_err("retrieving discover bsscfg index failed\n");
-                        brcmf_free_vif(p2p_vif);
+                        brcmf_free_vif(cfg, p2p_vif);
                         goto exit;
                 }
                 /* Verify that firmware uses same bssidx as driver !! */
                 if (p2p_ifp->bssidx != bssidx) {
                         brcmf_err("Incorrect bssidx=%d, compared to p2p_ifp->bssidx=%d\n",
                                   bssidx, p2p_ifp->bssidx);
-                        brcmf_free_vif(p2p_vif);
+                        brcmf_free_vif(cfg, p2p_vif);
                         goto exit;
                 }
 
@@ -1996,7 +1997,7 @@ void brcmf_p2p_detach(struct brcmf_p2p_info *p2p)
                 brcmf_p2p_cancel_remain_on_channel(vif->ifp);
                 brcmf_p2p_deinit_discovery(p2p);
                 /* remove discovery interface */
-                brcmf_free_vif(vif);
+                brcmf_free_vif(p2p->cfg, vif);
                 p2p->bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
         }
         /* just set it all to zero */
@@ -2013,17 +2014,30 @@ static void brcmf_p2p_get_current_chanspec(struct brcmf_p2p_info *p2p,
                                            u16 *chanspec)
 {
         struct brcmf_if *ifp;
-        struct brcmf_fil_chan_info_le ci;
+        u8 mac_addr[ETH_ALEN];
         struct brcmu_chan ch;
-        s32 err;
+        struct brcmf_bss_info_le *bi;
+        u8 *buf;
 
         ifp = p2p->bss_idx[P2PAPI_BSSCFG_PRIMARY].vif->ifp;
 
-        ch.chnum = 11;
-
-        err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_CHANNEL, &ci, sizeof(ci));
-        if (!err)
-                ch.chnum = le32_to_cpu(ci.hw_channel);
+        if (brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_BSSID, mac_addr,
+                                   ETH_ALEN) == 0) {
+                buf = kzalloc(WL_BSS_INFO_MAX, GFP_KERNEL);
+                if (buf != NULL) {
+                        *(__le32 *)buf = cpu_to_le32(WL_BSS_INFO_MAX);
+                        if (brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_BSS_INFO,
+                                                   buf, WL_BSS_INFO_MAX) == 0) {
+                                bi = (struct brcmf_bss_info_le *)(buf + 4);
+                                *chanspec = le16_to_cpu(bi->chanspec);
+                                kfree(buf);
+                                return;
+                        }
+                        kfree(buf);
+                }
+        }
+        /* Use default channel for P2P */
+        ch.chnum = BRCMF_P2P_TEMP_CHAN;
         ch.bw = BRCMU_CHAN_BW_20;
         p2p->cfg->d11inf.encchspec(&ch);
         *chanspec = ch.chspec;
@@ -2208,7 +2222,7 @@ static struct wireless_dev *brcmf_p2p_create_p2pdev(struct brcmf_p2p_info *p2p,
         return &p2p_vif->wdev;
 
 fail:
-        brcmf_free_vif(p2p_vif);
+        brcmf_free_vif(p2p->cfg, p2p_vif);
         return ERR_PTR(err);
 }
 
@@ -2217,13 +2231,31 @@ fail:
  *
  * @vif: virtual interface object to delete.
  */
-static void brcmf_p2p_delete_p2pdev(struct brcmf_cfg80211_vif *vif)
+static void brcmf_p2p_delete_p2pdev(struct brcmf_cfg80211_info *cfg,
+                                    struct brcmf_cfg80211_vif *vif)
 {
-        struct brcmf_p2p_info *p2p = &vif->ifp->drvr->config->p2p;
-
         cfg80211_unregister_wdev(&vif->wdev);
-        p2p->bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
-        brcmf_free_vif(vif);
+        cfg->p2p.bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
+        brcmf_free_vif(cfg, vif);
+}
+
+/**
+ * brcmf_p2p_free_p2p_if() - free up net device related data.
+ *
+ * @ndev: net device that needs to be freed.
+ */
+static void brcmf_p2p_free_p2p_if(struct net_device *ndev)
+{
+        struct brcmf_cfg80211_info *cfg;
+        struct brcmf_cfg80211_vif *vif;
+        struct brcmf_if *ifp;
+
+        ifp = netdev_priv(ndev);
+        cfg = ifp->drvr->config;
+        vif = ifp->vif;
+
+        brcmf_free_vif(cfg, vif);
+        free_netdev(ifp->ndev);
 }
 
 /**
@@ -2303,6 +2335,9 @@ struct wireless_dev *brcmf_p2p_add_vif(struct wiphy *wiphy, const char *name,
                 brcmf_err("Registering netdevice failed\n");
                 goto fail;
         }
+        /* override destructor */
+        ifp->ndev->destructor = brcmf_p2p_free_p2p_if;
+
         cfg->p2p.bss_idx[P2PAPI_BSSCFG_CONNECTION].vif = vif;
         /* Disable firmware roaming for P2P interface  */
         brcmf_fil_iovar_int_set(ifp, "roam_off", 1);
@@ -2314,7 +2349,7 @@ struct wireless_dev *brcmf_p2p_add_vif(struct wiphy *wiphy, const char *name,
         return &ifp->vif->wdev;
 
 fail:
-        brcmf_free_vif(vif);
+        brcmf_free_vif(cfg, vif);
         return ERR_PTR(err);
 }
 
@@ -2350,7 +2385,7 @@ int brcmf_p2p_del_vif(struct wiphy *wiphy, struct wireless_dev *wdev)
                 break;
 
         case NL80211_IFTYPE_P2P_DEVICE:
-                brcmf_p2p_delete_p2pdev(vif);
+                brcmf_p2p_delete_p2pdev(cfg, vif);
                 return 0;
         default:
                 return -ENOTSUPP;
@@ -2378,7 +2413,6 @@ int brcmf_p2p_del_vif(struct wiphy *wiphy, struct wireless_dev *wdev)
                         err = 0;
         }
         brcmf_cfg80211_arm_vif_event(cfg, NULL);
-        brcmf_free_vif(vif);
         p2p->bss_idx[P2PAPI_BSSCFG_CONNECTION].vif = NULL;
 
         return err;
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
index 761f501959a9..301e572e8923 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
@@ -459,6 +459,38 @@ send_key_to_dongle(struct net_device *ndev, struct brcmf_wsec_key *key)
         return err;
 }
 
+static s32
+brcmf_configure_arp_offload(struct brcmf_if *ifp, bool enable)
+{
+        s32 err;
+        u32 mode;
+
+        if (enable)
+                mode = BRCMF_ARP_OL_AGENT | BRCMF_ARP_OL_PEER_AUTO_REPLY;
+        else
+                mode = 0;
+
+        /* Try to set and enable ARP offload feature, this may fail, then it  */
+        /* is simply not supported and err 0 will be returned                 */
+        err = brcmf_fil_iovar_int_set(ifp, "arp_ol", mode);
+        if (err) {
+                brcmf_dbg(TRACE, "failed to set ARP offload mode to 0x%x, err = %d\n",
+                          mode, err);
+                err = 0;
+        } else {
+                err = brcmf_fil_iovar_int_set(ifp, "arpoe", enable);
+                if (err) {
+                        brcmf_dbg(TRACE, "failed to configure (%d) ARP offload err = %d\n",
+                                  enable, err);
+                        err = 0;
+                } else
+                        brcmf_dbg(TRACE, "successfully configured (%d) ARP offload to 0x%x\n",
+                                  enable, mode);
+        }
+
+        return err;
+}
+
 static struct wireless_dev *brcmf_cfg80211_add_iface(struct wiphy *wiphy,
                                                      const char *name,
                                                      enum nl80211_iftype type,
@@ -2216,6 +2248,11 @@ brcmf_cfg80211_set_power_mgmt(struct wiphy *wiphy, struct net_device *ndev,
         }
 
         pm = enabled ? PM_FAST : PM_OFF;
+        /* Do not enable the power save after assoc if it is a p2p interface */
+        if (ifp->vif->wdev.iftype == NL80211_IFTYPE_P2P_CLIENT) {
+                brcmf_dbg(INFO, "Do not enable power save for P2P clients\n");
+                pm = PM_OFF;
+        }
         brcmf_dbg(INFO, "power save %s\n", (pm ? "enabled" : "disabled"));
 
         err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PM, pm);
@@ -3640,10 +3677,28 @@ brcmf_config_ap_mgmt_ie(struct brcmf_cfg80211_vif *vif,
 }
 
 static s32
+brcmf_cfg80211_set_channel(struct brcmf_cfg80211_info *cfg,
+                           struct brcmf_if *ifp,
+                           struct ieee80211_channel *channel)
+{
+        u16 chanspec;
+        s32 err;
+
+        brcmf_dbg(TRACE, "band=%d, center_freq=%d\n", channel->band,
+                  channel->center_freq);
+
+        chanspec = channel_to_chanspec(&cfg->d11inf, channel);
+        err = brcmf_fil_iovar_int_set(ifp, "chanspec", chanspec);
+
+        return err;
+}
+
+static s32
 brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev,
                         struct cfg80211_ap_settings *settings)
 {
         s32 ie_offset;
+        struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
         struct brcmf_if *ifp = netdev_priv(ndev);
         struct brcmf_tlv *ssid_ie;
         struct brcmf_ssid_le ssid_le;
@@ -3683,6 +3738,7 @@ brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev,
         }
 
         brcmf_set_mpc(ifp, 0);
+        brcmf_configure_arp_offload(ifp, false);
 
         /* find the RSN_IE */
         rsn_ie = brcmf_parse_tlvs((u8 *)settings->beacon.tail,
@@ -3713,6 +3769,12 @@ brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev,
 
         brcmf_config_ap_mgmt_ie(ifp->vif, &settings->beacon);
 
+        err = brcmf_cfg80211_set_channel(cfg, ifp, settings->chandef.chan);
+        if (err < 0) {
+                brcmf_err("Set Channel failed, %d\n", err);
+                goto exit;
+        }
+
         if (settings->beacon_interval) {
                 err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_BCNPRD,
                                             settings->beacon_interval);
@@ -3789,8 +3851,10 @@ brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev,
         set_bit(BRCMF_VIF_STATUS_AP_CREATED, &ifp->vif->sme_state);
 
 exit:
-        if (err)
+        if (err) {
                 brcmf_set_mpc(ifp, 1);
+                brcmf_configure_arp_offload(ifp, true);
+        }
         return err;
 }
 
@@ -3831,6 +3895,7 @@ static int brcmf_cfg80211_stop_ap(struct wiphy *wiphy, struct net_device *ndev)
                         brcmf_err("bss_enable config failed %d\n", err);
         }
         brcmf_set_mpc(ifp, 1);
+        brcmf_configure_arp_offload(ifp, true);
         set_bit(BRCMF_VIF_STATUS_AP_CREATING, &ifp->vif->sme_state);
         clear_bit(BRCMF_VIF_STATUS_AP_CREATED, &ifp->vif->sme_state);
 
@@ -4148,7 +4213,7 @@ static const struct ieee80211_iface_limit brcmf_iface_limits[] = {
 static const struct ieee80211_iface_combination brcmf_iface_combos[] = {
         {
                  .max_interfaces = BRCMF_IFACE_MAX_CNT,
-                 .num_different_channels = 1, /* no multi-channel for now */
+                 .num_different_channels = 2,
                  .n_limits = ARRAY_SIZE(brcmf_iface_limits),
                  .limits = brcmf_iface_limits
         }
@@ -4256,20 +4321,16 @@ struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,
         return vif;
 }
 
-void brcmf_free_vif(struct brcmf_cfg80211_vif *vif)
+void brcmf_free_vif(struct brcmf_cfg80211_info *cfg,
+                    struct brcmf_cfg80211_vif *vif)
 {
-        struct brcmf_cfg80211_info *cfg;
-        struct wiphy *wiphy;
-
-        wiphy = vif->wdev.wiphy;
-        cfg = wiphy_priv(wiphy);
         list_del(&vif->list);
         cfg->vif_cnt--;
 
         kfree(vif);
         if (!cfg->vif_cnt) {
-                wiphy_unregister(wiphy);
-                wiphy_free(wiphy);
+                wiphy_unregister(cfg->wiphy);
+                wiphy_free(cfg->wiphy);
         }
 }
 
@@ -4646,7 +4707,6 @@ static s32 brcmf_notify_vif_event(struct brcmf_if *ifp,
                 return 0;
 
         case BRCMF_E_IF_DEL:
-                ifp->vif = NULL;
                 mutex_unlock(&event->vif_event_lock);
                 /* event may not be upon user request */
                 if (brcmf_cfg80211_vif_event_armed(cfg))
@@ -4852,8 +4912,7 @@ cfg80211_p2p_attach_out:
         wl_deinit_priv(cfg);
 
 cfg80211_attach_out:
-        brcmf_free_vif(vif);
-        wiphy_free(wiphy);
+        brcmf_free_vif(cfg, vif);
         return NULL;
 }
 
@@ -4865,7 +4924,7 @@ void brcmf_cfg80211_detach(struct brcmf_cfg80211_info *cfg)
         wl_deinit_priv(cfg);
         brcmf_btcoex_detach(cfg);
         list_for_each_entry_safe(vif, tmp, &cfg->vif_list, list) {
-                brcmf_free_vif(vif);
+                brcmf_free_vif(cfg, vif);
         }
 }
 
@@ -5229,6 +5288,8 @@ static s32 brcmf_config_dongle(struct brcmf_cfg80211_info *cfg)
         if (err)
                 goto default_conf_out;
 
+        brcmf_configure_arp_offload(ifp, true);
+
         cfg->dongle_up = true;
 default_conf_out:
 
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
index a71cff84cdcf..d9bdaf9a72d0 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
+++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
@@ -487,7 +487,8 @@ enum nl80211_iftype brcmf_cfg80211_get_iftype(struct brcmf_if *ifp);
 struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,
                                            enum nl80211_iftype type,
                                            bool pm_block);
-void brcmf_free_vif(struct brcmf_cfg80211_vif *vif);
+void brcmf_free_vif(struct brcmf_cfg80211_info *cfg,
+                    struct brcmf_cfg80211_vif *vif);
 
 s32 brcmf_vif_set_mgmt_ie(struct brcmf_cfg80211_vif *vif, s32 pktflag,
                           const u8 *vndr_ie_buf, u32 vndr_ie_len);
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/main.c b/drivers/net/wireless/brcm80211/brcmsmac/main.c
index 28e7aeedd184..9fd6f2fef11b 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
@@ -3074,21 +3074,8 @@ static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
  */
 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
 {
-        /* disallow PS when one of the following global conditions meets */
-        if (!wlc->pub->associated)
-                return false;
-
-        /* disallow PS when one of these meets when not scanning */
-        if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
-                return false;
-
-        if (wlc->bsscfg->type == BRCMS_TYPE_AP)
-                return false;
-
-        if (wlc->bsscfg->type == BRCMS_TYPE_ADHOC)
-                return false;
-
-        return true;
+        /* not supporting PS so always return false for now */
+        return false;
 }
 
 static void brcms_c_statsupd(struct brcms_c_info *wlc)
diff --git a/drivers/net/wireless/iwlegacy/3945-rs.c b/drivers/net/wireless/iwlegacy/3945-rs.c
index c9f197d9ca1e..fe31590a51b2 100644
--- a/drivers/net/wireless/iwlegacy/3945-rs.c
+++ b/drivers/net/wireless/iwlegacy/3945-rs.c
@@ -816,6 +816,7 @@ out:
                 rs_sta->last_txrate_idx = idx;
                 info->control.rates[0].idx = rs_sta->last_txrate_idx;
         }
+        info->control.rates[0].count = 1;
 
         D_RATE("leave: %d\n", idx);
 }
diff --git a/drivers/net/wireless/iwlegacy/4965-rs.c b/drivers/net/wireless/iwlegacy/4965-rs.c
index 1fc0b227e120..ed3c42a63a43 100644
--- a/drivers/net/wireless/iwlegacy/4965-rs.c
+++ b/drivers/net/wireless/iwlegacy/4965-rs.c
@@ -2268,7 +2268,7 @@ il4965_rs_get_rate(void *il_r, struct ieee80211_sta *sta, void *il_sta,
                 info->control.rates[0].flags = 0;
         }
         info->control.rates[0].idx = rate_idx;
-
+        info->control.rates[0].count = 1;
 }
 
 static void *
diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h
index f8246f2d88f9..4caaf52986a4 100644
--- a/drivers/net/wireless/iwlegacy/common.h
+++ b/drivers/net/wireless/iwlegacy/common.h
@@ -1832,16 +1832,16 @@ u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
 __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
                           u32 beacon_interval);
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 extern const struct dev_pm_ops il_pm_ops;
 
 #define IL_LEGACY_PM_OPS        (&il_pm_ops)
 
-#else /* !CONFIG_PM */
+#else /* !CONFIG_PM_SLEEP */
 
 #define IL_LEGACY_PM_OPS        NULL
 
-#endif /* !CONFIG_PM */
+#endif /* !CONFIG_PM_SLEEP */
 
 /*****************************************************
 *  Error Handling Debugging
diff --git a/drivers/net/wireless/iwlwifi/dvm/rs.c b/drivers/net/wireless/iwlwifi/dvm/rs.c
index 907bd6e50aad..10fbb176cc8e 100644
--- a/drivers/net/wireless/iwlwifi/dvm/rs.c
+++ b/drivers/net/wireless/iwlwifi/dvm/rs.c
@@ -2799,7 +2799,7 @@ static void rs_get_rate(void *priv_r, struct ieee80211_sta *sta, void *priv_sta,
                 info->control.rates[0].flags = 0;
         }
         info->control.rates[0].idx = rate_idx;
-
+        info->control.rates[0].count = 1;
 }
 
 static void *rs_alloc_sta(void *priv_rate, struct ieee80211_sta *sta,
diff --git a/drivers/net/wireless/iwlwifi/dvm/rxon.c b/drivers/net/wireless/iwlwifi/dvm/rxon.c
index 707446fa00bd..cd1ad0019185 100644
--- a/drivers/net/wireless/iwlwifi/dvm/rxon.c
+++ b/drivers/net/wireless/iwlwifi/dvm/rxon.c
@@ -1378,7 +1378,7 @@ static void iwlagn_chain_noise_reset(struct iwl_priv *priv)
         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
         int ret;
 
-        if (!(priv->calib_disabled & IWL_CHAIN_NOISE_CALIB_DISABLED))
+        if (priv->calib_disabled & IWL_CHAIN_NOISE_CALIB_DISABLED)
                 return;
 
         if ((data->state == IWL_CHAIN_NOISE_ALIVE) &&
diff --git a/drivers/net/wireless/iwlwifi/dvm/sta.c b/drivers/net/wireless/iwlwifi/dvm/sta.c
index db183b44e038..c3c13ce96eb0 100644
--- a/drivers/net/wireless/iwlwifi/dvm/sta.c
+++ b/drivers/net/wireless/iwlwifi/dvm/sta.c
@@ -735,7 +735,7 @@ void iwl_restore_stations(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
                                         memcpy(&lq, priv->stations[i].lq,
                                                sizeof(struct iwl_link_quality_cmd));
 
-                                if (!memcmp(&lq, &zero_lq, sizeof(lq)))
+                                if (memcmp(&lq, &zero_lq, sizeof(lq)))
                                         send_lq = true;
                         }
                         spin_unlock_bh(&priv->sta_lock);
diff --git a/drivers/net/wireless/iwlwifi/iwl-drv.c b/drivers/net/wireless/iwlwifi/iwl-drv.c
index 39aad9893e0b..40fed1f511e2 100644
--- a/drivers/net/wireless/iwlwifi/iwl-drv.c
+++ b/drivers/net/wireless/iwlwifi/iwl-drv.c
@@ -1000,10 +1000,12 @@ static void iwl_req_fw_callback(const struct firmware *ucode_raw, void *context)
          */
         if (load_module) {
                 err = request_module("%s", op->name);
+#ifdef CONFIG_IWLWIFI_OPMODE_MODULAR
                 if (err)
                         IWL_ERR(drv,
                                 "failed to load module %s (error %d), is dynamic loading enabled?\n",
                                 op->name, err);
+#endif
         }
         return;
 
diff --git a/drivers/net/wireless/iwlwifi/mvm/rs.c b/drivers/net/wireless/iwlwifi/mvm/rs.c
index 55334d542e26..b99fe3163866 100644
--- a/drivers/net/wireless/iwlwifi/mvm/rs.c
+++ b/drivers/net/wireless/iwlwifi/mvm/rs.c
@@ -2546,6 +2546,7 @@ static void rs_get_rate(void *mvm_r, struct ieee80211_sta *sta, void *mvm_sta,
                 info->control.rates[0].flags = 0;
         }
         info->control.rates[0].idx = rate_idx;
+        info->control.rates[0].count = 1;
 }
 
 static void *rs_alloc_sta(void *mvm_rate, struct ieee80211_sta *sta,
diff --git a/drivers/net/wireless/iwlwifi/mvm/tx.c b/drivers/net/wireless/iwlwifi/mvm/tx.c
index f212f16502ff..48c1891e3df6 100644
--- a/drivers/net/wireless/iwlwifi/mvm/tx.c
+++ b/drivers/net/wireless/iwlwifi/mvm/tx.c
@@ -180,7 +180,8 @@ static void iwl_mvm_set_tx_cmd_rate(struct iwl_mvm *mvm,
                 tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_STA_RATE);
                 return;
         } else if (ieee80211_is_back_req(fc)) {
-                tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_STA_RATE);
+                tx_cmd->tx_flags |=
+                        cpu_to_le32(TX_CMD_FLG_ACK | TX_CMD_FLG_BAR);
         }
 
         /* HT rate doesn't make sense for a non data frame */
diff --git a/drivers/net/wireless/mwifiex/debugfs.c b/drivers/net/wireless/mwifiex/debugfs.c
index 753b5682d53f..a5f9875cfd6e 100644
--- a/drivers/net/wireless/mwifiex/debugfs.c
+++ b/drivers/net/wireless/mwifiex/debugfs.c
@@ -26,10 +26,17 @@
 static struct dentry *mwifiex_dfs_dir;
 
 static char *bss_modes[] = {
-        "Unknown",
-        "Ad-hoc",
-        "Managed",
-        "Auto"
+        "UNSPECIFIED",
+        "ADHOC",
+        "STATION",
+        "AP",
+        "AP_VLAN",
+        "WDS",
+        "MONITOR",
+        "MESH_POINT",
+        "P2P_CLIENT",
+        "P2P_GO",
+        "P2P_DEVICE",
 };
 
 /* size/addr for mwifiex_debug_info */
@@ -200,7 +207,12 @@ mwifiex_info_read(struct file *file, char __user *ubuf,
         p += sprintf(p, "driver_version = %s", fmt);
         p += sprintf(p, "\nverext = %s", priv->version_str);
         p += sprintf(p, "\ninterface_name=\"%s\"\n", netdev->name);
-        p += sprintf(p, "bss_mode=\"%s\"\n", bss_modes[info.bss_mode]);
+
+        if (info.bss_mode >= ARRAY_SIZE(bss_modes))
+                p += sprintf(p, "bss_mode=\"%d\"\n", info.bss_mode);
+        else
+                p += sprintf(p, "bss_mode=\"%s\"\n", bss_modes[info.bss_mode]);
+
         p += sprintf(p, "media_state=\"%s\"\n",
                      (!priv->media_connected ? "Disconnected" : "Connected"));
         p += sprintf(p, "mac_address=\"%pM\"\n", netdev->dev_addr);
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index b52d70c75e1a..72f32e5caa4d 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -3027,19 +3027,26 @@ static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
          * TODO: we do not use +6 dBm option to do not increase power beyond
          * regulatory limit, however this could be utilized for devices with
          * CAPABILITY_POWER_LIMIT.
+         *
+         * TODO: add different temperature compensation code for RT3290 & RT5390
+         * to allow to use BBP_R1 for those chips.
          */
-        rt2800_bbp_read(rt2x00dev, 1, &r1);
-        if (delta <= -12) {
-                power_ctrl = 2;
-                delta += 12;
-        } else if (delta <= -6) {
-                power_ctrl = 1;
-                delta += 6;
-        } else {
-                power_ctrl = 0;
+        if (!rt2x00_rt(rt2x00dev, RT3290) &&
+            !rt2x00_rt(rt2x00dev, RT5390)) {
+                rt2800_bbp_read(rt2x00dev, 1, &r1);
+                if (delta <= -12) {
+                        power_ctrl = 2;
+                        delta += 12;
+                } else if (delta <= -6) {
+                        power_ctrl = 1;
+                        delta += 6;
+                } else {
+                        power_ctrl = 0;
+                }
+                rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
+                rt2800_bbp_write(rt2x00dev, 1, r1);
         }
-        rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
-        rt2800_bbp_write(rt2x00dev, 1, r1);
+
         offset = TX_PWR_CFG_0;
 
         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c
index 999ffc12578b..c97e9d327331 100644
--- a/drivers/net/wireless/rtlwifi/pci.c
+++ b/drivers/net/wireless/rtlwifi/pci.c
@@ -764,6 +764,7 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
                                  "can't alloc skb for rx\n");
                         goto done;
                 }
+                kmemleak_not_leak(new_skb);
 
                 pci_unmap_single(rtlpci->pdev,
                                  *((dma_addr_t *) skb->cb),
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
index 3d0498e69c8c..189ba124a8c6 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
@@ -1973,26 +1973,35 @@ void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
         }
 }
 
-void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
-                                   struct ieee80211_sta *sta,
-                                   u8 rssi_level)
+static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
+                                          struct ieee80211_sta *sta)
 {
         struct rtl_priv *rtlpriv = rtl_priv(hw);
         struct rtl_phy *rtlphy = &(rtlpriv->phy);
         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-        u32 ratr_value = (u32) mac->basic_rates;
-        u8 *mcsrate = mac->mcs;
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        u32 ratr_value;
         u8 ratr_index = 0;
         u8 nmode = mac->ht_enable;
-        u8 mimo_ps = 1;
-        u16 shortgi_rate = 0;
-        u32 tmp_ratr_value = 0;
+        u8 mimo_ps = IEEE80211_SMPS_OFF;
+        u16 shortgi_rate;
+        u32 tmp_ratr_value;
         u8 curtxbw_40mhz = mac->bw_40;
-        u8 curshortgi_40mhz = mac->sgi_40;
-        u8 curshortgi_20mhz = mac->sgi_20;
+        u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
+                               1 : 0;
+        u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
+                               1 : 0;
         enum wireless_mode wirelessmode = mac->mode;
 
-        ratr_value |= ((*(u16 *) (mcsrate))) << 12;
+        if (rtlhal->current_bandtype == BAND_ON_5G)
+                ratr_value = sta->supp_rates[1] << 4;
+        else
+                ratr_value = sta->supp_rates[0];
+        if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                ratr_value = 0xfff;
+
+        ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
+                        sta->ht_cap.mcs.rx_mask[0] << 12);
         switch (wirelessmode) {
         case WIRELESS_MODE_B:
                 if (ratr_value & 0x0000000c)
@@ -2006,7 +2015,7 @@ void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
         case WIRELESS_MODE_N_24G:
         case WIRELESS_MODE_N_5G:
                 nmode = 1;
-                if (mimo_ps == 0) {
+                if (mimo_ps == IEEE80211_SMPS_STATIC) {
                         ratr_value &= 0x0007F005;
                 } else {
                         u32 ratr_mask;
@@ -2016,8 +2025,7 @@ void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
                                 ratr_mask = 0x000ff005;
                         else
                                 ratr_mask = 0x0f0ff005;
-                        if (curtxbw_40mhz)
-                                ratr_mask |= 0x00000010;
+
                         ratr_value &= ratr_mask;
                 }
                 break;
@@ -2026,41 +2034,74 @@ void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
                         ratr_value &= 0x000ff0ff;
                 else
                         ratr_value &= 0x0f0ff0ff;
+
                 break;
         }
+
         ratr_value &= 0x0FFFFFFF;
-        if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
-            (!curtxbw_40mhz && curshortgi_20mhz))) {
+
+        if (nmode && ((curtxbw_40mhz &&
+                         curshortgi_40mhz) || (!curtxbw_40mhz &&
+                                               curshortgi_20mhz))) {
+
                 ratr_value |= 0x10000000;
                 tmp_ratr_value = (ratr_value >> 12);
+
                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
                         if ((1 << shortgi_rate) & tmp_ratr_value)
                                 break;
                 }
+
                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
-                               (shortgi_rate << 4) | (shortgi_rate);
+                    (shortgi_rate << 4) | (shortgi_rate);
         }
+
         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
+
+        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
+                 rtl_read_dword(rtlpriv, REG_ARFR0));
 }
 
-void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
+static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,
+                                         struct ieee80211_sta *sta,
+                                         u8 rssi_level)
 {
         struct rtl_priv *rtlpriv = rtl_priv(hw);
         struct rtl_phy *rtlphy = &(rtlpriv->phy);
         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-        u32 ratr_bitmap = (u32) mac->basic_rates;
-        u8 *p_mcsrate = mac->mcs;
-        u8 ratr_index = 0;
-        u8 curtxbw_40mhz = mac->bw_40;
-        u8 curshortgi_40mhz = mac->sgi_40;
-        u8 curshortgi_20mhz = mac->sgi_20;
-        enum wireless_mode wirelessmode = mac->mode;
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_sta_info *sta_entry = NULL;
+        u32 ratr_bitmap;
+        u8 ratr_index;
+        u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
+        u8 curshortgi_40mhz = curtxbw_40mhz &&
+                              (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
+                                1 : 0;
+        u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
+                                1 : 0;
+        enum wireless_mode wirelessmode = 0;
         bool shortgi = false;
         u8 rate_mask[5];
         u8 macid = 0;
-        u8 mimops = 1;
-
-        ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
+        u8 mimo_ps = IEEE80211_SMPS_OFF;
+
+        sta_entry = (struct rtl_sta_info *) sta->drv_priv;
+        wirelessmode = sta_entry->wireless_mode;
+        if (mac->opmode == NL80211_IFTYPE_STATION ||
+            mac->opmode == NL80211_IFTYPE_MESH_POINT)
+                curtxbw_40mhz = mac->bw_40;
+        else if (mac->opmode == NL80211_IFTYPE_AP ||
+                mac->opmode == NL80211_IFTYPE_ADHOC)
+                macid = sta->aid + 1;
+
+        if (rtlhal->current_bandtype == BAND_ON_5G)
+                ratr_bitmap = sta->supp_rates[1] << 4;
+        else
+                ratr_bitmap = sta->supp_rates[0];
+        if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                ratr_bitmap = 0xfff;
+        ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
+                        sta->ht_cap.mcs.rx_mask[0] << 12);
         switch (wirelessmode) {
         case WIRELESS_MODE_B:
                 ratr_index = RATR_INX_WIRELESS_B;
@@ -2071,6 +2112,7 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
                 break;
         case WIRELESS_MODE_G:
                 ratr_index = RATR_INX_WIRELESS_GB;
+
                 if (rssi_level == 1)
                         ratr_bitmap &= 0x00000f00;
                 else if (rssi_level == 2)
@@ -2085,7 +2127,8 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
         case WIRELESS_MODE_N_24G:
         case WIRELESS_MODE_N_5G:
                 ratr_index = RATR_INX_WIRELESS_NGB;
-                if (mimops == 0) {
+
+                if (mimo_ps == IEEE80211_SMPS_STATIC) {
                         if (rssi_level == 1)
                                 ratr_bitmap &= 0x00070000;
                         else if (rssi_level == 2)
@@ -2128,8 +2171,10 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
                                 }
                         }
                 }
+
                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
                     (!curtxbw_40mhz && curshortgi_20mhz)) {
+
                         if (macid == 0)
                                 shortgi = true;
                         else if (macid == 1)
@@ -2138,21 +2183,42 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
                 break;
         default:
                 ratr_index = RATR_INX_WIRELESS_NGB;
+
                 if (rtlphy->rf_type == RF_1T2R)
                         ratr_bitmap &= 0x000ff0ff;
                 else
                         ratr_bitmap &= 0x0f0ff0ff;
                 break;
         }
-        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "ratr_bitmap :%x\n",
-                 ratr_bitmap);
-        *(u32 *)&rate_mask = ((ratr_bitmap & 0x0fffffff) |
-                                      ratr_index << 28);
+        sta_entry->ratr_index = ratr_index;
+
+        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
+                 "ratr_bitmap :%x\n", ratr_bitmap);
+        *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
+                                     (ratr_index << 28);
         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
                  "Rate_index:%x, ratr_val:%x, %5phC\n",
                  ratr_index, ratr_bitmap, rate_mask);
-        rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
+        memcpy(rtlpriv->rate_mask, rate_mask, 5);
+        /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a
+         * "scheduled while atomic" if called directly */
+        schedule_work(&rtlpriv->works.fill_h2c_cmd);
+
+        if (macid != 0)
+                sta_entry->ratr_index = ratr_index;
+}
+
+void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
+                                 struct ieee80211_sta *sta,
+                                 u8 rssi_level)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        if (rtlpriv->dm.useramask)
+                rtl92cu_update_hal_rate_mask(hw, sta, rssi_level);
+        else
+                rtl92cu_update_hal_rate_table(hw, sta);
 }
 
 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
index f41a3aa4a26f..8e3ec1e25644 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
@@ -98,10 +98,6 @@ void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
                                    u32 add_msr, u32 rm_msr);
 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
-void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
-                                   struct ieee80211_sta *sta,
-                                   u8 rssi_level);
-void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level);
 
 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw);
 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
index 85b6bdb163c0..da4f587199ee 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
@@ -289,14 +289,30 @@ void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index,
                                 macaddr = cam_const_broad;
                                 entry_id = key_index;
                         } else {
+                                if (mac->opmode == NL80211_IFTYPE_AP ||
+                                    mac->opmode == NL80211_IFTYPE_MESH_POINT) {
+                                        entry_id = rtl_cam_get_free_entry(hw,
+                                                                 p_macaddr);
+                                        if (entry_id >=  TOTAL_CAM_ENTRY) {
+                                                RT_TRACE(rtlpriv, COMP_SEC,
+                                                         DBG_EMERG,
+                                                         "Can not find free hw security cam entry\n");
+                                                return;
+                                        }
+                                } else {
+                                        entry_id = CAM_PAIRWISE_KEY_POSITION;
+                                }
+
                                 key_index = PAIRWISE_KEYIDX;
-                                entry_id = CAM_PAIRWISE_KEY_POSITION;
                                 is_pairwise = true;
                         }
                 }
                 if (rtlpriv->sec.key_len[key_index] == 0) {
                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
                                  "delete one entry\n");
+                        if (mac->opmode == NL80211_IFTYPE_AP ||
+                            mac->opmode == NL80211_IFTYPE_MESH_POINT)
+                                rtl_cam_del_entry(hw, p_macaddr);
                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
                 } else {
                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
index 938b1e670b93..826f085c29dd 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
@@ -106,8 +106,7 @@ static struct rtl_hal_ops rtl8192cu_hal_ops = {
         .update_interrupt_mask = rtl92cu_update_interrupt_mask,
         .get_hw_reg = rtl92cu_get_hw_reg,
         .set_hw_reg = rtl92cu_set_hw_reg,
-        .update_rate_tbl = rtl92cu_update_hal_rate_table,
-        .update_rate_mask = rtl92cu_update_hal_rate_mask,
+        .update_rate_tbl = rtl92cu_update_hal_rate_tbl,
         .fill_tx_desc = rtl92cu_tx_fill_desc,
         .fill_fake_txdesc = rtl92cu_fill_fake_txdesc,
         .fill_tx_cmddesc = rtl92cu_tx_fill_cmddesc,
@@ -137,6 +136,7 @@ static struct rtl_hal_ops rtl8192cu_hal_ops = {
         .phy_lc_calibrate = _rtl92cu_phy_lc_calibrate,
         .phy_set_bw_mode_callback = rtl92cu_phy_set_bw_mode_callback,
         .dm_dynamic_txpower = rtl92cu_dm_dynamic_txpower,
+        .fill_h2c_cmd = rtl92c_fill_h2c_cmd,
 };
 
 static struct rtl_mod_params rtl92cu_mod_params = {
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
index a1310abd0d54..262e1e4c6e5b 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
@@ -49,5 +49,8 @@ bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
 u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
                             enum radio_path rfpath, u32 regaddr, u32 bitmask);
 void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
+void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
+                                 struct ieee80211_sta *sta,
+                                 u8 rssi_level);
 
 #endif
diff --git a/drivers/net/wireless/rtlwifi/usb.c b/drivers/net/wireless/rtlwifi/usb.c
index 76732b0cd221..a3532e077871 100644
--- a/drivers/net/wireless/rtlwifi/usb.c
+++ b/drivers/net/wireless/rtlwifi/usb.c
@@ -824,6 +824,7 @@ static void rtl_usb_stop(struct ieee80211_hw *hw)
 
         /* should after adapter start and interrupt enable. */
         set_hal_stop(rtlhal);
+        cancel_work_sync(&rtlpriv->works.fill_h2c_cmd);
         /* Enable software */
         SET_USB_STOP(rtlusb);
         rtl_usb_deinit(hw);
@@ -1026,6 +1027,16 @@ static bool rtl_usb_tx_chk_waitq_insert(struct ieee80211_hw *hw,
         return false;
 }
 
+static void rtl_fill_h2c_cmd_work_callback(struct work_struct *work)
+{
+        struct rtl_works *rtlworks =
+            container_of(work, struct rtl_works, fill_h2c_cmd);
+        struct ieee80211_hw *hw = rtlworks->hw;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        rtlpriv->cfg->ops->fill_h2c_cmd(hw, H2C_RA_MASK, 5, rtlpriv->rate_mask);
+}
+
 static struct rtl_intf_ops rtl_usb_ops = {
         .adapter_start = rtl_usb_start,
         .adapter_stop = rtl_usb_stop,
@@ -1057,6 +1068,8 @@ int rtl_usb_probe(struct usb_interface *intf,
 
         /* this spin lock must be initialized early */
         spin_lock_init(&rtlpriv->locks.usb_lock);
+        INIT_WORK(&rtlpriv->works.fill_h2c_cmd,
+                  rtl_fill_h2c_cmd_work_callback);
 
         rtlpriv->usb_data_index = 0;
         init_completion(&rtlpriv->firmware_loading_complete);
diff --git a/drivers/net/wireless/rtlwifi/wifi.h b/drivers/net/wireless/rtlwifi/wifi.h
index 44328baa6389..cc03e7c87cbe 100644
--- a/drivers/net/wireless/rtlwifi/wifi.h
+++ b/drivers/net/wireless/rtlwifi/wifi.h
@@ -1736,6 +1736,8 @@ struct rtl_hal_ops {
         void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
                                              bool mstate);
         void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
+        void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
+                              u32 cmd_len, u8 *p_cmdbuffer);
 };
 
 struct rtl_intf_ops {
@@ -1869,6 +1871,7 @@ struct rtl_works {
         struct delayed_work fwevt_wq;
 
         struct work_struct lps_change_work;
+        struct work_struct fill_h2c_cmd;
 };
 
 struct rtl_debug {
@@ -2048,6 +2051,7 @@ struct rtl_priv {
                 };
         };
         bool enter_ps;  /* true when entering PS */
+        u8 rate_mask[5];
 
         /*This must be the last item so
            that it points to the data allocated
diff --git a/drivers/net/wireless/ti/wl12xx/scan.c b/drivers/net/wireless/ti/wl12xx/scan.c
index affdb3ec6225..4a0bbb13806b 100644
--- a/drivers/net/wireless/ti/wl12xx/scan.c
+++ b/drivers/net/wireless/ti/wl12xx/scan.c
@@ -310,7 +310,7 @@ static void wl12xx_adjust_channels(struct wl1271_cmd_sched_scan_config *cmd,
         memcpy(cmd->channels_2, cmd_channels->channels_2,
                sizeof(cmd->channels_2));
         memcpy(cmd->channels_5, cmd_channels->channels_5,
-               sizeof(cmd->channels_2));
+               sizeof(cmd->channels_5));
         /* channels_4 are not supported, so no need to copy them */
 }
 
diff --git a/drivers/net/wireless/ti/wl12xx/wl12xx.h b/drivers/net/wireless/ti/wl12xx/wl12xx.h
index 222d03540200..9e5484a73667 100644
--- a/drivers/net/wireless/ti/wl12xx/wl12xx.h
+++ b/drivers/net/wireless/ti/wl12xx/wl12xx.h
@@ -36,12 +36,12 @@
 #define WL127X_IFTYPE_SR_VER    3
 #define WL127X_MAJOR_SR_VER     10
 #define WL127X_SUBTYPE_SR_VER   WLCORE_FW_VER_IGNORE
-#define WL127X_MINOR_SR_VER     115
+#define WL127X_MINOR_SR_VER     133
 /* minimum multi-role FW version for wl127x */
 #define WL127X_IFTYPE_MR_VER    5
 #define WL127X_MAJOR_MR_VER     7
 #define WL127X_SUBTYPE_MR_VER   WLCORE_FW_VER_IGNORE
-#define WL127X_MINOR_MR_VER     115
+#define WL127X_MINOR_MR_VER     42
 
 /* FW chip version for wl128x */
 #define WL128X_CHIP_VER         7
@@ -49,7 +49,7 @@
 #define WL128X_IFTYPE_SR_VER    3
 #define WL128X_MAJOR_SR_VER     10
 #define WL128X_SUBTYPE_SR_VER   WLCORE_FW_VER_IGNORE
-#define WL128X_MINOR_SR_VER     115
+#define WL128X_MINOR_SR_VER     133
 /* minimum multi-role FW version for wl128x */
 #define WL128X_IFTYPE_MR_VER    5
 #define WL128X_MAJOR_MR_VER     7
diff --git a/drivers/net/wireless/ti/wl18xx/scan.c b/drivers/net/wireless/ti/wl18xx/scan.c
index 09d944505ac0..2b642f8c9266 100644
--- a/drivers/net/wireless/ti/wl18xx/scan.c
+++ b/drivers/net/wireless/ti/wl18xx/scan.c
@@ -34,7 +34,7 @@ static void wl18xx_adjust_channels(struct wl18xx_cmd_scan_params *cmd,
         memcpy(cmd->channels_2, cmd_channels->channels_2,
                sizeof(cmd->channels_2));
         memcpy(cmd->channels_5, cmd_channels->channels_5,
-               sizeof(cmd->channels_2));
+               sizeof(cmd->channels_5));
         /* channels_4 are not supported, so no need to copy them */
 }
 
diff --git a/drivers/net/xen-netback/netback.c b/drivers/net/xen-netback/netback.c
index 37984e6d4e99..8c20935d72c9 100644
--- a/drivers/net/xen-netback/netback.c
+++ b/drivers/net/xen-netback/netback.c
@@ -662,7 +662,7 @@ static void xen_netbk_rx_action(struct xen_netbk *netbk)
 {
         struct xenvif *vif = NULL, *tmp;
         s8 status;
-        u16 irq, flags;
+        u16 flags;
         struct xen_netif_rx_response *resp;
         struct sk_buff_head rxq;
         struct sk_buff *skb;
@@ -771,13 +771,13 @@ static void xen_netbk_rx_action(struct xen_netbk *netbk)
                                          sco->meta_slots_used);
 
                 RING_PUSH_RESPONSES_AND_CHECK_NOTIFY(&vif->rx, ret);
-                irq = vif->irq;
-                if (ret && list_empty(&vif->notify_list))
-                        list_add_tail(&vif->notify_list, &notify);
 
                 xenvif_notify_tx_completion(vif);
 
-                xenvif_put(vif);
+                if (ret && list_empty(&vif->notify_list))
+                        list_add_tail(&vif->notify_list, &notify);
+                else
+                        xenvif_put(vif);
                 npo.meta_cons += sco->meta_slots_used;
                 dev_kfree_skb(skb);
         }
@@ -785,6 +785,7 @@ static void xen_netbk_rx_action(struct xen_netbk *netbk)
         list_for_each_entry_safe(vif, tmp, &notify, notify_list) {
                 notify_remote_via_irq(vif->irq);
                 list_del_init(&vif->notify_list);
+                xenvif_put(vif);
         }
 
         /* More work to do? */