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authorRajkumar Manoharan <rmanohar@qca.qualcomm.com>2011-07-29 08:08:15 -0400
committerJohn W. Linville <linville@tuxdriver.com>2011-08-09 16:11:32 -0400
commit15052f81d255eac44e745bc630b36aa86779ad9d (patch)
treeb8f6310299bcbe4cdd9174bac7be959470aee241 /drivers/net
parent5b36c9b4a9872f7852b8ce7cffbfc2f6d6c25371 (diff)
ath9k_hw: Fix incorrect Tx control power in AR9003 template
CTL power data incorrect in ctlPowerData_2G field of ar9300_eeprom. Setting incorrect CTL power in calibration is causing lower tx power. Tx power was reported as 3dBm while operating in channel 6 HT40+/ in channel 11 HT40- due to CTL powers in the calibration is set to zero. Cc: stable@kernel.org Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index d109c25417f4..6cfc9ebcd5c4 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -307,7 +307,7 @@ static const struct ar9300_eeprom ar9300_default = {
307 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 307 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
308 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 308 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
309 309
310 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } }, 310 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
311 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 311 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
312 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 312 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
313 313
@@ -884,7 +884,7 @@ static const struct ar9300_eeprom ar9300_x113 = {
884 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 884 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
885 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 885 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
886 886
887 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } }, 887 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
888 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 888 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
889 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 889 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
890 890
@@ -2040,7 +2040,7 @@ static const struct ar9300_eeprom ar9300_x112 = {
2040 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2040 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2041 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 2041 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2042 2042
2043 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } }, 2043 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2044 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2044 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2045 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2045 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2046 2046