diff options
author | raghavendra.koushik@neterion.com <raghavendra.koushik@neterion.com> | 2005-08-03 15:36:55 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2005-08-11 00:10:45 -0400 |
commit | 541ae68f6ddf1c27aa6879935ce541f110484202 (patch) | |
tree | f85387531b0e3f5888c296dfab185409ba4c1265 /drivers/net | |
parent | be3a6b02eb68a4d47397b771b6e4aa1f7f0f7ffb (diff) |
[PATCH] S2io: Support for Xframe II NIC
Hi,
This patch provides basic support for the Xframe II adapter.
Includes the following changes:
1. New values to program XAUI interface.
2. Print the PCI/PCI-X mode(bus frequency, width).
3. Remove EOI from reset during intialization.
4. Enable all 8 PCCs if Xframe II adapter.
5. Programs the RLDRAM size depending on the device.
(Note: RLDRAM size on XFARME-I is 64Mb whereas on XFRAME-II it's 32 Mb).
6. Enable extended(64-bit) statistics counters.
7. Program timer interrupt duration based on PCI/PCI-X clock speed.
8. Not required to save/restore PCI config space before/after reset.
Signed-off-by: Ravinandan Arakali <ravinandan.arakali@neterion.com>
Signed-off-by: Raghavendra Koushik <raghavendra.koushik@neterion.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/s2io-regs.h | 53 | ||||
-rw-r--r-- | drivers/net/s2io.c | 462 | ||||
-rw-r--r-- | drivers/net/s2io.h | 64 |
3 files changed, 471 insertions, 108 deletions
diff --git a/drivers/net/s2io-regs.h b/drivers/net/s2io-regs.h index 826deb0eb03a..159d87648f64 100644 --- a/drivers/net/s2io-regs.h +++ b/drivers/net/s2io-regs.h | |||
@@ -91,7 +91,21 @@ typedef struct _XENA_dev_config { | |||
91 | SERR_SOURCE_MC | \ | 91 | SERR_SOURCE_MC | \ |
92 | SERR_SOURCE_XGXS) | 92 | SERR_SOURCE_XGXS) |
93 | 93 | ||
94 | u8 unused_0[0x800 - 0x120]; | 94 | u64 pci_mode; |
95 | #define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60) | ||
96 | #define PCI_MODE_PCI_33 0 | ||
97 | #define PCI_MODE_PCI_66 0x1 | ||
98 | #define PCI_MODE_PCIX_M1_66 0x2 | ||
99 | #define PCI_MODE_PCIX_M1_100 0x3 | ||
100 | #define PCI_MODE_PCIX_M1_133 0x4 | ||
101 | #define PCI_MODE_PCIX_M2_66 0x5 | ||
102 | #define PCI_MODE_PCIX_M2_100 0x6 | ||
103 | #define PCI_MODE_PCIX_M2_133 0x7 | ||
104 | #define PCI_MODE_UNSUPPORTED BIT(0) | ||
105 | #define PCI_MODE_32_BITS BIT(8) | ||
106 | #define PCI_MODE_UNKNOWN_MODE BIT(9) | ||
107 | |||
108 | u8 unused_0[0x800 - 0x128]; | ||
95 | 109 | ||
96 | /* PCI-X Controller registers */ | 110 | /* PCI-X Controller registers */ |
97 | u64 pic_int_status; | 111 | u64 pic_int_status; |
@@ -223,19 +237,16 @@ typedef struct _XENA_dev_config { | |||
223 | u64 xmsi_data; | 237 | u64 xmsi_data; |
224 | 238 | ||
225 | u64 rx_mat; | 239 | u64 rx_mat; |
240 | #define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8) | ||
226 | 241 | ||
227 | u8 unused6[0x8]; | 242 | u8 unused6[0x8]; |
228 | 243 | ||
229 | u64 tx_mat0_7; | 244 | u64 tx_mat0_n[0x8]; |
230 | u64 tx_mat8_15; | 245 | #define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8) |
231 | u64 tx_mat16_23; | ||
232 | u64 tx_mat24_31; | ||
233 | u64 tx_mat32_39; | ||
234 | u64 tx_mat40_47; | ||
235 | u64 tx_mat48_55; | ||
236 | u64 tx_mat56_63; | ||
237 | 246 | ||
238 | u8 unused_1[0x10]; | 247 | u8 unused_1[0x8]; |
248 | u64 stat_byte_cnt; | ||
249 | #define STAT_BC(n) vBIT(n,4,12) | ||
239 | 250 | ||
240 | /* Automated statistics collection */ | 251 | /* Automated statistics collection */ |
241 | u64 stat_cfg; | 252 | u64 stat_cfg; |
@@ -269,7 +280,12 @@ typedef struct _XENA_dev_config { | |||
269 | u64 gpio_control; | 280 | u64 gpio_control; |
270 | #define GPIO_CTRL_GPIO_0 BIT(8) | 281 | #define GPIO_CTRL_GPIO_0 BIT(8) |
271 | 282 | ||
272 | u8 unused7[0x600]; | 283 | u8 unused7_1[0x240 - 0x200]; |
284 | |||
285 | u64 wreq_split_mask; | ||
286 | #define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12) | ||
287 | |||
288 | u8 unused7_2[0x800 - 0x248]; | ||
273 | 289 | ||
274 | /* TxDMA registers */ | 290 | /* TxDMA registers */ |
275 | u64 txdma_int_status; | 291 | u64 txdma_int_status; |
@@ -470,6 +486,7 @@ typedef struct _XENA_dev_config { | |||
470 | #define PRC_CTRL_NO_SNOOP (BIT(22)|BIT(23)) | 486 | #define PRC_CTRL_NO_SNOOP (BIT(22)|BIT(23)) |
471 | #define PRC_CTRL_NO_SNOOP_DESC BIT(22) | 487 | #define PRC_CTRL_NO_SNOOP_DESC BIT(22) |
472 | #define PRC_CTRL_NO_SNOOP_BUFF BIT(23) | 488 | #define PRC_CTRL_NO_SNOOP_BUFF BIT(23) |
489 | #define PRC_CTRL_BIMODAL_INTERRUPT BIT(37) | ||
473 | #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) | 490 | #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) |
474 | 491 | ||
475 | u64 prc_alarm_action; | 492 | u64 prc_alarm_action; |
@@ -742,7 +759,19 @@ typedef struct _XENA_dev_config { | |||
742 | u64 mc_rldram_test_d1; | 759 | u64 mc_rldram_test_d1; |
743 | u8 unused24[0x300 - 0x288]; | 760 | u8 unused24[0x300 - 0x288]; |
744 | u64 mc_rldram_test_d2; | 761 | u64 mc_rldram_test_d2; |
745 | u8 unused25[0x700 - 0x308]; | 762 | |
763 | u8 unused24_1[0x360 - 0x308]; | ||
764 | u64 mc_rldram_ctrl; | ||
765 | #define MC_RLDRAM_ENABLE_ODT BIT(7) | ||
766 | |||
767 | u8 unused24_2[0x640 - 0x368]; | ||
768 | u64 mc_rldram_ref_per_herc; | ||
769 | #define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16) | ||
770 | |||
771 | u8 unused24_3[0x660 - 0x648]; | ||
772 | u64 mc_rldram_mrs_herc; | ||
773 | |||
774 | u8 unused25[0x700 - 0x668]; | ||
746 | u64 mc_debug_ctrl; | 775 | u64 mc_debug_ctrl; |
747 | 776 | ||
748 | u8 unused26[0x3000 - 0x2f08]; | 777 | u8 unused26[0x3000 - 0x2f08]; |
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c index db3e394c740b..15e2ee9f9703 100644 --- a/drivers/net/s2io.c +++ b/drivers/net/s2io.c | |||
@@ -84,9 +84,10 @@ static inline int RXD_IS_UP2DT(RxD_t *rxdp) | |||
84 | * problem, 600B, 600C, 600D, 640B, 640C and 640D. | 84 | * problem, 600B, 600C, 600D, 640B, 640C and 640D. |
85 | * macro below identifies these cards given the subsystem_id. | 85 | * macro below identifies these cards given the subsystem_id. |
86 | */ | 86 | */ |
87 | #define CARDS_WITH_FAULTY_LINK_INDICATORS(subid) \ | 87 | #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \ |
88 | (((subid >= 0x600B) && (subid <= 0x600D)) || \ | 88 | (dev_type == XFRAME_I_DEVICE) ? \ |
89 | ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0 | 89 | ((((subid >= 0x600B) && (subid <= 0x600D)) || \ |
90 | ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0 | ||
90 | 91 | ||
91 | #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \ | 92 | #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \ |
92 | ADAPTER_STATUS_RMAC_LOCAL_FAULT))) | 93 | ADAPTER_STATUS_RMAC_LOCAL_FAULT))) |
@@ -207,7 +208,24 @@ static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid) | |||
207 | #define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL | 208 | #define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL |
208 | #define END_SIGN 0x0 | 209 | #define END_SIGN 0x0 |
209 | 210 | ||
210 | static u64 default_mdio_cfg[] = { | 211 | static u64 herc_act_dtx_cfg[] = { |
212 | /* Set address */ | ||
213 | 0x80000515BA750000ULL, 0x80000515BA7500E0ULL, | ||
214 | /* Write data */ | ||
215 | 0x80000515BA750004ULL, 0x80000515BA7500E4ULL, | ||
216 | /* Set address */ | ||
217 | 0x80010515003F0000ULL, 0x80010515003F00E0ULL, | ||
218 | /* Write data */ | ||
219 | 0x80010515003F0004ULL, 0x80010515003F00E4ULL, | ||
220 | /* Set address */ | ||
221 | 0x80020515F2100000ULL, 0x80020515F21000E0ULL, | ||
222 | /* Write data */ | ||
223 | 0x80020515F2100004ULL, 0x80020515F21000E4ULL, | ||
224 | /* Done */ | ||
225 | END_SIGN | ||
226 | }; | ||
227 | |||
228 | static u64 xena_mdio_cfg[] = { | ||
211 | /* Reset PMA PLL */ | 229 | /* Reset PMA PLL */ |
212 | 0xC001010000000000ULL, 0xC0010100000000E0ULL, | 230 | 0xC001010000000000ULL, 0xC0010100000000E0ULL, |
213 | 0xC0010100008000E4ULL, | 231 | 0xC0010100008000E4ULL, |
@@ -217,7 +235,7 @@ static u64 default_mdio_cfg[] = { | |||
217 | END_SIGN | 235 | END_SIGN |
218 | }; | 236 | }; |
219 | 237 | ||
220 | static u64 default_dtx_cfg[] = { | 238 | static u64 xena_dtx_cfg[] = { |
221 | 0x8000051500000000ULL, 0x80000515000000E0ULL, | 239 | 0x8000051500000000ULL, 0x80000515000000E0ULL, |
222 | 0x80000515D93500E4ULL, 0x8001051500000000ULL, | 240 | 0x80000515D93500E4ULL, 0x8001051500000000ULL, |
223 | 0x80010515000000E0ULL, 0x80010515001E00E4ULL, | 241 | 0x80010515000000E0ULL, 0x80010515001E00E4ULL, |
@@ -656,6 +674,87 @@ static void free_shared_mem(struct s2io_nic *nic) | |||
656 | } | 674 | } |
657 | 675 | ||
658 | /** | 676 | /** |
677 | * s2io_verify_pci_mode - | ||
678 | */ | ||
679 | |||
680 | static int s2io_verify_pci_mode(nic_t *nic) | ||
681 | { | ||
682 | XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; | ||
683 | register u64 val64 = 0; | ||
684 | int mode; | ||
685 | |||
686 | val64 = readq(&bar0->pci_mode); | ||
687 | mode = (u8)GET_PCI_MODE(val64); | ||
688 | |||
689 | if ( val64 & PCI_MODE_UNKNOWN_MODE) | ||
690 | return -1; /* Unknown PCI mode */ | ||
691 | return mode; | ||
692 | } | ||
693 | |||
694 | |||
695 | /** | ||
696 | * s2io_print_pci_mode - | ||
697 | */ | ||
698 | static int s2io_print_pci_mode(nic_t *nic) | ||
699 | { | ||
700 | XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; | ||
701 | register u64 val64 = 0; | ||
702 | int mode; | ||
703 | struct config_param *config = &nic->config; | ||
704 | |||
705 | val64 = readq(&bar0->pci_mode); | ||
706 | mode = (u8)GET_PCI_MODE(val64); | ||
707 | |||
708 | if ( val64 & PCI_MODE_UNKNOWN_MODE) | ||
709 | return -1; /* Unknown PCI mode */ | ||
710 | |||
711 | if (val64 & PCI_MODE_32_BITS) { | ||
712 | DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name); | ||
713 | } else { | ||
714 | DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name); | ||
715 | } | ||
716 | |||
717 | switch(mode) { | ||
718 | case PCI_MODE_PCI_33: | ||
719 | DBG_PRINT(ERR_DBG, "33MHz PCI bus\n"); | ||
720 | config->bus_speed = 33; | ||
721 | break; | ||
722 | case PCI_MODE_PCI_66: | ||
723 | DBG_PRINT(ERR_DBG, "66MHz PCI bus\n"); | ||
724 | config->bus_speed = 133; | ||
725 | break; | ||
726 | case PCI_MODE_PCIX_M1_66: | ||
727 | DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n"); | ||
728 | config->bus_speed = 133; /* Herc doubles the clock rate */ | ||
729 | break; | ||
730 | case PCI_MODE_PCIX_M1_100: | ||
731 | DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n"); | ||
732 | config->bus_speed = 200; | ||
733 | break; | ||
734 | case PCI_MODE_PCIX_M1_133: | ||
735 | DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n"); | ||
736 | config->bus_speed = 266; | ||
737 | break; | ||
738 | case PCI_MODE_PCIX_M2_66: | ||
739 | DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n"); | ||
740 | config->bus_speed = 133; | ||
741 | break; | ||
742 | case PCI_MODE_PCIX_M2_100: | ||
743 | DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n"); | ||
744 | config->bus_speed = 200; | ||
745 | break; | ||
746 | case PCI_MODE_PCIX_M2_133: | ||
747 | DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n"); | ||
748 | config->bus_speed = 266; | ||
749 | break; | ||
750 | default: | ||
751 | return -1; /* Unsupported bus speed */ | ||
752 | } | ||
753 | |||
754 | return mode; | ||
755 | } | ||
756 | |||
757 | /** | ||
659 | * init_nic - Initialization of hardware | 758 | * init_nic - Initialization of hardware |
660 | * @nic: device peivate variable | 759 | * @nic: device peivate variable |
661 | * Description: The function sequentially configures every block | 760 | * Description: The function sequentially configures every block |
@@ -687,6 +786,16 @@ static int init_nic(struct s2io_nic *nic) | |||
687 | return -1; | 786 | return -1; |
688 | } | 787 | } |
689 | 788 | ||
789 | /* | ||
790 | * Herc requires EOI to be removed from reset before XGXS, so.. | ||
791 | */ | ||
792 | if (nic->device_type & XFRAME_II_DEVICE) { | ||
793 | val64 = 0xA500000000ULL; | ||
794 | writeq(val64, &bar0->sw_reset); | ||
795 | msleep(500); | ||
796 | val64 = readq(&bar0->sw_reset); | ||
797 | } | ||
798 | |||
690 | /* Remove XGXS from reset state */ | 799 | /* Remove XGXS from reset state */ |
691 | val64 = 0; | 800 | val64 = 0; |
692 | writeq(val64, &bar0->sw_reset); | 801 | writeq(val64, &bar0->sw_reset); |
@@ -718,41 +827,51 @@ static int init_nic(struct s2io_nic *nic) | |||
718 | * of 64 bit values into two registers in a particular | 827 | * of 64 bit values into two registers in a particular |
719 | * sequence. Hence a macro 'SWITCH_SIGN' has been defined | 828 | * sequence. Hence a macro 'SWITCH_SIGN' has been defined |
720 | * which will be defined in the array of configuration values | 829 | * which will be defined in the array of configuration values |
721 | * (default_dtx_cfg & default_mdio_cfg) at appropriate places | 830 | * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places |
722 | * to switch writing from one regsiter to another. We continue | 831 | * to switch writing from one regsiter to another. We continue |
723 | * writing these values until we encounter the 'END_SIGN' macro. | 832 | * writing these values until we encounter the 'END_SIGN' macro. |
724 | * For example, After making a series of 21 writes into | 833 | * For example, After making a series of 21 writes into |
725 | * dtx_control register the 'SWITCH_SIGN' appears and hence we | 834 | * dtx_control register the 'SWITCH_SIGN' appears and hence we |
726 | * start writing into mdio_control until we encounter END_SIGN. | 835 | * start writing into mdio_control until we encounter END_SIGN. |
727 | */ | 836 | */ |
728 | while (1) { | 837 | if (nic->device_type & XFRAME_II_DEVICE) { |
729 | dtx_cfg: | 838 | while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) { |
730 | while (default_dtx_cfg[dtx_cnt] != END_SIGN) { | 839 | SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt], |
731 | if (default_dtx_cfg[dtx_cnt] == SWITCH_SIGN) { | ||
732 | dtx_cnt++; | ||
733 | goto mdio_cfg; | ||
734 | } | ||
735 | SPECIAL_REG_WRITE(default_dtx_cfg[dtx_cnt], | ||
736 | &bar0->dtx_control, UF); | 840 | &bar0->dtx_control, UF); |
737 | val64 = readq(&bar0->dtx_control); | 841 | if (dtx_cnt & 0x1) |
842 | msleep(1); /* Necessary!! */ | ||
738 | dtx_cnt++; | 843 | dtx_cnt++; |
739 | } | 844 | } |
740 | mdio_cfg: | 845 | } else { |
741 | while (default_mdio_cfg[mdio_cnt] != END_SIGN) { | 846 | while (1) { |
742 | if (default_mdio_cfg[mdio_cnt] == SWITCH_SIGN) { | 847 | dtx_cfg: |
848 | while (xena_dtx_cfg[dtx_cnt] != END_SIGN) { | ||
849 | if (xena_dtx_cfg[dtx_cnt] == SWITCH_SIGN) { | ||
850 | dtx_cnt++; | ||
851 | goto mdio_cfg; | ||
852 | } | ||
853 | SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt], | ||
854 | &bar0->dtx_control, UF); | ||
855 | val64 = readq(&bar0->dtx_control); | ||
856 | dtx_cnt++; | ||
857 | } | ||
858 | mdio_cfg: | ||
859 | while (xena_mdio_cfg[mdio_cnt] != END_SIGN) { | ||
860 | if (xena_mdio_cfg[mdio_cnt] == SWITCH_SIGN) { | ||
861 | mdio_cnt++; | ||
862 | goto dtx_cfg; | ||
863 | } | ||
864 | SPECIAL_REG_WRITE(xena_mdio_cfg[mdio_cnt], | ||
865 | &bar0->mdio_control, UF); | ||
866 | val64 = readq(&bar0->mdio_control); | ||
743 | mdio_cnt++; | 867 | mdio_cnt++; |
868 | } | ||
869 | if ((xena_dtx_cfg[dtx_cnt] == END_SIGN) && | ||
870 | (xena_mdio_cfg[mdio_cnt] == END_SIGN)) { | ||
871 | break; | ||
872 | } else { | ||
744 | goto dtx_cfg; | 873 | goto dtx_cfg; |
745 | } | 874 | } |
746 | SPECIAL_REG_WRITE(default_mdio_cfg[mdio_cnt], | ||
747 | &bar0->mdio_control, UF); | ||
748 | val64 = readq(&bar0->mdio_control); | ||
749 | mdio_cnt++; | ||
750 | } | ||
751 | if ((default_dtx_cfg[dtx_cnt] == END_SIGN) && | ||
752 | (default_mdio_cfg[mdio_cnt] == END_SIGN)) { | ||
753 | break; | ||
754 | } else { | ||
755 | goto dtx_cfg; | ||
756 | } | 875 | } |
757 | } | 876 | } |
758 | 877 | ||
@@ -803,7 +922,8 @@ static int init_nic(struct s2io_nic *nic) | |||
803 | * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug | 922 | * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug |
804 | * SXE-008 TRANSMIT DMA ARBITRATION ISSUE. | 923 | * SXE-008 TRANSMIT DMA ARBITRATION ISSUE. |
805 | */ | 924 | */ |
806 | if (get_xena_rev_id(nic->pdev) < 4) | 925 | if ((nic->device_type == XFRAME_I_DEVICE) && |
926 | (get_xena_rev_id(nic->pdev) < 4)) | ||
807 | writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable); | 927 | writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable); |
808 | 928 | ||
809 | val64 = readq(&bar0->tx_fifo_partition_0); | 929 | val64 = readq(&bar0->tx_fifo_partition_0); |
@@ -833,7 +953,11 @@ static int init_nic(struct s2io_nic *nic) | |||
833 | * configured Rings. | 953 | * configured Rings. |
834 | */ | 954 | */ |
835 | val64 = 0; | 955 | val64 = 0; |
836 | mem_size = 64; | 956 | if (nic->device_type & XFRAME_II_DEVICE) |
957 | mem_size = 32; | ||
958 | else | ||
959 | mem_size = 64; | ||
960 | |||
837 | for (i = 0; i < config->rx_ring_num; i++) { | 961 | for (i = 0; i < config->rx_ring_num; i++) { |
838 | switch (i) { | 962 | switch (i) { |
839 | case 0: | 963 | case 0: |
@@ -1116,6 +1240,11 @@ static int init_nic(struct s2io_nic *nic) | |||
1116 | /* Program statistics memory */ | 1240 | /* Program statistics memory */ |
1117 | writeq(mac_control->stats_mem_phy, &bar0->stat_addr); | 1241 | writeq(mac_control->stats_mem_phy, &bar0->stat_addr); |
1118 | 1242 | ||
1243 | if (nic->device_type == XFRAME_II_DEVICE) { | ||
1244 | val64 = STAT_BC(0x320); | ||
1245 | writeq(val64, &bar0->stat_byte_cnt); | ||
1246 | } | ||
1247 | |||
1119 | /* | 1248 | /* |
1120 | * Initializing the sampling rate for the device to calculate the | 1249 | * Initializing the sampling rate for the device to calculate the |
1121 | * bandwidth utilization. | 1250 | * bandwidth utilization. |
@@ -1134,12 +1263,18 @@ static int init_nic(struct s2io_nic *nic) | |||
1134 | * 250 interrupts per sec. Continuous interrupts are enabled | 1263 | * 250 interrupts per sec. Continuous interrupts are enabled |
1135 | * by default. | 1264 | * by default. |
1136 | */ | 1265 | */ |
1137 | val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078) | | 1266 | if (nic->device_type == XFRAME_II_DEVICE) { |
1138 | TTI_DATA1_MEM_TX_URNG_A(0xA) | | 1267 | int count = (nic->config.bus_speed * 125)/2; |
1268 | val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count); | ||
1269 | } else { | ||
1270 | |||
1271 | val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078); | ||
1272 | } | ||
1273 | val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) | | ||
1139 | TTI_DATA1_MEM_TX_URNG_B(0x10) | | 1274 | TTI_DATA1_MEM_TX_URNG_B(0x10) | |
1140 | TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN; | 1275 | TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN; |
1141 | if (use_continuous_tx_intrs) | 1276 | if (use_continuous_tx_intrs) |
1142 | val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN; | 1277 | val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN; |
1143 | writeq(val64, &bar0->tti_data1_mem); | 1278 | writeq(val64, &bar0->tti_data1_mem); |
1144 | 1279 | ||
1145 | val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | | 1280 | val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | |
@@ -1171,9 +1306,19 @@ static int init_nic(struct s2io_nic *nic) | |||
1171 | time++; | 1306 | time++; |
1172 | } | 1307 | } |
1173 | 1308 | ||
1309 | |||
1174 | /* RTI Initialization */ | 1310 | /* RTI Initialization */ |
1175 | val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF) | | 1311 | if (nic->device_type == XFRAME_II_DEVICE) { |
1176 | RTI_DATA1_MEM_RX_URNG_A(0xA) | | 1312 | /* |
1313 | * Programmed to generate Apprx 500 Intrs per | ||
1314 | * second | ||
1315 | */ | ||
1316 | int count = (nic->config.bus_speed * 125)/4; | ||
1317 | val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count); | ||
1318 | } else { | ||
1319 | val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF); | ||
1320 | } | ||
1321 | val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) | | ||
1177 | RTI_DATA1_MEM_RX_URNG_B(0x10) | | 1322 | RTI_DATA1_MEM_RX_URNG_B(0x10) | |
1178 | RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN; | 1323 | RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN; |
1179 | 1324 | ||
@@ -1267,6 +1412,15 @@ static int init_nic(struct s2io_nic *nic) | |||
1267 | val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits); | 1412 | val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits); |
1268 | writeq(val64, &bar0->pic_control); | 1413 | writeq(val64, &bar0->pic_control); |
1269 | 1414 | ||
1415 | /* | ||
1416 | * Programming the Herc to split every write transaction | ||
1417 | * that does not start on an ADB to reduce disconnects. | ||
1418 | */ | ||
1419 | if (nic->device_type == XFRAME_II_DEVICE) { | ||
1420 | val64 = WREQ_SPLIT_MASK_SET_MASK(255); | ||
1421 | writeq(val64, &bar0->wreq_split_mask); | ||
1422 | } | ||
1423 | |||
1270 | return SUCCESS; | 1424 | return SUCCESS; |
1271 | } | 1425 | } |
1272 | 1426 | ||
@@ -1509,18 +1663,18 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag) | |||
1509 | } | 1663 | } |
1510 | } | 1664 | } |
1511 | 1665 | ||
1512 | static int check_prc_pcc_state(u64 val64, int flag, int rev_id) | 1666 | static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc) |
1513 | { | 1667 | { |
1514 | int ret = 0; | 1668 | int ret = 0; |
1515 | 1669 | ||
1516 | if (flag == FALSE) { | 1670 | if (flag == FALSE) { |
1517 | if (rev_id >= 4) { | 1671 | if ((!herc && (rev_id >= 4)) || herc) { |
1518 | if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) && | 1672 | if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) && |
1519 | ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == | 1673 | ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == |
1520 | ADAPTER_STATUS_RC_PRC_QUIESCENT)) { | 1674 | ADAPTER_STATUS_RC_PRC_QUIESCENT)) { |
1521 | ret = 1; | 1675 | ret = 1; |
1522 | } | 1676 | } |
1523 | } else { | 1677 | }else { |
1524 | if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) && | 1678 | if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) && |
1525 | ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == | 1679 | ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == |
1526 | ADAPTER_STATUS_RC_PRC_QUIESCENT)) { | 1680 | ADAPTER_STATUS_RC_PRC_QUIESCENT)) { |
@@ -1528,7 +1682,7 @@ static int check_prc_pcc_state(u64 val64, int flag, int rev_id) | |||
1528 | } | 1682 | } |
1529 | } | 1683 | } |
1530 | } else { | 1684 | } else { |
1531 | if (rev_id >= 4) { | 1685 | if ((!herc && (rev_id >= 4)) || herc) { |
1532 | if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) == | 1686 | if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) == |
1533 | ADAPTER_STATUS_RMAC_PCC_IDLE) && | 1687 | ADAPTER_STATUS_RMAC_PCC_IDLE) && |
1534 | (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) || | 1688 | (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) || |
@@ -1564,10 +1718,11 @@ static int check_prc_pcc_state(u64 val64, int flag, int rev_id) | |||
1564 | 1718 | ||
1565 | static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag) | 1719 | static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag) |
1566 | { | 1720 | { |
1567 | int ret = 0; | 1721 | int ret = 0, herc; |
1568 | u64 tmp64 = ~((u64) val64); | 1722 | u64 tmp64 = ~((u64) val64); |
1569 | int rev_id = get_xena_rev_id(sp->pdev); | 1723 | int rev_id = get_xena_rev_id(sp->pdev); |
1570 | 1724 | ||
1725 | herc = (sp->device_type == XFRAME_II_DEVICE); | ||
1571 | if (! | 1726 | if (! |
1572 | (tmp64 & | 1727 | (tmp64 & |
1573 | (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY | | 1728 | (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY | |
@@ -1575,7 +1730,7 @@ static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag) | |||
1575 | ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY | | 1730 | ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY | |
1576 | ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK | | 1731 | ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK | |
1577 | ADAPTER_STATUS_P_PLL_LOCK))) { | 1732 | ADAPTER_STATUS_P_PLL_LOCK))) { |
1578 | ret = check_prc_pcc_state(val64, flag, rev_id); | 1733 | ret = check_prc_pcc_state(val64, flag, rev_id, herc); |
1579 | } | 1734 | } |
1580 | 1735 | ||
1581 | return ret; | 1736 | return ret; |
@@ -1706,7 +1861,8 @@ static int start_nic(struct s2io_nic *nic) | |||
1706 | 1861 | ||
1707 | /* SXE-002: Initialize link and activity LED */ | 1862 | /* SXE-002: Initialize link and activity LED */ |
1708 | subid = nic->pdev->subsystem_device; | 1863 | subid = nic->pdev->subsystem_device; |
1709 | if ((subid & 0xFF) >= 0x07) { | 1864 | if (((subid & 0xFF) >= 0x07) && |
1865 | (nic->device_type == XFRAME_I_DEVICE)) { | ||
1710 | val64 = readq(&bar0->gpio_control); | 1866 | val64 = readq(&bar0->gpio_control); |
1711 | val64 |= 0x0000800000000000ULL; | 1867 | val64 |= 0x0000800000000000ULL; |
1712 | writeq(val64, &bar0->gpio_control); | 1868 | writeq(val64, &bar0->gpio_control); |
@@ -2541,9 +2697,12 @@ void s2io_reset(nic_t * sp) | |||
2541 | */ | 2697 | */ |
2542 | msleep(250); | 2698 | msleep(250); |
2543 | 2699 | ||
2700 | if (!(sp->device_type & XFRAME_II_DEVICE)) { | ||
2544 | /* Restore the PCI state saved during initializarion. */ | 2701 | /* Restore the PCI state saved during initializarion. */ |
2545 | pci_restore_state(sp->pdev); | 2702 | pci_restore_state(sp->pdev); |
2546 | 2703 | } else { | |
2704 | pci_set_master(sp->pdev); | ||
2705 | } | ||
2547 | s2io_init_pci(sp); | 2706 | s2io_init_pci(sp); |
2548 | 2707 | ||
2549 | msleep(250); | 2708 | msleep(250); |
@@ -2568,7 +2727,8 @@ void s2io_reset(nic_t * sp) | |||
2568 | 2727 | ||
2569 | /* SXE-002: Configure link and activity LED to turn it off */ | 2728 | /* SXE-002: Configure link and activity LED to turn it off */ |
2570 | subid = sp->pdev->subsystem_device; | 2729 | subid = sp->pdev->subsystem_device; |
2571 | if ((subid & 0xFF) >= 0x07) { | 2730 | if (((subid & 0xFF) >= 0x07) && |
2731 | (sp->device_type == XFRAME_I_DEVICE)) { | ||
2572 | val64 = readq(&bar0->gpio_control); | 2732 | val64 = readq(&bar0->gpio_control); |
2573 | val64 |= 0x0000800000000000ULL; | 2733 | val64 |= 0x0000800000000000ULL; |
2574 | writeq(val64, &bar0->gpio_control); | 2734 | writeq(val64, &bar0->gpio_control); |
@@ -2576,6 +2736,15 @@ void s2io_reset(nic_t * sp) | |||
2576 | writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700)); | 2736 | writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700)); |
2577 | } | 2737 | } |
2578 | 2738 | ||
2739 | /* | ||
2740 | * Clear spurious ECC interrupts that would have occured on | ||
2741 | * XFRAME II cards after reset. | ||
2742 | */ | ||
2743 | if (sp->device_type == XFRAME_II_DEVICE) { | ||
2744 | val64 = readq(&bar0->pcc_err_reg); | ||
2745 | writeq(val64, &bar0->pcc_err_reg); | ||
2746 | } | ||
2747 | |||
2579 | sp->device_enabled_once = FALSE; | 2748 | sp->device_enabled_once = FALSE; |
2580 | } | 2749 | } |
2581 | 2750 | ||
@@ -3463,7 +3632,8 @@ static void s2io_phy_id(unsigned long data) | |||
3463 | u16 subid; | 3632 | u16 subid; |
3464 | 3633 | ||
3465 | subid = sp->pdev->subsystem_device; | 3634 | subid = sp->pdev->subsystem_device; |
3466 | if ((subid & 0xFF) >= 0x07) { | 3635 | if ((sp->device_type == XFRAME_II_DEVICE) || |
3636 | ((subid & 0xFF) >= 0x07)) { | ||
3467 | val64 = readq(&bar0->gpio_control); | 3637 | val64 = readq(&bar0->gpio_control); |
3468 | val64 ^= GPIO_CTRL_GPIO_0; | 3638 | val64 ^= GPIO_CTRL_GPIO_0; |
3469 | writeq(val64, &bar0->gpio_control); | 3639 | writeq(val64, &bar0->gpio_control); |
@@ -3500,7 +3670,8 @@ static int s2io_ethtool_idnic(struct net_device *dev, u32 data) | |||
3500 | 3670 | ||
3501 | subid = sp->pdev->subsystem_device; | 3671 | subid = sp->pdev->subsystem_device; |
3502 | last_gpio_ctrl_val = readq(&bar0->gpio_control); | 3672 | last_gpio_ctrl_val = readq(&bar0->gpio_control); |
3503 | if ((subid & 0xFF) < 0x07) { | 3673 | if ((sp->device_type == XFRAME_I_DEVICE) && |
3674 | ((subid & 0xFF) < 0x07)) { | ||
3504 | val64 = readq(&bar0->adapter_control); | 3675 | val64 = readq(&bar0->adapter_control); |
3505 | if (!(val64 & ADAPTER_CNTL_EN)) { | 3676 | if (!(val64 & ADAPTER_CNTL_EN)) { |
3506 | printk(KERN_ERR | 3677 | printk(KERN_ERR |
@@ -3520,7 +3691,7 @@ static int s2io_ethtool_idnic(struct net_device *dev, u32 data) | |||
3520 | msleep_interruptible(MAX_FLICKER_TIME); | 3691 | msleep_interruptible(MAX_FLICKER_TIME); |
3521 | del_timer_sync(&sp->id_timer); | 3692 | del_timer_sync(&sp->id_timer); |
3522 | 3693 | ||
3523 | if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) { | 3694 | if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) { |
3524 | writeq(last_gpio_ctrl_val, &bar0->gpio_control); | 3695 | writeq(last_gpio_ctrl_val, &bar0->gpio_control); |
3525 | last_gpio_ctrl_val = readq(&bar0->gpio_control); | 3696 | last_gpio_ctrl_val = readq(&bar0->gpio_control); |
3526 | } | 3697 | } |
@@ -4134,44 +4305,91 @@ static void s2io_get_ethtool_stats(struct net_device *dev, | |||
4134 | StatInfo_t *stat_info = sp->mac_control.stats_info; | 4305 | StatInfo_t *stat_info = sp->mac_control.stats_info; |
4135 | 4306 | ||
4136 | s2io_updt_stats(sp); | 4307 | s2io_updt_stats(sp); |
4137 | tmp_stats[i++] = le32_to_cpu(stat_info->tmac_frms); | 4308 | tmp_stats[i++] = |
4138 | tmp_stats[i++] = le32_to_cpu(stat_info->tmac_data_octets); | 4309 | (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 | |
4310 | le32_to_cpu(stat_info->tmac_frms); | ||
4311 | tmp_stats[i++] = | ||
4312 | (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 | | ||
4313 | le32_to_cpu(stat_info->tmac_data_octets); | ||
4139 | tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms); | 4314 | tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms); |
4140 | tmp_stats[i++] = le32_to_cpu(stat_info->tmac_mcst_frms); | 4315 | tmp_stats[i++] = |
4141 | tmp_stats[i++] = le32_to_cpu(stat_info->tmac_bcst_frms); | 4316 | (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 | |
4317 | le32_to_cpu(stat_info->tmac_mcst_frms); | ||
4318 | tmp_stats[i++] = | ||
4319 | (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 | | ||
4320 | le32_to_cpu(stat_info->tmac_bcst_frms); | ||
4142 | tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms); | 4321 | tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms); |
4143 | tmp_stats[i++] = le32_to_cpu(stat_info->tmac_any_err_frms); | 4322 | tmp_stats[i++] = |
4323 | (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 | | ||
4324 | le32_to_cpu(stat_info->tmac_any_err_frms); | ||
4144 | tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets); | 4325 | tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets); |
4145 | tmp_stats[i++] = le32_to_cpu(stat_info->tmac_vld_ip); | 4326 | tmp_stats[i++] = |
4146 | tmp_stats[i++] = le32_to_cpu(stat_info->tmac_drop_ip); | 4327 | (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 | |
4147 | tmp_stats[i++] = le32_to_cpu(stat_info->tmac_icmp); | 4328 | le32_to_cpu(stat_info->tmac_vld_ip); |
4148 | tmp_stats[i++] = le32_to_cpu(stat_info->tmac_rst_tcp); | 4329 | tmp_stats[i++] = |
4330 | (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 | | ||
4331 | le32_to_cpu(stat_info->tmac_drop_ip); | ||
4332 | tmp_stats[i++] = | ||
4333 | (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 | | ||
4334 | le32_to_cpu(stat_info->tmac_icmp); | ||
4335 | tmp_stats[i++] = | ||
4336 | (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 | | ||
4337 | le32_to_cpu(stat_info->tmac_rst_tcp); | ||
4149 | tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp); | 4338 | tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp); |
4150 | tmp_stats[i++] = le32_to_cpu(stat_info->tmac_udp); | 4339 | tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 | |
4151 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_vld_frms); | 4340 | le32_to_cpu(stat_info->tmac_udp); |
4152 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_data_octets); | 4341 | tmp_stats[i++] = |
4342 | (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 | | ||
4343 | le32_to_cpu(stat_info->rmac_vld_frms); | ||
4344 | tmp_stats[i++] = | ||
4345 | (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 | | ||
4346 | le32_to_cpu(stat_info->rmac_data_octets); | ||
4153 | tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms); | 4347 | tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms); |
4154 | tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms); | 4348 | tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms); |
4155 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_vld_mcst_frms); | 4349 | tmp_stats[i++] = |
4156 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_vld_bcst_frms); | 4350 | (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 | |
4351 | le32_to_cpu(stat_info->rmac_vld_mcst_frms); | ||
4352 | tmp_stats[i++] = | ||
4353 | (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 | | ||
4354 | le32_to_cpu(stat_info->rmac_vld_bcst_frms); | ||
4157 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms); | 4355 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms); |
4158 | tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms); | 4356 | tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms); |
4159 | tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms); | 4357 | tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms); |
4160 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_discarded_frms); | 4358 | tmp_stats[i++] = |
4161 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_usized_frms); | 4359 | (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 | |
4162 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_osized_frms); | 4360 | le32_to_cpu(stat_info->rmac_discarded_frms); |
4163 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_frag_frms); | 4361 | tmp_stats[i++] = |
4164 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_jabber_frms); | 4362 | (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 | |
4165 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ip); | 4363 | le32_to_cpu(stat_info->rmac_usized_frms); |
4364 | tmp_stats[i++] = | ||
4365 | (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 | | ||
4366 | le32_to_cpu(stat_info->rmac_osized_frms); | ||
4367 | tmp_stats[i++] = | ||
4368 | (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 | | ||
4369 | le32_to_cpu(stat_info->rmac_frag_frms); | ||
4370 | tmp_stats[i++] = | ||
4371 | (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 | | ||
4372 | le32_to_cpu(stat_info->rmac_jabber_frms); | ||
4373 | tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 | | ||
4374 | le32_to_cpu(stat_info->rmac_ip); | ||
4166 | tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets); | 4375 | tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets); |
4167 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip); | 4376 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip); |
4168 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_drop_ip); | 4377 | tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 | |
4169 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_icmp); | 4378 | le32_to_cpu(stat_info->rmac_drop_ip); |
4379 | tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 | | ||
4380 | le32_to_cpu(stat_info->rmac_icmp); | ||
4170 | tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp); | 4381 | tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp); |
4171 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_udp); | 4382 | tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 | |
4172 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_drp_udp); | 4383 | le32_to_cpu(stat_info->rmac_udp); |
4173 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pause_cnt); | 4384 | tmp_stats[i++] = |
4174 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_accepted_ip); | 4385 | (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 | |
4386 | le32_to_cpu(stat_info->rmac_err_drp_udp); | ||
4387 | tmp_stats[i++] = | ||
4388 | (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 | | ||
4389 | le32_to_cpu(stat_info->rmac_pause_cnt); | ||
4390 | tmp_stats[i++] = | ||
4391 | (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 | | ||
4392 | le32_to_cpu(stat_info->rmac_accepted_ip); | ||
4175 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp); | 4393 | tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp); |
4176 | tmp_stats[i++] = 0; | 4394 | tmp_stats[i++] = 0; |
4177 | tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs; | 4395 | tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs; |
@@ -4401,7 +4619,8 @@ static void s2io_set_link(unsigned long data) | |||
4401 | val64 = readq(&bar0->adapter_control); | 4619 | val64 = readq(&bar0->adapter_control); |
4402 | val64 |= ADAPTER_CNTL_EN; | 4620 | val64 |= ADAPTER_CNTL_EN; |
4403 | writeq(val64, &bar0->adapter_control); | 4621 | writeq(val64, &bar0->adapter_control); |
4404 | if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) { | 4622 | if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type, |
4623 | subid)) { | ||
4405 | val64 = readq(&bar0->gpio_control); | 4624 | val64 = readq(&bar0->gpio_control); |
4406 | val64 |= GPIO_CTRL_GPIO_0; | 4625 | val64 |= GPIO_CTRL_GPIO_0; |
4407 | writeq(val64, &bar0->gpio_control); | 4626 | writeq(val64, &bar0->gpio_control); |
@@ -4423,7 +4642,8 @@ static void s2io_set_link(unsigned long data) | |||
4423 | } | 4642 | } |
4424 | s2io_link(nic, LINK_UP); | 4643 | s2io_link(nic, LINK_UP); |
4425 | } else { | 4644 | } else { |
4426 | if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) { | 4645 | if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type, |
4646 | subid)) { | ||
4427 | val64 = readq(&bar0->gpio_control); | 4647 | val64 = readq(&bar0->gpio_control); |
4428 | val64 &= ~GPIO_CTRL_GPIO_0; | 4648 | val64 &= ~GPIO_CTRL_GPIO_0; |
4429 | writeq(val64, &bar0->gpio_control); | 4649 | writeq(val64, &bar0->gpio_control); |
@@ -4708,7 +4928,6 @@ static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp) | |||
4708 | netif_rx(skb); | 4928 | netif_rx(skb); |
4709 | } | 4929 | } |
4710 | #endif | 4930 | #endif |
4711 | |||
4712 | dev->last_rx = jiffies; | 4931 | dev->last_rx = jiffies; |
4713 | atomic_dec(&sp->rx_bufs_left[ring_no]); | 4932 | atomic_dec(&sp->rx_bufs_left[ring_no]); |
4714 | return SUCCESS; | 4933 | return SUCCESS; |
@@ -4842,6 +5061,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) | |||
4842 | u16 subid; | 5061 | u16 subid; |
4843 | mac_info_t *mac_control; | 5062 | mac_info_t *mac_control; |
4844 | struct config_param *config; | 5063 | struct config_param *config; |
5064 | int mode; | ||
4845 | 5065 | ||
4846 | #ifdef CONFIG_S2IO_NAPI | 5066 | #ifdef CONFIG_S2IO_NAPI |
4847 | DBG_PRINT(ERR_DBG, "NAPI support has been enabled\n"); | 5067 | DBG_PRINT(ERR_DBG, "NAPI support has been enabled\n"); |
@@ -4898,6 +5118,12 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) | |||
4898 | sp->high_dma_flag = dma_flag; | 5118 | sp->high_dma_flag = dma_flag; |
4899 | sp->device_enabled_once = FALSE; | 5119 | sp->device_enabled_once = FALSE; |
4900 | 5120 | ||
5121 | if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) || | ||
5122 | (pdev->device == PCI_DEVICE_ID_HERC_UNI)) | ||
5123 | sp->device_type = XFRAME_II_DEVICE; | ||
5124 | else | ||
5125 | sp->device_type = XFRAME_I_DEVICE; | ||
5126 | |||
4901 | /* Initialize some PCI/PCI-X fields of the NIC. */ | 5127 | /* Initialize some PCI/PCI-X fields of the NIC. */ |
4902 | s2io_init_pci(sp); | 5128 | s2io_init_pci(sp); |
4903 | 5129 | ||
@@ -5033,7 +5259,9 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) | |||
5033 | INIT_WORK(&sp->set_link_task, | 5259 | INIT_WORK(&sp->set_link_task, |
5034 | (void (*)(void *)) s2io_set_link, sp); | 5260 | (void (*)(void *)) s2io_set_link, sp); |
5035 | 5261 | ||
5036 | pci_save_state(sp->pdev); | 5262 | if (!(sp->device_type & XFRAME_II_DEVICE)) { |
5263 | pci_save_state(sp->pdev); | ||
5264 | } | ||
5037 | 5265 | ||
5038 | /* Setting swapper control on the NIC, for proper reset operation */ | 5266 | /* Setting swapper control on the NIC, for proper reset operation */ |
5039 | if (s2io_set_swapper(sp)) { | 5267 | if (s2io_set_swapper(sp)) { |
@@ -5043,12 +5271,26 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) | |||
5043 | goto set_swap_failed; | 5271 | goto set_swap_failed; |
5044 | } | 5272 | } |
5045 | 5273 | ||
5046 | /* | 5274 | /* Verify if the Herc works on the slot its placed into */ |
5047 | * Fix for all "FFs" MAC address problems observed on | 5275 | if (sp->device_type & XFRAME_II_DEVICE) { |
5048 | * Alpha platforms | 5276 | mode = s2io_verify_pci_mode(sp); |
5049 | */ | 5277 | if (mode < 0) { |
5050 | fix_mac_address(sp); | 5278 | DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__); |
5051 | s2io_reset(sp); | 5279 | DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n"); |
5280 | ret = -EBADSLT; | ||
5281 | goto set_swap_failed; | ||
5282 | } | ||
5283 | } | ||
5284 | |||
5285 | /* Not needed for Herc */ | ||
5286 | if (sp->device_type & XFRAME_I_DEVICE) { | ||
5287 | /* | ||
5288 | * Fix for all "FFs" MAC address problems observed on | ||
5289 | * Alpha platforms | ||
5290 | */ | ||
5291 | fix_mac_address(sp); | ||
5292 | s2io_reset(sp); | ||
5293 | } | ||
5052 | 5294 | ||
5053 | /* | 5295 | /* |
5054 | * MAC address initialization. | 5296 | * MAC address initialization. |
@@ -5073,22 +5315,13 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) | |||
5073 | sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16); | 5315 | sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16); |
5074 | sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24); | 5316 | sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24); |
5075 | 5317 | ||
5076 | DBG_PRINT(INIT_DBG, | ||
5077 | "DEFAULT MAC ADDR:0x%02x-%02x-%02x-%02x-%02x-%02x\n", | ||
5078 | sp->def_mac_addr[0].mac_addr[0], | ||
5079 | sp->def_mac_addr[0].mac_addr[1], | ||
5080 | sp->def_mac_addr[0].mac_addr[2], | ||
5081 | sp->def_mac_addr[0].mac_addr[3], | ||
5082 | sp->def_mac_addr[0].mac_addr[4], | ||
5083 | sp->def_mac_addr[0].mac_addr[5]); | ||
5084 | |||
5085 | /* Set the factory defined MAC address initially */ | 5318 | /* Set the factory defined MAC address initially */ |
5086 | dev->addr_len = ETH_ALEN; | 5319 | dev->addr_len = ETH_ALEN; |
5087 | memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN); | 5320 | memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN); |
5088 | 5321 | ||
5089 | /* | 5322 | /* |
5090 | * Initialize the tasklet status and link state flags | 5323 | * Initialize the tasklet status and link state flags |
5091 | * and the card statte parameter | 5324 | * and the card state parameter |
5092 | */ | 5325 | */ |
5093 | atomic_set(&(sp->card_state), 0); | 5326 | atomic_set(&(sp->card_state), 0); |
5094 | sp->tasklet_status = 0; | 5327 | sp->tasklet_status = 0; |
@@ -5123,9 +5356,46 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) | |||
5123 | goto register_failed; | 5356 | goto register_failed; |
5124 | } | 5357 | } |
5125 | 5358 | ||
5359 | if (sp->device_type & XFRAME_II_DEVICE) { | ||
5360 | DBG_PRINT(ERR_DBG, "%s: Neterion Xframe II 10GbE adapter ", | ||
5361 | dev->name); | ||
5362 | DBG_PRINT(ERR_DBG, "(rev %d), Driver %s\n", | ||
5363 | get_xena_rev_id(sp->pdev), | ||
5364 | s2io_driver_version); | ||
5365 | DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n", | ||
5366 | sp->def_mac_addr[0].mac_addr[0], | ||
5367 | sp->def_mac_addr[0].mac_addr[1], | ||
5368 | sp->def_mac_addr[0].mac_addr[2], | ||
5369 | sp->def_mac_addr[0].mac_addr[3], | ||
5370 | sp->def_mac_addr[0].mac_addr[4], | ||
5371 | sp->def_mac_addr[0].mac_addr[5]); | ||
5372 | int mode = s2io_print_pci_mode(sp); | ||
5373 | if (mode < 0) { | ||
5374 | DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode "); | ||
5375 | ret = -EBADSLT; | ||
5376 | goto set_swap_failed; | ||
5377 | } | ||
5378 | } else { | ||
5379 | DBG_PRINT(ERR_DBG, "%s: Neterion Xframe I 10GbE adapter ", | ||
5380 | dev->name); | ||
5381 | DBG_PRINT(ERR_DBG, "(rev %d), Driver %s\n", | ||
5382 | get_xena_rev_id(sp->pdev), | ||
5383 | s2io_driver_version); | ||
5384 | DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n", | ||
5385 | sp->def_mac_addr[0].mac_addr[0], | ||
5386 | sp->def_mac_addr[0].mac_addr[1], | ||
5387 | sp->def_mac_addr[0].mac_addr[2], | ||
5388 | sp->def_mac_addr[0].mac_addr[3], | ||
5389 | sp->def_mac_addr[0].mac_addr[4], | ||
5390 | sp->def_mac_addr[0].mac_addr[5]); | ||
5391 | } | ||
5392 | |||
5126 | /* Initialize device name */ | 5393 | /* Initialize device name */ |
5127 | strcpy(sp->name, dev->name); | 5394 | strcpy(sp->name, dev->name); |
5128 | strcat(sp->name, ": Neterion Xframe I 10GbE adapter"); | 5395 | if (sp->device_type & XFRAME_II_DEVICE) |
5396 | strcat(sp->name, ": Neterion Xframe II 10GbE adapter"); | ||
5397 | else | ||
5398 | strcat(sp->name, ": Neterion Xframe I 10GbE adapter"); | ||
5129 | 5399 | ||
5130 | /* | 5400 | /* |
5131 | * Make Link state as off at this point, when the Link change | 5401 | * Make Link state as off at this point, when the Link change |
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h index b924ef21814a..df8cfd0475be 100644 --- a/drivers/net/s2io.h +++ b/drivers/net/s2io.h | |||
@@ -201,6 +201,67 @@ typedef struct stat_block { | |||
201 | u32 rxf_wr_cnt; | 201 | u32 rxf_wr_cnt; |
202 | u32 txf_rd_cnt; | 202 | u32 txf_rd_cnt; |
203 | 203 | ||
204 | /* Tx MAC statistics overflow counters. */ | ||
205 | u32 tmac_data_octets_oflow; | ||
206 | u32 tmac_frms_oflow; | ||
207 | u32 tmac_bcst_frms_oflow; | ||
208 | u32 tmac_mcst_frms_oflow; | ||
209 | u32 tmac_ucst_frms_oflow; | ||
210 | u32 tmac_ttl_octets_oflow; | ||
211 | u32 tmac_any_err_frms_oflow; | ||
212 | u32 tmac_nucst_frms_oflow; | ||
213 | u64 tmac_vlan_frms; | ||
214 | u32 tmac_drop_ip_oflow; | ||
215 | u32 tmac_vld_ip_oflow; | ||
216 | u32 tmac_rst_tcp_oflow; | ||
217 | u32 tmac_icmp_oflow; | ||
218 | u32 tpa_unknown_protocol; | ||
219 | u32 tmac_udp_oflow; | ||
220 | u32 reserved_10; | ||
221 | u32 tpa_parse_failure; | ||
222 | |||
223 | /* Rx MAC Statistics overflow counters. */ | ||
224 | u32 rmac_data_octets_oflow; | ||
225 | u32 rmac_vld_frms_oflow; | ||
226 | u32 rmac_vld_bcst_frms_oflow; | ||
227 | u32 rmac_vld_mcst_frms_oflow; | ||
228 | u32 rmac_accepted_ucst_frms_oflow; | ||
229 | u32 rmac_ttl_octets_oflow; | ||
230 | u32 rmac_discarded_frms_oflow; | ||
231 | u32 rmac_accepted_nucst_frms_oflow; | ||
232 | u32 rmac_usized_frms_oflow; | ||
233 | u32 rmac_drop_events_oflow; | ||
234 | u32 rmac_frag_frms_oflow; | ||
235 | u32 rmac_osized_frms_oflow; | ||
236 | u32 rmac_ip_oflow; | ||
237 | u32 rmac_jabber_frms_oflow; | ||
238 | u32 rmac_icmp_oflow; | ||
239 | u32 rmac_drop_ip_oflow; | ||
240 | u32 rmac_err_drp_udp_oflow; | ||
241 | u32 rmac_udp_oflow; | ||
242 | u32 reserved_11; | ||
243 | u32 rmac_pause_cnt_oflow; | ||
244 | u64 rmac_ttl_1519_4095_frms; | ||
245 | u64 rmac_ttl_4096_8191_frms; | ||
246 | u64 rmac_ttl_8192_max_frms; | ||
247 | u64 rmac_ttl_gt_max_frms; | ||
248 | u64 rmac_osized_alt_frms; | ||
249 | u64 rmac_jabber_alt_frms; | ||
250 | u64 rmac_gt_max_alt_frms; | ||
251 | u64 rmac_vlan_frms; | ||
252 | u32 rmac_len_discard; | ||
253 | u32 rmac_fcs_discard; | ||
254 | u32 rmac_pf_discard; | ||
255 | u32 rmac_da_discard; | ||
256 | u32 rmac_red_discard; | ||
257 | u32 rmac_rts_discard; | ||
258 | u32 reserved_12; | ||
259 | u32 rmac_ingm_full_discard; | ||
260 | u32 reserved_13; | ||
261 | u32 rmac_accepted_ip_oflow; | ||
262 | u32 reserved_14; | ||
263 | u32 link_fault_cnt; | ||
264 | |||
204 | /* Software statistics maintained by driver */ | 265 | /* Software statistics maintained by driver */ |
205 | swStat_t sw_stat; | 266 | swStat_t sw_stat; |
206 | } StatInfo_t; | 267 | } StatInfo_t; |
@@ -690,6 +751,9 @@ struct s2io_nic { | |||
690 | atomic_t card_state; | 751 | atomic_t card_state; |
691 | volatile unsigned long link_state; | 752 | volatile unsigned long link_state; |
692 | struct vlan_group *vlgrp; | 753 | struct vlan_group *vlgrp; |
754 | #define XFRAME_I_DEVICE 1 | ||
755 | #define XFRAME_II_DEVICE 2 | ||
756 | u8 device_type; | ||
693 | 757 | ||
694 | spinlock_t rx_lock; | 758 | spinlock_t rx_lock; |
695 | atomic_t isr_cnt; | 759 | atomic_t isr_cnt; |