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authorDale Farnsworth <dale@farnsworth.org>2006-01-16 19:00:24 -0500
committerJeff Garzik <jgarzik@pobox.com>2006-01-17 07:23:39 -0500
commitc2e5b352fcefb644959a0c8b1bb2e297f0d4ac3d (patch)
tree65972fbb796b4f08e66600faf53e7046fcb0702c /drivers/net
parentab4384a6588925607f734e195f49e34a80f31e84 (diff)
[PATCH] mv643xx_eth: Remove needless mask of extended intr register
All interrupts controlled by the extended mask register are also masked by a bit in the main mask register, so there is no need to directly manipulate the extended mask register. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> mv643xx_eth.c | 81 ++++++++++++++++++---------------------------------------- 1 file changed, 26 insertions(+), 55 deletions(-) Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/mv643xx_eth.c81
1 files changed, 26 insertions, 55 deletions
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index 6118ea799a65..40ae36b20c9d 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -62,10 +62,10 @@
62#define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN 62#define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
63#define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7) 63#define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
64 64
65#define INT_CAUSE_UNMASK_ALL 0x0007ffff 65#define INT_UNMASK_ALL 0x0007ffff
66#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff 66#define INT_UNMASK_ALL_EXT 0x0011ffff
67#define INT_CAUSE_MASK_ALL 0x00000000 67#define INT_MASK_ALL 0x00000000
68#define INT_CAUSE_MASK_ALL_EXT 0x00000000 68#define INT_MASK_ALL_EXT 0x00000000
69#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL 69#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
70#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT 70#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
71 71
@@ -205,7 +205,7 @@ static void mv643xx_eth_rx_task(void *data)
205 else { 205 else {
206 /* Return interrupts */ 206 /* Return interrupts */
207 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num), 207 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
208 INT_CAUSE_UNMASK_ALL); 208 INT_UNMASK_ALL);
209 } 209 }
210#endif 210#endif
211} 211}
@@ -470,12 +470,12 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
470 470
471 /* Read interrupt cause registers */ 471 /* Read interrupt cause registers */
472 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) & 472 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
473 INT_CAUSE_UNMASK_ALL; 473 INT_UNMASK_ALL;
474 474
475 if (eth_int_cause & BIT1) 475 if (eth_int_cause & BIT1)
476 eth_int_cause_ext = mv_read( 476 eth_int_cause_ext = mv_read(
477 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) & 477 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
478 INT_CAUSE_UNMASK_ALL_EXT; 478 INT_UNMASK_ALL_EXT;
479 479
480#ifdef MV643XX_NAPI 480#ifdef MV643XX_NAPI
481 if (!(eth_int_cause & 0x0007fffd)) { 481 if (!(eth_int_cause & 0x0007fffd)) {
@@ -500,11 +500,10 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
500 } else { 500 } else {
501 if (netif_rx_schedule_prep(dev)) { 501 if (netif_rx_schedule_prep(dev)) {
502 /* Mask all the interrupts */ 502 /* Mask all the interrupts */
503 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0); 503 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
504 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG 504 INT_MASK_ALL);
505 (port_num), 0); 505 /* wait for previous write to complete */
506 /* ensure previous writes have taken effect */ 506 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
507 mv_read(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num));
508 __netif_rx_schedule(dev); 507 __netif_rx_schedule(dev);
509 } 508 }
510#else 509#else
@@ -517,9 +516,9 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
517 * with skb's. 516 * with skb's.
518 */ 517 */
519#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK 518#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
520 /* Unmask all interrupts on ethernet port */ 519 /* Mask all interrupts on ethernet port */
521 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 520 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
522 INT_CAUSE_MASK_ALL); 521 INT_MASK_ALL);
523 /* wait for previous write to take effect */ 522 /* wait for previous write to take effect */
524 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); 523 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
525 524
@@ -857,11 +856,10 @@ static int mv643xx_eth_open(struct net_device *dev)
857 856
858 /* Unmask phy and link status changes interrupts */ 857 /* Unmask phy and link status changes interrupts */
859 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 858 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
860 INT_CAUSE_UNMASK_ALL_EXT); 859 INT_UNMASK_ALL_EXT);
861 860
862 /* Unmask RX buffer and TX end interrupt */ 861 /* Unmask RX buffer and TX end interrupt */
863 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 862 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
864 INT_CAUSE_UNMASK_ALL);
865 return 0; 863 return 0;
866 864
867out_free_tx_skb: 865out_free_tx_skb:
@@ -950,13 +948,9 @@ static int mv643xx_eth_stop(struct net_device *dev)
950 struct mv643xx_private *mp = netdev_priv(dev); 948 struct mv643xx_private *mp = netdev_priv(dev);
951 unsigned int port_num = mp->port_num; 949 unsigned int port_num = mp->port_num;
952 950
953 /* Mask RX buffer and TX end interrupt */ 951 /* Mask all interrupts on ethernet port */
954 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0); 952 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
955 953 /* wait for previous write to complete */
956 /* Mask phy and link status changes interrupts */
957 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
958
959 /* ensure previous writes have taken effect */
960 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); 954 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
961 955
962#ifdef MV643XX_NAPI 956#ifdef MV643XX_NAPI
@@ -1040,9 +1034,7 @@ static int mv643xx_poll(struct net_device *dev, int *budget)
1040 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0); 1034 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1041 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); 1035 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1042 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 1036 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1043 INT_CAUSE_UNMASK_ALL); 1037 INT_UNMASK_ALL);
1044 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1045 INT_CAUSE_UNMASK_ALL_EXT);
1046 } 1038 }
1047 1039
1048 return done ? 0 : 1; 1040 return done ? 0 : 1;
@@ -1307,39 +1299,18 @@ static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1307} 1299}
1308 1300
1309#ifdef CONFIG_NET_POLL_CONTROLLER 1301#ifdef CONFIG_NET_POLL_CONTROLLER
1310static inline void mv643xx_enable_irq(struct mv643xx_private *mp)
1311{
1312 int port_num = mp->port_num;
1313 unsigned long flags;
1314
1315 spin_lock_irqsave(&mp->lock, flags);
1316 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1317 INT_CAUSE_UNMASK_ALL);
1318 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1319 INT_CAUSE_UNMASK_ALL_EXT);
1320 spin_unlock_irqrestore(&mp->lock, flags);
1321}
1322
1323static inline void mv643xx_disable_irq(struct mv643xx_private *mp)
1324{
1325 int port_num = mp->port_num;
1326 unsigned long flags;
1327
1328 spin_lock_irqsave(&mp->lock, flags);
1329 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1330 INT_CAUSE_MASK_ALL);
1331 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1332 INT_CAUSE_MASK_ALL_EXT);
1333 spin_unlock_irqrestore(&mp->lock, flags);
1334}
1335
1336static void mv643xx_netpoll(struct net_device *netdev) 1302static void mv643xx_netpoll(struct net_device *netdev)
1337{ 1303{
1338 struct mv643xx_private *mp = netdev_priv(netdev); 1304 struct mv643xx_private *mp = netdev_priv(netdev);
1305 int port_num = mp->port_num;
1306
1307 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
1308 /* wait for previous write to complete */
1309 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1339 1310
1340 mv643xx_disable_irq(mp);
1341 mv643xx_eth_int_handler(netdev->irq, netdev, NULL); 1311 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
1342 mv643xx_enable_irq(mp); 1312
1313 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
1343} 1314}
1344#endif 1315#endif
1345 1316