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authorMatt Carlson <mcarlson@broadcom.com>2007-11-13 00:19:37 -0500
committerDavid S. Miller <davem@davemloft.net>2007-11-13 00:19:37 -0500
commit5f5c51e3d473d8ddc0c32156c2b27e2fe92b9b57 (patch)
tree46c1c182a79c9aaf4b65cf3a360380c8482bd007 /drivers/net
parentaa6c91fe5913faa2cd2a62de993a3130799412b1 (diff)
[TG3]: Increase the PCI MRRS
Previous devices hardcoded the PCI Maximum Read Request Size to 4K. To better comply with the PCI spec, the hardware now defaults the MRRS to 512 bytes. This will yield poor driver performance if left untouched. This patch increases the MRRS to 4K on driver initialization. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/tg3.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index ecd64a224e95..72db78b1ec3b 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -5098,12 +5098,15 @@ static void tg3_restore_pci_state(struct tg3 *tp)
5098 5098
5099 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); 5099 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5100 5100
5101 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { 5101 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5102 pcie_set_readrq(tp->pdev, 4096);
5103 else {
5102 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, 5104 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5103 tp->pci_cacheline_sz); 5105 tp->pci_cacheline_sz);
5104 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, 5106 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5105 tp->pci_lat_timer); 5107 tp->pci_lat_timer);
5106 } 5108 }
5109
5107 /* Make sure PCI-X relaxed ordering bit is clear. */ 5110 /* Make sure PCI-X relaxed ordering bit is clear. */
5108 if (tp->pcix_cap) { 5111 if (tp->pcix_cap) {
5109 u16 pcix_cmd; 5112 u16 pcix_cmd;
@@ -11215,6 +11218,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11215 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); 11218 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11216 if (pcie_cap != 0) { 11219 if (pcie_cap != 0) {
11217 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; 11220 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11221
11222 pcie_set_readrq(tp->pdev, 4096);
11223
11218 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 11224 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11219 u16 lnkctl; 11225 u16 lnkctl;
11220 11226