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authorGeorge <george0505@realtek.com>2011-02-19 17:29:32 -0500
committerJohn W. Linville <linville@tuxdriver.com>2011-02-21 15:39:58 -0500
commitf0a39ae738d660cb69e486abd20c0dec1cdcb898 (patch)
treeb2a3a6593cb01fa8dd88d5e02ef470b07ad4e727 /drivers/net
parent666e8457fae432ec292e0abc344f8684046fa605 (diff)
rtlwifi: rtl8192cu: Add routine phy
Add the routine rtlwifi/rtl8192cu/phy.c. Most of the code is included from rtlwifi/rtl8192c/phy_common.c. Signed-off-by: George <george0505@realtek.com> Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/phy.c611
1 files changed, 611 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c b/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c
new file mode 100644
index 000000000000..dc65ef2bbeac
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c
@@ -0,0 +1,611 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "rf.h"
37#include "dm.h"
38#include "table.h"
39
40#include "../rtl8192c/phy_common.c"
41
42u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
43 enum radio_path rfpath, u32 regaddr, u32 bitmask)
44{
45 struct rtl_priv *rtlpriv = rtl_priv(hw);
46 u32 original_value, readback_value, bitshift;
47 struct rtl_phy *rtlphy = &(rtlpriv->phy);
48
49 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
50 "rfpath(%#x), bitmask(%#x)\n",
51 regaddr, rfpath, bitmask));
52 if (rtlphy->rf_mode != RF_OP_BY_FW) {
53 original_value = _rtl92c_phy_rf_serial_read(hw,
54 rfpath, regaddr);
55 } else {
56 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
57 rfpath, regaddr);
58 }
59 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
60 readback_value = (original_value & bitmask) >> bitshift;
61 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
62 ("regaddr(%#x), rfpath(%#x), "
63 "bitmask(%#x), original_value(%#x)\n",
64 regaddr, rfpath, bitmask, original_value));
65 return readback_value;
66}
67
68void rtl92c_phy_set_rf_reg(struct ieee80211_hw *hw,
69 enum radio_path rfpath,
70 u32 regaddr, u32 bitmask, u32 data)
71{
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
73 struct rtl_phy *rtlphy = &(rtlpriv->phy);
74 u32 original_value, bitshift;
75
76 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
77 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
78 regaddr, bitmask, data, rfpath));
79 if (rtlphy->rf_mode != RF_OP_BY_FW) {
80 if (bitmask != RFREG_OFFSET_MASK) {
81 original_value = _rtl92c_phy_rf_serial_read(hw,
82 rfpath,
83 regaddr);
84 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
85 data =
86 ((original_value & (~bitmask)) |
87 (data << bitshift));
88 }
89 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
90 } else {
91 if (bitmask != RFREG_OFFSET_MASK) {
92 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
93 rfpath,
94 regaddr);
95 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
96 data =
97 ((original_value & (~bitmask)) |
98 (data << bitshift));
99 }
100 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
101 }
102 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
103 "bitmask(%#x), data(%#x), rfpath(%#x)\n",
104 regaddr, bitmask, data, rfpath));
105}
106
107bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
108{
109 bool rtstatus;
110 struct rtl_priv *rtlpriv = rtl_priv(hw);
111 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
112 bool is92c = IS_92C_SERIAL(rtlhal->version);
113
114 rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
115 if (is92c && IS_HARDWARE_TYPE_8192CE(rtlhal))
116 rtl_write_byte(rtlpriv, 0x14, 0x71);
117 return rtstatus;
118}
119
120bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
121{
122 bool rtstatus = true;
123 struct rtl_priv *rtlpriv = rtl_priv(hw);
124 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
125 u16 regval;
126 u8 b_reg_hwparafile = 1;
127
128 _rtl92c_phy_init_bb_rf_register_definition(hw);
129 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
130 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval | BIT(13) |
131 BIT(0) | BIT(1));
132 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
133 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
134 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
135 if (IS_HARDWARE_TYPE_8192CE(rtlhal)) {
136 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
137 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
138 } else if (IS_HARDWARE_TYPE_8192CU(rtlhal)) {
139 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD |
140 FEN_BB_GLB_RSTn | FEN_BBRSTB);
141 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
142 }
143 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
144 if (b_reg_hwparafile == 1)
145 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
146 return rtstatus;
147}
148
149static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
150{
151 struct rtl_priv *rtlpriv = rtl_priv(hw);
152 struct rtl_phy *rtlphy = &(rtlpriv->phy);
153 u32 i;
154 u32 arraylength;
155 u32 *ptrarray;
156
157 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
158 arraylength = rtlphy->hwparam_tables[MAC_REG].length ;
159 ptrarray = rtlphy->hwparam_tables[MAC_REG].pdata;
160 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
161 ("Img:RTL8192CEMAC_2T_ARRAY\n"));
162 for (i = 0; i < arraylength; i = i + 2)
163 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
164 return true;
165}
166
167static bool _rtl92c_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
168 u8 configtype)
169{
170 int i;
171 u32 *phy_regarray_table;
172 u32 *agctab_array_table;
173 u16 phy_reg_arraylen, agctab_arraylen;
174 struct rtl_priv *rtlpriv = rtl_priv(hw);
175 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
176 struct rtl_phy *rtlphy = &(rtlpriv->phy);
177
178 if (IS_92C_SERIAL(rtlhal->version)) {
179 agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_2T].length;
180 agctab_array_table = rtlphy->hwparam_tables[AGCTAB_2T].pdata;
181 phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_2T].length;
182 phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_2T].pdata;
183 } else {
184 agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_1T].length;
185 agctab_array_table = rtlphy->hwparam_tables[AGCTAB_1T].pdata;
186 phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_1T].length;
187 phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_1T].pdata;
188 }
189 if (configtype == BASEBAND_CONFIG_PHY_REG) {
190 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
191 if (phy_regarray_table[i] == 0xfe)
192 mdelay(50);
193 else if (phy_regarray_table[i] == 0xfd)
194 mdelay(5);
195 else if (phy_regarray_table[i] == 0xfc)
196 mdelay(1);
197 else if (phy_regarray_table[i] == 0xfb)
198 udelay(50);
199 else if (phy_regarray_table[i] == 0xfa)
200 udelay(5);
201 else if (phy_regarray_table[i] == 0xf9)
202 udelay(1);
203 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
204 phy_regarray_table[i + 1]);
205 udelay(1);
206 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
207 ("The phy_regarray_table[0] is %x"
208 " Rtl819XPHY_REGArray[1] is %x\n",
209 phy_regarray_table[i],
210 phy_regarray_table[i + 1]));
211 }
212 rtl92c_phy_config_bb_external_pa(hw);
213 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
214 for (i = 0; i < agctab_arraylen; i = i + 2) {
215 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
216 agctab_array_table[i + 1]);
217 udelay(1);
218 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
219 ("The agctab_array_table[0] is "
220 "%x Rtl819XPHY_REGArray[1] is %x\n",
221 agctab_array_table[i],
222 agctab_array_table[i + 1]));
223 }
224 }
225 return true;
226}
227
228static bool _rtl92c_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
229 u8 configtype)
230{
231 struct rtl_priv *rtlpriv = rtl_priv(hw);
232 struct rtl_phy *rtlphy = &(rtlpriv->phy);
233 int i;
234 u32 *phy_regarray_table_pg;
235 u16 phy_regarray_pg_len;
236
237 rtlphy->pwrgroup_cnt = 0;
238 phy_regarray_pg_len = rtlphy->hwparam_tables[PHY_REG_PG].length;
239 phy_regarray_table_pg = rtlphy->hwparam_tables[PHY_REG_PG].pdata;
240 if (configtype == BASEBAND_CONFIG_PHY_REG) {
241 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
242 if (phy_regarray_table_pg[i] == 0xfe)
243 mdelay(50);
244 else if (phy_regarray_table_pg[i] == 0xfd)
245 mdelay(5);
246 else if (phy_regarray_table_pg[i] == 0xfc)
247 mdelay(1);
248 else if (phy_regarray_table_pg[i] == 0xfb)
249 udelay(50);
250 else if (phy_regarray_table_pg[i] == 0xfa)
251 udelay(5);
252 else if (phy_regarray_table_pg[i] == 0xf9)
253 udelay(1);
254 _rtl92c_store_pwrIndex_diffrate_offset(hw,
255 phy_regarray_table_pg[i],
256 phy_regarray_table_pg[i + 1],
257 phy_regarray_table_pg[i + 2]);
258 }
259 } else {
260 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
261 ("configtype != BaseBand_Config_PHY_REG\n"));
262 }
263 return true;
264}
265
266bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
267 enum radio_path rfpath)
268{
269 int i;
270 u32 *radioa_array_table;
271 u32 *radiob_array_table;
272 u16 radioa_arraylen, radiob_arraylen;
273 struct rtl_priv *rtlpriv = rtl_priv(hw);
274 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
275 struct rtl_phy *rtlphy = &(rtlpriv->phy);
276
277 if (IS_92C_SERIAL(rtlhal->version)) {
278 radioa_arraylen = rtlphy->hwparam_tables[RADIOA_2T].length;
279 radioa_array_table = rtlphy->hwparam_tables[RADIOA_2T].pdata;
280 radiob_arraylen = rtlphy->hwparam_tables[RADIOB_2T].length;
281 radiob_array_table = rtlphy->hwparam_tables[RADIOB_2T].pdata;
282 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
283 ("Radio_A:RTL8192CERADIOA_2TARRAY\n"));
284 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
285 ("Radio_B:RTL8192CE_RADIOB_2TARRAY\n"));
286 } else {
287 radioa_arraylen = rtlphy->hwparam_tables[RADIOA_1T].length;
288 radioa_array_table = rtlphy->hwparam_tables[RADIOA_1T].pdata;
289 radiob_arraylen = rtlphy->hwparam_tables[RADIOB_1T].length;
290 radiob_array_table = rtlphy->hwparam_tables[RADIOB_1T].pdata;
291 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
292 ("Radio_A:RTL8192CE_RADIOA_1TARRAY\n"));
293 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
294 ("Radio_B:RTL8192CE_RADIOB_1TARRAY\n"));
295 }
296 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
297 switch (rfpath) {
298 case RF90_PATH_A:
299 for (i = 0; i < radioa_arraylen; i = i + 2) {
300 if (radioa_array_table[i] == 0xfe)
301 mdelay(50);
302 else if (radioa_array_table[i] == 0xfd)
303 mdelay(5);
304 else if (radioa_array_table[i] == 0xfc)
305 mdelay(1);
306 else if (radioa_array_table[i] == 0xfb)
307 udelay(50);
308 else if (radioa_array_table[i] == 0xfa)
309 udelay(5);
310 else if (radioa_array_table[i] == 0xf9)
311 udelay(1);
312 else {
313 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
314 RFREG_OFFSET_MASK,
315 radioa_array_table[i + 1]);
316 udelay(1);
317 }
318 }
319 _rtl92c_phy_config_rf_external_pa(hw, rfpath);
320 break;
321 case RF90_PATH_B:
322 for (i = 0; i < radiob_arraylen; i = i + 2) {
323 if (radiob_array_table[i] == 0xfe) {
324 mdelay(50);
325 } else if (radiob_array_table[i] == 0xfd)
326 mdelay(5);
327 else if (radiob_array_table[i] == 0xfc)
328 mdelay(1);
329 else if (radiob_array_table[i] == 0xfb)
330 udelay(50);
331 else if (radiob_array_table[i] == 0xfa)
332 udelay(5);
333 else if (radiob_array_table[i] == 0xf9)
334 udelay(1);
335 else {
336 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
337 RFREG_OFFSET_MASK,
338 radiob_array_table[i + 1]);
339 udelay(1);
340 }
341 }
342 break;
343 case RF90_PATH_C:
344 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
345 ("switch case not process\n"));
346 break;
347 case RF90_PATH_D:
348 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
349 ("switch case not process\n"));
350 break;
351 }
352 return true;
353}
354
355void rtl92c_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
356{
357 struct rtl_priv *rtlpriv = rtl_priv(hw);
358 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
359 struct rtl_phy *rtlphy = &(rtlpriv->phy);
360 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
361 u8 reg_bw_opmode;
362 u8 reg_prsr_rsc;
363
364 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
365 ("Switch to %s bandwidth\n",
366 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
367 "20MHz" : "40MHz"))
368 if (is_hal_stop(rtlhal)) {
369 rtlphy->set_bwmode_inprogress = false;
370 return;
371 }
372 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
373 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
374 switch (rtlphy->current_chan_bw) {
375 case HT_CHANNEL_WIDTH_20:
376 reg_bw_opmode |= BW_OPMODE_20MHZ;
377 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
378 break;
379 case HT_CHANNEL_WIDTH_20_40:
380 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
381 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
382 reg_prsr_rsc =
383 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
384 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
385 break;
386 default:
387 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
388 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
389 break;
390 }
391 switch (rtlphy->current_chan_bw) {
392 case HT_CHANNEL_WIDTH_20:
393 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
394 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
395 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
396 break;
397 case HT_CHANNEL_WIDTH_20_40:
398 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
399 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
400 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
401 (mac->cur_40_prime_sc >> 1));
402 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
403 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
404 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
405 (mac->cur_40_prime_sc ==
406 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
407 break;
408 default:
409 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
410 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
411 break;
412 }
413 rtl92c_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
414 rtlphy->set_bwmode_inprogress = false;
415 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
416}
417
418void rtl92c_bb_block_on(struct ieee80211_hw *hw)
419{
420 struct rtl_priv *rtlpriv = rtl_priv(hw);
421
422 mutex_lock(&rtlpriv->io.bb_mutex);
423 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
424 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
425 mutex_unlock(&rtlpriv->io.bb_mutex);
426}
427
428static void _rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
429{
430 u8 tmpreg;
431 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
432 struct rtl_priv *rtlpriv = rtl_priv(hw);
433
434 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
435
436 if ((tmpreg & 0x70) != 0)
437 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
438 else
439 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
440
441 if ((tmpreg & 0x70) != 0) {
442 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
443 if (is2t)
444 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
445 MASK12BITS);
446 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
447 (rf_a_mode & 0x8FFFF) | 0x10000);
448 if (is2t)
449 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
450 (rf_b_mode & 0x8FFFF) | 0x10000);
451 }
452 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
453 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
454 mdelay(100);
455 if ((tmpreg & 0x70) != 0) {
456 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
457 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
458 if (is2t)
459 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
460 rf_b_mode);
461 } else {
462 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
463 }
464}
465
466static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
467 enum rf_pwrstate rfpwr_state)
468{
469 struct rtl_priv *rtlpriv = rtl_priv(hw);
470 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
471 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
472 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
473 bool bresult = true;
474 u8 i, queue_id;
475 struct rtl8192_tx_ring *ring = NULL;
476
477 ppsc->set_rfpowerstate_inprogress = true;
478 switch (rfpwr_state) {
479 case ERFON:
480 if ((ppsc->rfpwr_state == ERFOFF) &&
481 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
482 bool rtstatus;
483 u32 InitializeCount = 0;
484
485 do {
486 InitializeCount++;
487 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
488 ("IPS Set eRf nic enable\n"));
489 rtstatus = rtl_ps_enable_nic(hw);
490 } while ((rtstatus != true)
491 && (InitializeCount < 10));
492 RT_CLEAR_PS_LEVEL(ppsc,
493 RT_RF_OFF_LEVL_HALT_NIC);
494 } else {
495 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
496 ("Set ERFON sleeped:%d ms\n",
497 jiffies_to_msecs(jiffies -
498 ppsc->
499 last_sleep_jiffies)));
500 ppsc->last_awake_jiffies = jiffies;
501 rtl92ce_phy_set_rf_on(hw);
502 }
503 if (mac->link_state == MAC80211_LINKED) {
504 rtlpriv->cfg->ops->led_control(hw,
505 LED_CTL_LINK);
506 } else {
507 rtlpriv->cfg->ops->led_control(hw,
508 LED_CTL_NO_LINK);
509 }
510 break;
511 case ERFOFF:
512 for (queue_id = 0, i = 0;
513 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
514 ring = &pcipriv->dev.tx_ring[queue_id];
515 if (skb_queue_len(&ring->queue) == 0 ||
516 queue_id == BEACON_QUEUE) {
517 queue_id++;
518 continue;
519 } else {
520 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
521 ("eRf Off/Sleep: %d times "
522 "TcbBusyQueue[%d] "
523 "=%d before doze!\n", (i + 1),
524 queue_id,
525 skb_queue_len(&ring->queue)));
526 udelay(10);
527 i++;
528 }
529 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
530 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
531 ("\nERFOFF: %d times "
532 "TcbBusyQueue[%d] = %d !\n",
533 MAX_DOZE_WAITING_TIMES_9x,
534 queue_id,
535 skb_queue_len(&ring->queue)));
536 break;
537 }
538 }
539 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
540 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
541 ("IPS Set eRf nic disable\n"));
542 rtl_ps_disable_nic(hw);
543 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
544 } else {
545 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
546 rtlpriv->cfg->ops->led_control(hw,
547 LED_CTL_NO_LINK);
548 } else {
549 rtlpriv->cfg->ops->led_control(hw,
550 LED_CTL_POWER_OFF);
551 }
552 }
553 break;
554 case ERFSLEEP:
555 if (ppsc->rfpwr_state == ERFOFF)
556 break;
557 for (queue_id = 0, i = 0;
558 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
559 ring = &pcipriv->dev.tx_ring[queue_id];
560 if (skb_queue_len(&ring->queue) == 0) {
561 queue_id++;
562 continue;
563 } else {
564 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
565 ("eRf Off/Sleep: %d times "
566 "TcbBusyQueue[%d] =%d before "
567 "doze!\n", (i + 1), queue_id,
568 skb_queue_len(&ring->queue)));
569 udelay(10);
570 i++;
571 }
572 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
573 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
574 ("\n ERFSLEEP: %d times "
575 "TcbBusyQueue[%d] = %d !\n",
576 MAX_DOZE_WAITING_TIMES_9x,
577 queue_id,
578 skb_queue_len(&ring->queue)));
579 break;
580 }
581 }
582 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
583 ("Set ERFSLEEP awaked:%d ms\n",
584 jiffies_to_msecs(jiffies -
585 ppsc->last_awake_jiffies)));
586 ppsc->last_sleep_jiffies = jiffies;
587 _rtl92ce_phy_set_rf_sleep(hw);
588 break;
589 default:
590 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
591 ("switch case not process\n"));
592 bresult = false;
593 break;
594 }
595 if (bresult)
596 ppsc->rfpwr_state = rfpwr_state;
597 ppsc->set_rfpowerstate_inprogress = false;
598 return bresult;
599}
600
601bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
602 enum rf_pwrstate rfpwr_state)
603{
604 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
605 bool bresult = false;
606
607 if (rfpwr_state == ppsc->rfpwr_state)
608 return bresult;
609 bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
610 return bresult;
611}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 11:30:26 -0500