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authorLinus Torvalds <torvalds@linux-foundation.org>2012-12-13 22:20:31 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-12-13 22:20:31 -0500
commite777d192ffb9f2929d547a2f8a5f65b7db7a9552 (patch)
treec9a82698ae66c0465aeb07908c9063d8c098da27 /drivers/net
parentf132c54e3ab25b305a1e368ad413a417052c966e (diff)
parentf92363d12359498f9a9960511de1a550f0ec41c2 (diff)
Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
Pull first round of SCSI updates from James Bottomley: "This patch set includes two large new drivers: mpt3sas (for the next gen fusion SAS hardware) and csiostor a FCoE offload driver for the Chelsio converged network cards (this includes some net changes which I've OK'd with DaveM). The rest of the patch is driver updates (qla2xxx, lpfc, hptiop, be2iscsi) plus a few assorted updates and bug fixes. We also have a Power Management rework in the Upper Layer Drivers preparatory to doing ACPI zero power optical devices, but the actual enabler is still being worked on. Signed-off-by: James Bottomley <JBottomley@Parallels.com>" * tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (72 commits) [SCSI] mpt3sas: add new driver supporting 12GB SAS [SCSI] scsi_transport_sas: add 12GB definitions for mpt3sas [SCSI] miscdevice: Adding support for MPT3SAS_MINOR(222) [SCSI] csiostor: remove unneeded memset() [SCSI] csiostor: Fix sparse warnings. [SCSI] qla2xxx: Display that driver is operating in legacy interrupt mode. [SCSI] qla2xxx: Dont clear drv active on iospace config failure. [SCSI] qla2xxx: Fix typo in qla2xxx driver. [SCSI] qla2xxx: Update ql2xextended_error_logging parameter description with new option. [SCSI] qla2xxx: Parameterize the link speed of hba rather than fcport. [SCSI] qla2xxx: Add 16Gb/s case to get port speed capability. [SCSI] qla2xxx: Move marking fcport online ahead of setting iiDMA speed. [SCSI] qla2xxx: Add acquiring of risc semaphore before doing ISP reset. [SCSI] qla2xxx: Ignore driver ack bit if corresponding presence bit is not set. [SCSI] qla2xxx: Fix typo in qla83xx_fw_dump function. [SCSI] qla2xxx: Add Gen3 PCIe speed 8GT/s to the log message. [SCSI] qla2xxx: Use correct Request-Q-Out register during bidirectional request processing [SCSI] qla2xxx: Move noisy Start scsi failed messages to verbose logging level. [SCSI] qla2xxx: Fix coccinelle warnings in qla2x00_relogin. [SCSI] qla2xxx: No fcport FC-4 type assignment in GA_NXT response. ...
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c10
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/sge.c6
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_hw.c20
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_msg.h1
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_regs.h36
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h41
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4vf/sge.c8
7 files changed, 93 insertions, 29 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 130dd9d5b493..a27b4ae20f43 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -3203,7 +3203,7 @@ static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3203 memset(c, 0, sizeof(*c)); 3203 memset(c, 0, sizeof(*c));
3204 c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3204 c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3205 FW_CMD_REQUEST | FW_CMD_READ); 3205 FW_CMD_REQUEST | FW_CMD_READ);
3206 c->retval_len16 = htonl(FW_LEN16(*c)); 3206 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3207 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c); 3207 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
3208 if (ret < 0) 3208 if (ret < 0)
3209 return ret; 3209 return ret;
@@ -3397,7 +3397,7 @@ static int adap_init0_config(struct adapter *adapter, int reset)
3397 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3397 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3398 FW_CMD_REQUEST | 3398 FW_CMD_REQUEST |
3399 FW_CMD_READ); 3399 FW_CMD_READ);
3400 caps_cmd.retval_len16 = 3400 caps_cmd.cfvalid_to_len16 =
3401 htonl(FW_CAPS_CONFIG_CMD_CFVALID | 3401 htonl(FW_CAPS_CONFIG_CMD_CFVALID |
3402 FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3402 FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3403 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | 3403 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
@@ -3422,7 +3422,7 @@ static int adap_init0_config(struct adapter *adapter, int reset)
3422 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3422 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3423 FW_CMD_REQUEST | 3423 FW_CMD_REQUEST |
3424 FW_CMD_WRITE); 3424 FW_CMD_WRITE);
3425 caps_cmd.retval_len16 = htonl(FW_LEN16(caps_cmd)); 3425 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3426 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 3426 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3427 NULL); 3427 NULL);
3428 if (ret < 0) 3428 if (ret < 0)
@@ -3497,7 +3497,7 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
3497 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3497 memset(&caps_cmd, 0, sizeof(caps_cmd));
3498 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3498 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3499 FW_CMD_REQUEST | FW_CMD_READ); 3499 FW_CMD_REQUEST | FW_CMD_READ);
3500 caps_cmd.retval_len16 = htonl(FW_LEN16(caps_cmd)); 3500 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3501 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 3501 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3502 &caps_cmd); 3502 &caps_cmd);
3503 if (ret < 0) 3503 if (ret < 0)
@@ -3929,7 +3929,7 @@ static int adap_init0(struct adapter *adap)
3929 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3929 memset(&caps_cmd, 0, sizeof(caps_cmd));
3930 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3930 caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3931 FW_CMD_REQUEST | FW_CMD_READ); 3931 FW_CMD_REQUEST | FW_CMD_READ);
3932 caps_cmd.retval_len16 = htonl(FW_LEN16(caps_cmd)); 3932 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3933 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 3933 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3934 &caps_cmd); 3934 &caps_cmd);
3935 if (ret < 0) 3935 if (ret < 0)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/sge.c b/drivers/net/ethernet/chelsio/cxgb4/sge.c
index 3ecc087d732d..fe9a2ea3588b 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/sge.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/sge.c
@@ -508,7 +508,7 @@ static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
508{ 508{
509 if (q->pend_cred >= 8) { 509 if (q->pend_cred >= 8) {
510 wmb(); 510 wmb();
511 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), DBPRIO | 511 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), DBPRIO(1) |
512 QID(q->cntxt_id) | PIDX(q->pend_cred / 8)); 512 QID(q->cntxt_id) | PIDX(q->pend_cred / 8));
513 q->pend_cred &= 7; 513 q->pend_cred &= 7;
514 } 514 }
@@ -2082,10 +2082,10 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
2082 goto fl_nomem; 2082 goto fl_nomem;
2083 2083
2084 flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc); 2084 flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);
2085 c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN | 2085 c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN(1) |
2086 FW_IQ_CMD_FL0FETCHRO(1) | 2086 FW_IQ_CMD_FL0FETCHRO(1) |
2087 FW_IQ_CMD_FL0DATARO(1) | 2087 FW_IQ_CMD_FL0DATARO(1) |
2088 FW_IQ_CMD_FL0PADEN); 2088 FW_IQ_CMD_FL0PADEN(1));
2089 c.fl0dcaen_to_fl0cidxfthresh = htons(FW_IQ_CMD_FL0FBMIN(2) | 2089 c.fl0dcaen_to_fl0cidxfthresh = htons(FW_IQ_CMD_FL0FBMIN(2) |
2090 FW_IQ_CMD_FL0FBMAX(3)); 2090 FW_IQ_CMD_FL0FBMAX(3));
2091 c.fl0size = htons(flsz); 2091 c.fl0size = htons(flsz);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index 45f2bea2e929..8d9c7547b070 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -648,12 +648,12 @@ static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
648 648
649 if (!byte_cnt || byte_cnt > 4) 649 if (!byte_cnt || byte_cnt > 4)
650 return -EINVAL; 650 return -EINVAL;
651 if (t4_read_reg(adapter, SF_OP) & BUSY) 651 if (t4_read_reg(adapter, SF_OP) & SF_BUSY)
652 return -EBUSY; 652 return -EBUSY;
653 cont = cont ? SF_CONT : 0; 653 cont = cont ? SF_CONT : 0;
654 lock = lock ? SF_LOCK : 0; 654 lock = lock ? SF_LOCK : 0;
655 t4_write_reg(adapter, SF_OP, lock | cont | BYTECNT(byte_cnt - 1)); 655 t4_write_reg(adapter, SF_OP, lock | cont | BYTECNT(byte_cnt - 1));
656 ret = t4_wait_op_done(adapter, SF_OP, BUSY, 0, SF_ATTEMPTS, 5); 656 ret = t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
657 if (!ret) 657 if (!ret)
658 *valp = t4_read_reg(adapter, SF_DATA); 658 *valp = t4_read_reg(adapter, SF_DATA);
659 return ret; 659 return ret;
@@ -676,14 +676,14 @@ static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
676{ 676{
677 if (!byte_cnt || byte_cnt > 4) 677 if (!byte_cnt || byte_cnt > 4)
678 return -EINVAL; 678 return -EINVAL;
679 if (t4_read_reg(adapter, SF_OP) & BUSY) 679 if (t4_read_reg(adapter, SF_OP) & SF_BUSY)
680 return -EBUSY; 680 return -EBUSY;
681 cont = cont ? SF_CONT : 0; 681 cont = cont ? SF_CONT : 0;
682 lock = lock ? SF_LOCK : 0; 682 lock = lock ? SF_LOCK : 0;
683 t4_write_reg(adapter, SF_DATA, val); 683 t4_write_reg(adapter, SF_DATA, val);
684 t4_write_reg(adapter, SF_OP, lock | 684 t4_write_reg(adapter, SF_OP, lock |
685 cont | BYTECNT(byte_cnt - 1) | OP_WR); 685 cont | BYTECNT(byte_cnt - 1) | OP_WR);
686 return t4_wait_op_done(adapter, SF_OP, BUSY, 0, SF_ATTEMPTS, 5); 686 return t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
687} 687}
688 688
689/** 689/**
@@ -2252,14 +2252,14 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
2252 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 2252 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
2253 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i) | EPIOWR); 2253 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i) | EPIOWR);
2254 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 2254 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2255 if (t4_read_reg(adap, EPIO_REG(OP)) & BUSY) 2255 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)
2256 return -ETIMEDOUT; 2256 return -ETIMEDOUT;
2257 2257
2258 /* write CRC */ 2258 /* write CRC */
2259 t4_write_reg(adap, EPIO_REG(DATA0), crc); 2259 t4_write_reg(adap, EPIO_REG(DATA0), crc);
2260 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i + 32) | EPIOWR); 2260 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i + 32) | EPIOWR);
2261 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 2261 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2262 if (t4_read_reg(adap, EPIO_REG(OP)) & BUSY) 2262 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)
2263 return -ETIMEDOUT; 2263 return -ETIMEDOUT;
2264 } 2264 }
2265#undef EPIO_REG 2265#undef EPIO_REG
@@ -2405,7 +2405,7 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
2405retry: 2405retry:
2406 memset(&c, 0, sizeof(c)); 2406 memset(&c, 0, sizeof(c));
2407 INIT_CMD(c, HELLO, WRITE); 2407 INIT_CMD(c, HELLO, WRITE);
2408 c.err_to_mbasyncnot = htonl( 2408 c.err_to_clearinit = htonl(
2409 FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 2409 FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
2410 FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 2410 FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
2411 FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox : 2411 FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
@@ -2426,7 +2426,7 @@ retry:
2426 return ret; 2426 return ret;
2427 } 2427 }
2428 2428
2429 v = ntohl(c.err_to_mbasyncnot); 2429 v = ntohl(c.err_to_clearinit);
2430 master_mbox = FW_HELLO_CMD_MBMASTER_GET(v); 2430 master_mbox = FW_HELLO_CMD_MBMASTER_GET(v);
2431 if (state) { 2431 if (state) {
2432 if (v & FW_HELLO_CMD_ERR) 2432 if (v & FW_HELLO_CMD_ERR)
@@ -2774,7 +2774,7 @@ int t4_fw_config_file(struct adapter *adap, unsigned int mbox,
2774 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 2774 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2775 FW_CMD_REQUEST | 2775 FW_CMD_REQUEST |
2776 FW_CMD_READ); 2776 FW_CMD_READ);
2777 caps_cmd.retval_len16 = 2777 caps_cmd.cfvalid_to_len16 =
2778 htonl(FW_CAPS_CONFIG_CMD_CFVALID | 2778 htonl(FW_CAPS_CONFIG_CMD_CFVALID |
2779 FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 2779 FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
2780 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | 2780 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
@@ -2797,7 +2797,7 @@ int t4_fw_config_file(struct adapter *adap, unsigned int mbox,
2797 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 2797 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2798 FW_CMD_REQUEST | 2798 FW_CMD_REQUEST |
2799 FW_CMD_WRITE); 2799 FW_CMD_WRITE);
2800 caps_cmd.retval_len16 = htonl(FW_LEN16(caps_cmd)); 2800 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
2801 return t4_wr_mbox(adap, mbox, &caps_cmd, sizeof(caps_cmd), NULL); 2801 return t4_wr_mbox(adap, mbox, &caps_cmd, sizeof(caps_cmd), NULL);
2802} 2802}
2803 2803
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h b/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
index eb71b8250b91..b760808fd6d9 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
@@ -658,6 +658,7 @@ struct ulptx_sgl {
658 __be32 cmd_nsge; 658 __be32 cmd_nsge;
659#define ULPTX_CMD(x) ((x) << 24) 659#define ULPTX_CMD(x) ((x) << 24)
660#define ULPTX_NSGE(x) ((x) << 0) 660#define ULPTX_NSGE(x) ((x) << 0)
661#define ULPTX_MORE (1U << 23)
661 __be32 len0; 662 __be32 len0;
662 __be64 addr0; 663 __be64 addr0;
663 struct ulptx_sge_pair sge[0]; 664 struct ulptx_sge_pair sge[0];
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
index a1a8b57200f6..75393f5cff41 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
@@ -67,7 +67,7 @@
67#define QID_MASK 0xffff8000U 67#define QID_MASK 0xffff8000U
68#define QID_SHIFT 15 68#define QID_SHIFT 15
69#define QID(x) ((x) << QID_SHIFT) 69#define QID(x) ((x) << QID_SHIFT)
70#define DBPRIO 0x00004000U 70#define DBPRIO(x) ((x) << 14)
71#define PIDX_MASK 0x00003fffU 71#define PIDX_MASK 0x00003fffU
72#define PIDX_SHIFT 0 72#define PIDX_SHIFT 0
73#define PIDX(x) ((x) << PIDX_SHIFT) 73#define PIDX(x) ((x) << PIDX_SHIFT)
@@ -193,6 +193,12 @@
193#define SGE_FL_BUFFER_SIZE1 0x1048 193#define SGE_FL_BUFFER_SIZE1 0x1048
194#define SGE_FL_BUFFER_SIZE2 0x104c 194#define SGE_FL_BUFFER_SIZE2 0x104c
195#define SGE_FL_BUFFER_SIZE3 0x1050 195#define SGE_FL_BUFFER_SIZE3 0x1050
196#define SGE_FL_BUFFER_SIZE4 0x1054
197#define SGE_FL_BUFFER_SIZE5 0x1058
198#define SGE_FL_BUFFER_SIZE6 0x105c
199#define SGE_FL_BUFFER_SIZE7 0x1060
200#define SGE_FL_BUFFER_SIZE8 0x1064
201
196#define SGE_INGRESS_RX_THRESHOLD 0x10a0 202#define SGE_INGRESS_RX_THRESHOLD 0x10a0
197#define THRESHOLD_0_MASK 0x3f000000U 203#define THRESHOLD_0_MASK 0x3f000000U
198#define THRESHOLD_0_SHIFT 24 204#define THRESHOLD_0_SHIFT 24
@@ -217,6 +223,17 @@
217#define EGRTHRESHOLD(x) ((x) << EGRTHRESHOLDshift) 223#define EGRTHRESHOLD(x) ((x) << EGRTHRESHOLDshift)
218#define EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift) 224#define EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift)
219 225
226#define SGE_DBFIFO_STATUS 0x10a4
227#define HP_INT_THRESH_SHIFT 28
228#define HP_INT_THRESH_MASK 0xfU
229#define HP_INT_THRESH(x) ((x) << HP_INT_THRESH_SHIFT)
230#define LP_INT_THRESH_SHIFT 12
231#define LP_INT_THRESH_MASK 0xfU
232#define LP_INT_THRESH(x) ((x) << LP_INT_THRESH_SHIFT)
233
234#define SGE_DOORBELL_CONTROL 0x10a8
235#define ENABLE_DROP (1 << 13)
236
220#define SGE_TIMER_VALUE_0_AND_1 0x10b8 237#define SGE_TIMER_VALUE_0_AND_1 0x10b8
221#define TIMERVALUE0_MASK 0xffff0000U 238#define TIMERVALUE0_MASK 0xffff0000U
222#define TIMERVALUE0_SHIFT 16 239#define TIMERVALUE0_SHIFT 16
@@ -277,6 +294,10 @@
277#define A_SGE_CTXT_CMD 0x11fc 294#define A_SGE_CTXT_CMD 0x11fc
278#define A_SGE_DBQ_CTXT_BADDR 0x1084 295#define A_SGE_DBQ_CTXT_BADDR 0x1084
279 296
297#define PCIE_PF_CFG 0x40
298#define AIVEC(x) ((x) << 4)
299#define AIVEC_MASK 0x3ffU
300
280#define PCIE_PF_CLI 0x44 301#define PCIE_PF_CLI 0x44
281#define PCIE_INT_CAUSE 0x3004 302#define PCIE_INT_CAUSE 0x3004
282#define UNXSPLCPLERR 0x20000000U 303#define UNXSPLCPLERR 0x20000000U
@@ -322,6 +343,13 @@
322#define PCIE_MEM_ACCESS_OFFSET 0x306c 343#define PCIE_MEM_ACCESS_OFFSET 0x306c
323 344
324#define PCIE_FW 0x30b8 345#define PCIE_FW 0x30b8
346#define PCIE_FW_ERR 0x80000000U
347#define PCIE_FW_INIT 0x40000000U
348#define PCIE_FW_HALT 0x20000000U
349#define PCIE_FW_MASTER_VLD 0x00008000U
350#define PCIE_FW_MASTER(x) ((x) << 12)
351#define PCIE_FW_MASTER_MASK 0x7
352#define PCIE_FW_MASTER_GET(x) (((x) >> 12) & PCIE_FW_MASTER_MASK)
325 353
326#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908 354#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
327#define RNPP 0x80000000U 355#define RNPP 0x80000000U
@@ -432,6 +460,9 @@
432#define MBOWNER(x) ((x) << MBOWNER_SHIFT) 460#define MBOWNER(x) ((x) << MBOWNER_SHIFT)
433#define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT) 461#define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT)
434 462
463#define CIM_PF_HOST_INT_ENABLE 0x288
464#define MBMSGRDYINTEN(x) ((x) << 19)
465
435#define CIM_PF_HOST_INT_CAUSE 0x28c 466#define CIM_PF_HOST_INT_CAUSE 0x28c
436#define MBMSGRDYINT 0x00080000U 467#define MBMSGRDYINT 0x00080000U
437 468
@@ -922,7 +953,7 @@
922 953
923#define SF_DATA 0x193f8 954#define SF_DATA 0x193f8
924#define SF_OP 0x193fc 955#define SF_OP 0x193fc
925#define BUSY 0x80000000U 956#define SF_BUSY 0x80000000U
926#define SF_LOCK 0x00000010U 957#define SF_LOCK 0x00000010U
927#define SF_CONT 0x00000008U 958#define SF_CONT 0x00000008U
928#define BYTECNT_MASK 0x00000006U 959#define BYTECNT_MASK 0x00000006U
@@ -981,6 +1012,7 @@
981#define I2CM 0x00000002U 1012#define I2CM 0x00000002U
982#define CIM 0x00000001U 1013#define CIM 0x00000001U
983 1014
1015#define PL_INT_ENABLE 0x19410
984#define PL_INT_MAP0 0x19414 1016#define PL_INT_MAP0 0x19414
985#define PL_RST 0x19428 1017#define PL_RST 0x19428
986#define PIORST 0x00000002U 1018#define PIORST 0x00000002U
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
index a6364632b490..0abc864cdd3a 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
@@ -68,6 +68,7 @@ struct fw_wr_hdr {
68}; 68};
69 69
70#define FW_WR_OP(x) ((x) << 24) 70#define FW_WR_OP(x) ((x) << 24)
71#define FW_WR_OP_GET(x) (((x) >> 24) & 0xff)
71#define FW_WR_ATOMIC(x) ((x) << 23) 72#define FW_WR_ATOMIC(x) ((x) << 23)
72#define FW_WR_FLUSH(x) ((x) << 22) 73#define FW_WR_FLUSH(x) ((x) << 22)
73#define FW_WR_COMPL(x) ((x) << 21) 74#define FW_WR_COMPL(x) ((x) << 21)
@@ -222,6 +223,7 @@ struct fw_cmd_hdr {
222#define FW_CMD_OP(x) ((x) << 24) 223#define FW_CMD_OP(x) ((x) << 24)
223#define FW_CMD_OP_GET(x) (((x) >> 24) & 0xff) 224#define FW_CMD_OP_GET(x) (((x) >> 24) & 0xff)
224#define FW_CMD_REQUEST (1U << 23) 225#define FW_CMD_REQUEST (1U << 23)
226#define FW_CMD_REQUEST_GET(x) (((x) >> 23) & 0x1)
225#define FW_CMD_READ (1U << 22) 227#define FW_CMD_READ (1U << 22)
226#define FW_CMD_WRITE (1U << 21) 228#define FW_CMD_WRITE (1U << 21)
227#define FW_CMD_EXEC (1U << 20) 229#define FW_CMD_EXEC (1U << 20)
@@ -229,6 +231,7 @@ struct fw_cmd_hdr {
229#define FW_CMD_RETVAL(x) ((x) << 8) 231#define FW_CMD_RETVAL(x) ((x) << 8)
230#define FW_CMD_RETVAL_GET(x) (((x) >> 8) & 0xff) 232#define FW_CMD_RETVAL_GET(x) (((x) >> 8) & 0xff)
231#define FW_CMD_LEN16(x) ((x) << 0) 233#define FW_CMD_LEN16(x) ((x) << 0)
234#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
232 235
233enum fw_ldst_addrspc { 236enum fw_ldst_addrspc {
234 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 237 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
@@ -241,7 +244,8 @@ enum fw_ldst_addrspc {
241 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 244 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
242 FW_LDST_ADDRSPC_MDIO = 0x0018, 245 FW_LDST_ADDRSPC_MDIO = 0x0018,
243 FW_LDST_ADDRSPC_MPS = 0x0020, 246 FW_LDST_ADDRSPC_MPS = 0x0020,
244 FW_LDST_ADDRSPC_FUNC = 0x0028 247 FW_LDST_ADDRSPC_FUNC = 0x0028,
248 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
245}; 249};
246 250
247enum fw_ldst_mps_fid { 251enum fw_ldst_mps_fid {
@@ -303,6 +307,16 @@ struct fw_ldst_cmd {
303 __be64 data0; 307 __be64 data0;
304 __be64 data1; 308 __be64 data1;
305 } func; 309 } func;
310 struct fw_ldst_pcie {
311 u8 ctrl_to_fn;
312 u8 bnum;
313 u8 r;
314 u8 ext_r;
315 u8 select_naccess;
316 u8 pcie_fn;
317 __be16 nset_pkd;
318 __be32 data[12];
319 } pcie;
306 } u; 320 } u;
307}; 321};
308 322
@@ -312,6 +326,9 @@ struct fw_ldst_cmd {
312#define FW_LDST_CMD_FID(x) ((x) << 15) 326#define FW_LDST_CMD_FID(x) ((x) << 15)
313#define FW_LDST_CMD_CTL(x) ((x) << 0) 327#define FW_LDST_CMD_CTL(x) ((x) << 0)
314#define FW_LDST_CMD_RPLCPF(x) ((x) << 0) 328#define FW_LDST_CMD_RPLCPF(x) ((x) << 0)
329#define FW_LDST_CMD_LC (1U << 4)
330#define FW_LDST_CMD_NACCESS(x) ((x) << 0)
331#define FW_LDST_CMD_FN(x) ((x) << 0)
315 332
316struct fw_reset_cmd { 333struct fw_reset_cmd {
317 __be32 op_to_write; 334 __be32 op_to_write;
@@ -333,7 +350,7 @@ enum fw_hellow_cmd {
333struct fw_hello_cmd { 350struct fw_hello_cmd {
334 __be32 op_to_write; 351 __be32 op_to_write;
335 __be32 retval_len16; 352 __be32 retval_len16;
336 __be32 err_to_mbasyncnot; 353 __be32 err_to_clearinit;
337#define FW_HELLO_CMD_ERR (1U << 31) 354#define FW_HELLO_CMD_ERR (1U << 31)
338#define FW_HELLO_CMD_INIT (1U << 30) 355#define FW_HELLO_CMD_INIT (1U << 30)
339#define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29) 356#define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29)
@@ -343,6 +360,7 @@ struct fw_hello_cmd {
343#define FW_HELLO_CMD_MBMASTER(x) ((x) << FW_HELLO_CMD_MBMASTER_SHIFT) 360#define FW_HELLO_CMD_MBMASTER(x) ((x) << FW_HELLO_CMD_MBMASTER_SHIFT)
344#define FW_HELLO_CMD_MBMASTER_GET(x) \ 361#define FW_HELLO_CMD_MBMASTER_GET(x) \
345 (((x) >> FW_HELLO_CMD_MBMASTER_SHIFT) & FW_HELLO_CMD_MBMASTER_MASK) 362 (((x) >> FW_HELLO_CMD_MBMASTER_SHIFT) & FW_HELLO_CMD_MBMASTER_MASK)
363#define FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << 23)
346#define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20) 364#define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20)
347#define FW_HELLO_CMD_STAGE(x) ((x) << 17) 365#define FW_HELLO_CMD_STAGE(x) ((x) << 17)
348#define FW_HELLO_CMD_CLEARINIT (1U << 16) 366#define FW_HELLO_CMD_CLEARINIT (1U << 16)
@@ -428,6 +446,7 @@ enum fw_caps_config_iscsi {
428enum fw_caps_config_fcoe { 446enum fw_caps_config_fcoe {
429 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 447 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
430 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 448 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
449 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
431}; 450};
432 451
433enum fw_memtype_cf { 452enum fw_memtype_cf {
@@ -440,7 +459,7 @@ enum fw_memtype_cf {
440 459
441struct fw_caps_config_cmd { 460struct fw_caps_config_cmd {
442 __be32 op_to_write; 461 __be32 op_to_write;
443 __be32 retval_len16; 462 __be32 cfvalid_to_len16;
444 __be32 r2; 463 __be32 r2;
445 __be32 hwmbitmap; 464 __be32 hwmbitmap;
446 __be16 nbmcaps; 465 __be16 nbmcaps;
@@ -701,8 +720,8 @@ struct fw_iq_cmd {
701#define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6) 720#define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6)
702#define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4) 721#define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4)
703#define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3) 722#define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3)
704#define FW_IQ_CMD_FL0PADEN (1U << 2) 723#define FW_IQ_CMD_FL0PADEN(x) ((x) << 2)
705#define FW_IQ_CMD_FL0PACKEN (1U << 1) 724#define FW_IQ_CMD_FL0PACKEN(x) ((x) << 1)
706#define FW_IQ_CMD_FL0CONGEN (1U << 0) 725#define FW_IQ_CMD_FL0CONGEN (1U << 0)
707 726
708#define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15) 727#define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15)
@@ -1190,6 +1209,14 @@ enum fw_port_dcb_cfg_rc {
1190 FW_PORT_DCB_CFG_ERROR = 0x1 1209 FW_PORT_DCB_CFG_ERROR = 0x1
1191}; 1210};
1192 1211
1212enum fw_port_dcb_type {
1213 FW_PORT_DCB_TYPE_PGID = 0x00,
1214 FW_PORT_DCB_TYPE_PGRATE = 0x01,
1215 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
1216 FW_PORT_DCB_TYPE_PFC = 0x03,
1217 FW_PORT_DCB_TYPE_APP_ID = 0x04,
1218};
1219
1193struct fw_port_cmd { 1220struct fw_port_cmd {
1194 __be32 op_to_portid; 1221 __be32 op_to_portid;
1195 __be32 action_to_len16; 1222 __be32 action_to_len16;
@@ -1257,6 +1284,7 @@ struct fw_port_cmd {
1257#define FW_PORT_CMD_TXIPG(x) ((x) << 19) 1284#define FW_PORT_CMD_TXIPG(x) ((x) << 19)
1258 1285
1259#define FW_PORT_CMD_LSTATUS (1U << 31) 1286#define FW_PORT_CMD_LSTATUS (1U << 31)
1287#define FW_PORT_CMD_LSTATUS_GET(x) (((x) >> 31) & 0x1)
1260#define FW_PORT_CMD_LSPEED(x) ((x) << 24) 1288#define FW_PORT_CMD_LSPEED(x) ((x) << 24)
1261#define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f) 1289#define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f)
1262#define FW_PORT_CMD_TXPAUSE (1U << 23) 1290#define FW_PORT_CMD_TXPAUSE (1U << 23)
@@ -1305,6 +1333,9 @@ enum fw_port_module_type {
1305 FW_PORT_MOD_TYPE_TWINAX_PASSIVE, 1333 FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
1306 FW_PORT_MOD_TYPE_TWINAX_ACTIVE, 1334 FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
1307 FW_PORT_MOD_TYPE_LRM, 1335 FW_PORT_MOD_TYPE_LRM,
1336 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_MASK - 3,
1337 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_MASK - 2,
1338 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_MASK - 1,
1308 1339
1309 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK 1340 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK
1310}; 1341};
diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/sge.c b/drivers/net/ethernet/chelsio/cxgb4vf/sge.c
index f16745f4b36b..92170d50d9d8 100644
--- a/drivers/net/ethernet/chelsio/cxgb4vf/sge.c
+++ b/drivers/net/ethernet/chelsio/cxgb4vf/sge.c
@@ -536,7 +536,7 @@ static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
536 if (fl->pend_cred >= FL_PER_EQ_UNIT) { 536 if (fl->pend_cred >= FL_PER_EQ_UNIT) {
537 wmb(); 537 wmb();
538 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL, 538 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
539 DBPRIO | 539 DBPRIO(1) |
540 QID(fl->cntxt_id) | 540 QID(fl->cntxt_id) |
541 PIDX(fl->pend_cred / FL_PER_EQ_UNIT)); 541 PIDX(fl->pend_cred / FL_PER_EQ_UNIT));
542 fl->pend_cred %= FL_PER_EQ_UNIT; 542 fl->pend_cred %= FL_PER_EQ_UNIT;
@@ -952,7 +952,7 @@ static inline void ring_tx_db(struct adapter *adapter, struct sge_txq *tq,
952 * Warn if we write doorbells with the wrong priority and write 952 * Warn if we write doorbells with the wrong priority and write
953 * descriptors before telling HW. 953 * descriptors before telling HW.
954 */ 954 */
955 WARN_ON((QID(tq->cntxt_id) | PIDX(n)) & DBPRIO); 955 WARN_ON((QID(tq->cntxt_id) | PIDX(n)) & DBPRIO(1));
956 wmb(); 956 wmb();
957 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL, 957 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
958 QID(tq->cntxt_id) | PIDX(n)); 958 QID(tq->cntxt_id) | PIDX(n));
@@ -2126,8 +2126,8 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
2126 cmd.iqns_to_fl0congen = 2126 cmd.iqns_to_fl0congen =
2127 cpu_to_be32( 2127 cpu_to_be32(
2128 FW_IQ_CMD_FL0HOSTFCMODE(SGE_HOSTFCMODE_NONE) | 2128 FW_IQ_CMD_FL0HOSTFCMODE(SGE_HOSTFCMODE_NONE) |
2129 FW_IQ_CMD_FL0PACKEN | 2129 FW_IQ_CMD_FL0PACKEN(1) |
2130 FW_IQ_CMD_FL0PADEN); 2130 FW_IQ_CMD_FL0PADEN(1));
2131 cmd.fl0dcaen_to_fl0cidxfthresh = 2131 cmd.fl0dcaen_to_fl0cidxfthresh =
2132 cpu_to_be16( 2132 cpu_to_be16(
2133 FW_IQ_CMD_FL0FBMIN(SGE_FETCHBURSTMIN_64B) | 2133 FW_IQ_CMD_FL0FBMIN(SGE_FETCHBURSTMIN_64B) |