diff options
author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2011-03-07 16:59:38 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2011-03-14 17:10:14 -0400 |
commit | c5ed53687b39c195b4730de8c0355c1b78054ba6 (patch) | |
tree | 273acc9e661d8d50ce3ccddcb18d933e387eeb5b /drivers/net | |
parent | 4986b996882d82c68ab54b822d7cfdd7dd35f19a (diff) |
net: sh_eth: remove almost #ifdef of SH7763
The SH7763 has GETHER. So the specification of some registers differs than
other CPUs. This patch removes almost #ifdef of CONFIG_CPU_SUBTYPE_SH7763.
Then we are able to add other CPU's GETHER easily.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/sh_eth.c | 72 | ||||
-rw-r--r-- | drivers/net/sh_eth.h | 14 |
2 files changed, 47 insertions, 39 deletions
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index c7abcc586dbd..6734311e56e4 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c | |||
@@ -157,7 +157,7 @@ static void sh_eth_reset(struct net_device *ndev) | |||
157 | int cnt = 100; | 157 | int cnt = 100; |
158 | 158 | ||
159 | sh_eth_write(ndev, EDSR_ENALL, EDSR); | 159 | sh_eth_write(ndev, EDSR_ENALL, EDSR); |
160 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST, EDMR); | 160 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR); |
161 | while (cnt > 0) { | 161 | while (cnt > 0) { |
162 | if (!(sh_eth_read(ndev, EDMR) & 0x3)) | 162 | if (!(sh_eth_read(ndev, EDMR) & 0x3)) |
163 | break; | 163 | break; |
@@ -285,9 +285,9 @@ static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) | |||
285 | /* Chip Reset */ | 285 | /* Chip Reset */ |
286 | static void sh_eth_reset(struct net_device *ndev) | 286 | static void sh_eth_reset(struct net_device *ndev) |
287 | { | 287 | { |
288 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST, EDMR); | 288 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR); |
289 | mdelay(3); | 289 | mdelay(3); |
290 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST, EDMR); | 290 | sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR); |
291 | } | 291 | } |
292 | #endif | 292 | #endif |
293 | 293 | ||
@@ -365,6 +365,22 @@ static void read_mac_address(struct net_device *ndev, unsigned char *mac) | |||
365 | } | 365 | } |
366 | } | 366 | } |
367 | 367 | ||
368 | static int sh_eth_is_gether(struct sh_eth_private *mdp) | ||
369 | { | ||
370 | if (mdp->reg_offset == sh_eth_offset_gigabit) | ||
371 | return 1; | ||
372 | else | ||
373 | return 0; | ||
374 | } | ||
375 | |||
376 | static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) | ||
377 | { | ||
378 | if (sh_eth_is_gether(mdp)) | ||
379 | return EDTRR_TRNS_GETHER; | ||
380 | else | ||
381 | return EDTRR_TRNS_ETHER; | ||
382 | } | ||
383 | |||
368 | struct bb_info { | 384 | struct bb_info { |
369 | struct mdiobb_ctrl ctrl; | 385 | struct mdiobb_ctrl ctrl; |
370 | u32 addr; | 386 | u32 addr; |
@@ -504,9 +520,8 @@ static void sh_eth_ring_format(struct net_device *ndev) | |||
504 | /* Rx descriptor address set */ | 520 | /* Rx descriptor address set */ |
505 | if (i == 0) { | 521 | if (i == 0) { |
506 | sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); | 522 | sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); |
507 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) | 523 | if (sh_eth_is_gether(mdp)) |
508 | sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); | 524 | sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); |
509 | #endif | ||
510 | } | 525 | } |
511 | } | 526 | } |
512 | 527 | ||
@@ -526,9 +541,8 @@ static void sh_eth_ring_format(struct net_device *ndev) | |||
526 | if (i == 0) { | 541 | if (i == 0) { |
527 | /* Tx descriptor address set */ | 542 | /* Tx descriptor address set */ |
528 | sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); | 543 | sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); |
529 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) | 544 | if (sh_eth_is_gether(mdp)) |
530 | sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); | 545 | sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); |
531 | #endif | ||
532 | } | 546 | } |
533 | } | 547 | } |
534 | 548 | ||
@@ -940,9 +954,9 @@ static void sh_eth_error(struct net_device *ndev, int intr_status) | |||
940 | sh_eth_txfree(ndev); | 954 | sh_eth_txfree(ndev); |
941 | 955 | ||
942 | /* SH7712 BUG */ | 956 | /* SH7712 BUG */ |
943 | if (edtrr ^ EDTRR_TRNS) { | 957 | if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { |
944 | /* tx dma start */ | 958 | /* tx dma start */ |
945 | sh_eth_write(ndev, EDTRR_TRNS, EDTRR); | 959 | sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); |
946 | } | 960 | } |
947 | /* wakeup */ | 961 | /* wakeup */ |
948 | netif_wake_queue(ndev); | 962 | netif_wake_queue(ndev); |
@@ -1347,8 +1361,8 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |||
1347 | 1361 | ||
1348 | mdp->cur_tx++; | 1362 | mdp->cur_tx++; |
1349 | 1363 | ||
1350 | if (!(sh_eth_read(ndev, EDTRR) & EDTRR_TRNS)) | 1364 | if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) |
1351 | sh_eth_write(ndev, EDTRR_TRNS, EDTRR); | 1365 | sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); |
1352 | 1366 | ||
1353 | return NETDEV_TX_OK; | 1367 | return NETDEV_TX_OK; |
1354 | } | 1368 | } |
@@ -1406,15 +1420,15 @@ static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) | |||
1406 | sh_eth_write(ndev, 0, CDCR); /* (write clear) */ | 1420 | sh_eth_write(ndev, 0, CDCR); /* (write clear) */ |
1407 | mdp->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR); | 1421 | mdp->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR); |
1408 | sh_eth_write(ndev, 0, LCCR); /* (write clear) */ | 1422 | sh_eth_write(ndev, 0, LCCR); /* (write clear) */ |
1409 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) | 1423 | if (sh_eth_is_gether(mdp)) { |
1410 | mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);/* CERCR */ | 1424 | mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR); |
1411 | sh_eth_write(ndev, 0, CERCR); /* (write clear) */ | 1425 | sh_eth_write(ndev, 0, CERCR); /* (write clear) */ |
1412 | mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);/* CEECR */ | 1426 | mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR); |
1413 | sh_eth_write(ndev, 0, CEECR); /* (write clear) */ | 1427 | sh_eth_write(ndev, 0, CEECR); /* (write clear) */ |
1414 | #else | 1428 | } else { |
1415 | mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR); | 1429 | mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR); |
1416 | sh_eth_write(ndev, 0, CNDCR); /* (write clear) */ | 1430 | sh_eth_write(ndev, 0, CNDCR); /* (write clear) */ |
1417 | #endif | 1431 | } |
1418 | pm_runtime_put_sync(&mdp->pdev->dev); | 1432 | pm_runtime_put_sync(&mdp->pdev->dev); |
1419 | 1433 | ||
1420 | return &mdp->stats; | 1434 | return &mdp->stats; |
@@ -1465,13 +1479,13 @@ static void sh_eth_tsu_init(struct sh_eth_private *mdp) | |||
1465 | sh_eth_tsu_write(mdp, 0, TSU_FWSL0); | 1479 | sh_eth_tsu_write(mdp, 0, TSU_FWSL0); |
1466 | sh_eth_tsu_write(mdp, 0, TSU_FWSL1); | 1480 | sh_eth_tsu_write(mdp, 0, TSU_FWSL1); |
1467 | sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); | 1481 | sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); |
1468 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) | 1482 | if (sh_eth_is_gether(mdp)) { |
1469 | sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ | 1483 | sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ |
1470 | sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ | 1484 | sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ |
1471 | #else | 1485 | } else { |
1472 | sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ | 1486 | sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ |
1473 | sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ | 1487 | sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ |
1474 | #endif | 1488 | } |
1475 | sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ | 1489 | sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ |
1476 | sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ | 1490 | sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ |
1477 | sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ | 1491 | sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ |
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 35a3adbb2e7a..b349c5e2bcda 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h | |||
@@ -400,20 +400,14 @@ enum GECMR_BIT { | |||
400 | enum DMAC_M_BIT { | 400 | enum DMAC_M_BIT { |
401 | EDMR_EL = 0x40, /* Litte endian */ | 401 | EDMR_EL = 0x40, /* Litte endian */ |
402 | EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, | 402 | EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, |
403 | #ifdef CONFIG_CPU_SUBTYPE_SH7763 | 403 | EDMR_SRST_GETHER = 0x03, |
404 | EDMR_SRST = 0x03, | 404 | EDMR_SRST_ETHER = 0x01, |
405 | #else /* CONFIG_CPU_SUBTYPE_SH7763 */ | ||
406 | EDMR_SRST = 0x01, | ||
407 | #endif | ||
408 | }; | 405 | }; |
409 | 406 | ||
410 | /* EDTRR */ | 407 | /* EDTRR */ |
411 | enum DMAC_T_BIT { | 408 | enum DMAC_T_BIT { |
412 | #ifdef CONFIG_CPU_SUBTYPE_SH7763 | 409 | EDTRR_TRNS_GETHER = 0x03, |
413 | EDTRR_TRNS = 0x03, | 410 | EDTRR_TRNS_ETHER = 0x01, |
414 | #else | ||
415 | EDTRR_TRNS = 0x01, | ||
416 | #endif | ||
417 | }; | 411 | }; |
418 | 412 | ||
419 | /* EDRRR*/ | 413 | /* EDRRR*/ |