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authorMallikarjuna R Chilakala <mallikarjuna.chilakala@intel.com>2010-05-13 13:33:41 -0400
committerDavid S. Miller <davem@davemloft.net>2010-05-14 00:07:34 -0400
commit21ce849ba5cc178740c6532ba3dded852296ad91 (patch)
treebbf2070fa966bce5a49485df254cfdb653d30aa6 /drivers/net
parente8171aaad7ec335b8cbd71f56eb08b545f0c404f (diff)
ixgbe: Refactor common code between 82598 & 82599 to accommodate new hardware
Some of the following MAC functions are moved from 82598 & 82599 specific hardware files to common.[ch] to accommodate new silicon changes. Also fixed some white space issues * get_san_mac_addr, check_link, set_vmdq, clear_vmdq, clear_vfta, * set_vfta, fc_enable, init_uta_tables Signed-off-by: Mallikarjuna R Chilakala <mallikarjuna.chilakala@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c8
-rw-r--r--drivers/net/ixgbe/ixgbe_82599.c403
-rw-r--r--drivers/net/ixgbe/ixgbe_common.c518
-rw-r--r--drivers/net/ixgbe/ixgbe_common.h17
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h32
5 files changed, 557 insertions, 421 deletions
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index 35a06b47587b..f2b7ff44215b 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -42,9 +42,9 @@ static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed, 42 ixgbe_link_speed *speed,
43 bool *autoneg); 43 bool *autoneg);
44static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 44static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
45 ixgbe_link_speed speed, 45 ixgbe_link_speed speed,
46 bool autoneg, 46 bool autoneg,
47 bool autoneg_wait_to_complete); 47 bool autoneg_wait_to_complete);
48static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 48static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
49 u8 *eeprom_data); 49 u8 *eeprom_data);
50 50
@@ -1221,7 +1221,7 @@ static struct ixgbe_mac_operations mac_ops_82598 = {
1221 1221
1222static struct ixgbe_eeprom_operations eeprom_ops_82598 = { 1222static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1223 .init_params = &ixgbe_init_eeprom_params_generic, 1223 .init_params = &ixgbe_init_eeprom_params_generic,
1224 .read = &ixgbe_read_eeprom_generic, 1224 .read = &ixgbe_read_eerd_generic,
1225 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 1225 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1226 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 1226 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1227}; 1227};
diff --git a/drivers/net/ixgbe/ixgbe_82599.c b/drivers/net/ixgbe/ixgbe_82599.c
index 38c384031c4c..dc197a4b0676 100644
--- a/drivers/net/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ixgbe/ixgbe_82599.c
@@ -133,27 +133,6 @@ setup_sfp_out:
133 return ret_val; 133 return ret_val;
134} 134}
135 135
136/**
137 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
138 * @hw: pointer to hardware structure
139 *
140 * Read PCIe configuration space, and get the MSI-X vector count from
141 * the capabilities table.
142 **/
143static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
144{
145 struct ixgbe_adapter *adapter = hw->back;
146 u16 msix_count;
147 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
148 &msix_count);
149 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
150
151 /* MSI-X count is zero-based in HW, so increment to give proper value */
152 msix_count++;
153
154 return msix_count;
155}
156
157static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) 136static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
158{ 137{
159 struct ixgbe_mac_info *mac = &hw->mac; 138 struct ixgbe_mac_info *mac = &hw->mac;
@@ -165,7 +144,7 @@ static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
165 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 144 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
166 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 145 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
167 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 146 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
168 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw); 147 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
169 148
170 return 0; 149 return 0;
171} 150}
@@ -735,60 +714,6 @@ out:
735} 714}
736 715
737/** 716/**
738 * ixgbe_check_mac_link_82599 - Determine link and speed status
739 * @hw: pointer to hardware structure
740 * @speed: pointer to link speed
741 * @link_up: true when link is up
742 * @link_up_wait_to_complete: bool used to wait for link up or not
743 *
744 * Reads the links register to determine if link is up and the current speed
745 **/
746static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
747 ixgbe_link_speed *speed,
748 bool *link_up,
749 bool link_up_wait_to_complete)
750{
751 u32 links_reg;
752 u32 i;
753
754 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
755 if (link_up_wait_to_complete) {
756 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
757 if (links_reg & IXGBE_LINKS_UP) {
758 *link_up = true;
759 break;
760 } else {
761 *link_up = false;
762 }
763 msleep(100);
764 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
765 }
766 } else {
767 if (links_reg & IXGBE_LINKS_UP)
768 *link_up = true;
769 else
770 *link_up = false;
771 }
772
773 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
774 IXGBE_LINKS_SPEED_10G_82599)
775 *speed = IXGBE_LINK_SPEED_10GB_FULL;
776 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
777 IXGBE_LINKS_SPEED_1G_82599)
778 *speed = IXGBE_LINK_SPEED_1GB_FULL;
779 else
780 *speed = IXGBE_LINK_SPEED_100_FULL;
781
782 /* if link is down, zero out the current_mode */
783 if (*link_up == false) {
784 hw->fc.current_mode = ixgbe_fc_none;
785 hw->fc.fc_was_autonegged = false;
786 }
787
788 return 0;
789}
790
791/**
792 * ixgbe_setup_mac_link_82599 - Set MAC link speed 717 * ixgbe_setup_mac_link_82599 - Set MAC link speed
793 * @hw: pointer to hardware structure 718 * @hw: pointer to hardware structure
794 * @speed: new link speed 719 * @speed: new link speed
@@ -1050,243 +975,6 @@ reset_hw_out:
1050} 975}
1051 976
1052/** 977/**
1053 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
1054 * @hw: pointer to hardware struct
1055 * @rar: receive address register index to disassociate
1056 * @vmdq: VMDq pool index to remove from the rar
1057 **/
1058static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
1059{
1060 u32 mpsar_lo, mpsar_hi;
1061 u32 rar_entries = hw->mac.num_rar_entries;
1062
1063 if (rar < rar_entries) {
1064 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1065 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1066
1067 if (!mpsar_lo && !mpsar_hi)
1068 goto done;
1069
1070 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
1071 if (mpsar_lo) {
1072 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
1073 mpsar_lo = 0;
1074 }
1075 if (mpsar_hi) {
1076 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
1077 mpsar_hi = 0;
1078 }
1079 } else if (vmdq < 32) {
1080 mpsar_lo &= ~(1 << vmdq);
1081 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
1082 } else {
1083 mpsar_hi &= ~(1 << (vmdq - 32));
1084 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
1085 }
1086
1087 /* was that the last pool using this rar? */
1088 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
1089 hw->mac.ops.clear_rar(hw, rar);
1090 } else {
1091 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1092 }
1093
1094done:
1095 return 0;
1096}
1097
1098/**
1099 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
1100 * @hw: pointer to hardware struct
1101 * @rar: receive address register index to associate with a VMDq index
1102 * @vmdq: VMDq pool index
1103 **/
1104static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
1105{
1106 u32 mpsar;
1107 u32 rar_entries = hw->mac.num_rar_entries;
1108
1109 if (rar < rar_entries) {
1110 if (vmdq < 32) {
1111 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1112 mpsar |= 1 << vmdq;
1113 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
1114 } else {
1115 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1116 mpsar |= 1 << (vmdq - 32);
1117 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
1118 }
1119 } else {
1120 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1121 }
1122 return 0;
1123}
1124
1125/**
1126 * ixgbe_set_vfta_82599 - Set VLAN filter table
1127 * @hw: pointer to hardware structure
1128 * @vlan: VLAN id to write to VLAN filter
1129 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1130 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1131 *
1132 * Turn on/off specified VLAN in the VLAN filter table.
1133 **/
1134static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1135 bool vlan_on)
1136{
1137 u32 regindex;
1138 u32 vlvf_index;
1139 u32 bitindex;
1140 u32 bits;
1141 u32 first_empty_slot;
1142 u32 vt_ctl;
1143
1144 if (vlan > 4095)
1145 return IXGBE_ERR_PARAM;
1146
1147 /*
1148 * this is a 2 part operation - first the VFTA, then the
1149 * VLVF and VLVFB if vind is set
1150 */
1151
1152 /* Part 1
1153 * The VFTA is a bitstring made up of 128 32-bit registers
1154 * that enable the particular VLAN id, much like the MTA:
1155 * bits[11-5]: which register
1156 * bits[4-0]: which bit in the register
1157 */
1158 regindex = (vlan >> 5) & 0x7F;
1159 bitindex = vlan & 0x1F;
1160 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1161 if (vlan_on)
1162 bits |= (1 << bitindex);
1163 else
1164 bits &= ~(1 << bitindex);
1165 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1166
1167
1168 /* Part 2
1169 * If VT mode is set
1170 * Either vlan_on
1171 * make sure the vlan is in VLVF
1172 * set the vind bit in the matching VLVFB
1173 * Or !vlan_on
1174 * clear the pool bit and possibly the vind
1175 */
1176 vt_ctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1177 if (!(vt_ctl & IXGBE_VT_CTL_VT_ENABLE))
1178 goto out;
1179
1180 /* find the vlanid or the first empty slot */
1181 first_empty_slot = 0;
1182
1183 for (vlvf_index = 1; vlvf_index < IXGBE_VLVF_ENTRIES; vlvf_index++) {
1184 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(vlvf_index));
1185 if (!bits && !first_empty_slot)
1186 first_empty_slot = vlvf_index;
1187 else if ((bits & 0x0FFF) == vlan)
1188 break;
1189 }
1190
1191 if (vlvf_index >= IXGBE_VLVF_ENTRIES) {
1192 if (first_empty_slot)
1193 vlvf_index = first_empty_slot;
1194 else {
1195 hw_dbg(hw, "No space in VLVF.\n");
1196 goto out;
1197 }
1198 }
1199
1200 if (vlan_on) {
1201 /* set the pool bit */
1202 if (vind < 32) {
1203 bits = IXGBE_READ_REG(hw,
1204 IXGBE_VLVFB(vlvf_index * 2));
1205 bits |= (1 << vind);
1206 IXGBE_WRITE_REG(hw,
1207 IXGBE_VLVFB(vlvf_index * 2), bits);
1208 } else {
1209 bits = IXGBE_READ_REG(hw,
1210 IXGBE_VLVFB((vlvf_index * 2) + 1));
1211 bits |= (1 << (vind - 32));
1212 IXGBE_WRITE_REG(hw,
1213 IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
1214 }
1215 } else {
1216 /* clear the pool bit */
1217 if (vind < 32) {
1218 bits = IXGBE_READ_REG(hw,
1219 IXGBE_VLVFB(vlvf_index * 2));
1220 bits &= ~(1 << vind);
1221 IXGBE_WRITE_REG(hw,
1222 IXGBE_VLVFB(vlvf_index * 2), bits);
1223 bits |= IXGBE_READ_REG(hw,
1224 IXGBE_VLVFB((vlvf_index * 2) + 1));
1225 } else {
1226 bits = IXGBE_READ_REG(hw,
1227 IXGBE_VLVFB((vlvf_index * 2) + 1));
1228 bits &= ~(1 << (vind - 32));
1229 IXGBE_WRITE_REG(hw,
1230 IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
1231 bits |= IXGBE_READ_REG(hw,
1232 IXGBE_VLVFB(vlvf_index * 2));
1233 }
1234 }
1235
1236 if (bits) {
1237 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
1238 (IXGBE_VLVF_VIEN | vlan));
1239 /* if bits is non-zero then some pools/VFs are still
1240 * using this VLAN ID. Force the VFTA entry to on */
1241 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1242 bits |= (1 << bitindex);
1243 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1244 }
1245 else
1246 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
1247
1248out:
1249 return 0;
1250}
1251
1252/**
1253 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1254 * @hw: pointer to hardware structure
1255 *
1256 * Clears the VLAN filer table, and the VMDq index associated with the filter
1257 **/
1258static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1259{
1260 u32 offset;
1261
1262 for (offset = 0; offset < hw->mac.vft_size; offset++)
1263 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1264
1265 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1266 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1267 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1268 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1269 }
1270
1271 return 0;
1272}
1273
1274/**
1275 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1276 * @hw: pointer to hardware structure
1277 **/
1278static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1279{
1280 int i;
1281 hw_dbg(hw, " Clearing UTA\n");
1282
1283 for (i = 0; i < 128; i++)
1284 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1285
1286 return 0;
1287}
1288
1289/**
1290 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 978 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1291 * @hw: pointer to hardware structure 979 * @hw: pointer to hardware structure
1292 **/ 980 **/
@@ -2550,75 +2238,6 @@ static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
2550} 2238}
2551 2239
2552/** 2240/**
2553 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2554 * @hw: pointer to hardware structure
2555 * @san_mac_offset: SAN MAC address offset
2556 *
2557 * This function will read the EEPROM location for the SAN MAC address
2558 * pointer, and returns the value at that location. This is used in both
2559 * get and set mac_addr routines.
2560 **/
2561static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2562 u16 *san_mac_offset)
2563{
2564 /*
2565 * First read the EEPROM pointer to see if the MAC addresses are
2566 * available.
2567 */
2568 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2569
2570 return 0;
2571}
2572
2573/**
2574 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2575 * @hw: pointer to hardware structure
2576 * @san_mac_addr: SAN MAC address
2577 *
2578 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2579 * per-port, so set_lan_id() must be called before reading the addresses.
2580 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2581 * upon for non-SFP connections, so we must call it here.
2582 **/
2583static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
2584{
2585 u16 san_mac_data, san_mac_offset;
2586 u8 i;
2587
2588 /*
2589 * First read the EEPROM pointer to see if the MAC addresses are
2590 * available. If they're not, no point in calling set_lan_id() here.
2591 */
2592 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2593
2594 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2595 /*
2596 * No addresses available in this EEPROM. It's not an
2597 * error though, so just wipe the local address and return.
2598 */
2599 for (i = 0; i < 6; i++)
2600 san_mac_addr[i] = 0xFF;
2601
2602 goto san_mac_addr_out;
2603 }
2604
2605 /* make sure we know which port we need to program */
2606 hw->mac.ops.set_lan_id(hw);
2607 /* apply the port offset to the address offset */
2608 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2609 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2610 for (i = 0; i < 3; i++) {
2611 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2612 san_mac_addr[i * 2] = (u8)(san_mac_data);
2613 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2614 san_mac_offset++;
2615 }
2616
2617san_mac_addr_out:
2618 return 0;
2619}
2620
2621/**
2622 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 2241 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2623 * @hw: pointer to hardware structure 2242 * @hw: pointer to hardware structure
2624 * 2243 *
@@ -2720,7 +2339,7 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
2720 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599, 2339 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2721 .enable_rx_dma = &ixgbe_enable_rx_dma_82599, 2340 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2722 .get_mac_addr = &ixgbe_get_mac_addr_generic, 2341 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2723 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599, 2342 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2724 .get_device_caps = &ixgbe_get_device_caps_82599, 2343 .get_device_caps = &ixgbe_get_device_caps_82599,
2725 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599, 2344 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599,
2726 .stop_adapter = &ixgbe_stop_adapter_generic, 2345 .stop_adapter = &ixgbe_stop_adapter_generic,
@@ -2729,7 +2348,7 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
2729 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, 2348 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2730 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, 2349 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2731 .setup_link = &ixgbe_setup_mac_link_82599, 2350 .setup_link = &ixgbe_setup_mac_link_82599,
2732 .check_link = &ixgbe_check_mac_link_82599, 2351 .check_link = &ixgbe_check_mac_link_generic,
2733 .get_link_capabilities = &ixgbe_get_link_capabilities_82599, 2352 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2734 .led_on = &ixgbe_led_on_generic, 2353 .led_on = &ixgbe_led_on_generic,
2735 .led_off = &ixgbe_led_off_generic, 2354 .led_off = &ixgbe_led_off_generic,
@@ -2737,23 +2356,23 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
2737 .blink_led_stop = &ixgbe_blink_led_stop_generic, 2356 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2738 .set_rar = &ixgbe_set_rar_generic, 2357 .set_rar = &ixgbe_set_rar_generic,
2739 .clear_rar = &ixgbe_clear_rar_generic, 2358 .clear_rar = &ixgbe_clear_rar_generic,
2740 .set_vmdq = &ixgbe_set_vmdq_82599, 2359 .set_vmdq = &ixgbe_set_vmdq_generic,
2741 .clear_vmdq = &ixgbe_clear_vmdq_82599, 2360 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2742 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 2361 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2743 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic, 2362 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2744 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 2363 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2745 .enable_mc = &ixgbe_enable_mc_generic, 2364 .enable_mc = &ixgbe_enable_mc_generic,
2746 .disable_mc = &ixgbe_disable_mc_generic, 2365 .disable_mc = &ixgbe_disable_mc_generic,
2747 .clear_vfta = &ixgbe_clear_vfta_82599, 2366 .clear_vfta = &ixgbe_clear_vfta_generic,
2748 .set_vfta = &ixgbe_set_vfta_82599, 2367 .set_vfta = &ixgbe_set_vfta_generic,
2749 .fc_enable = &ixgbe_fc_enable_generic, 2368 .fc_enable = &ixgbe_fc_enable_generic,
2750 .init_uta_tables = &ixgbe_init_uta_tables_82599, 2369 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2751 .setup_sfp = &ixgbe_setup_sfp_modules_82599, 2370 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2752}; 2371};
2753 2372
2754static struct ixgbe_eeprom_operations eeprom_ops_82599 = { 2373static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2755 .init_params = &ixgbe_init_eeprom_params_generic, 2374 .init_params = &ixgbe_init_eeprom_params_generic,
2756 .read = &ixgbe_read_eeprom_generic, 2375 .read = &ixgbe_read_eerd_generic,
2757 .write = &ixgbe_write_eeprom_generic, 2376 .write = &ixgbe_write_eeprom_generic,
2758 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 2377 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2759 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 2378 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
@@ -2762,7 +2381,7 @@ static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2762static struct ixgbe_phy_operations phy_ops_82599 = { 2381static struct ixgbe_phy_operations phy_ops_82599 = {
2763 .identify = &ixgbe_identify_phy_82599, 2382 .identify = &ixgbe_identify_phy_82599,
2764 .identify_sfp = &ixgbe_identify_sfp_module_generic, 2383 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2765 .init = &ixgbe_init_phy_ops_82599, 2384 .init = &ixgbe_init_phy_ops_82599,
2766 .reset = &ixgbe_reset_phy_generic, 2385 .reset = &ixgbe_reset_phy_generic,
2767 .read_reg = &ixgbe_read_phy_reg_generic, 2386 .read_reg = &ixgbe_read_phy_reg_generic,
2768 .write_reg = &ixgbe_write_phy_reg_generic, 2387 .write_reg = &ixgbe_write_phy_reg_generic,
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c
index 753f2ab39d7f..1159d9138f05 100644
--- a/drivers/net/ixgbe/ixgbe_common.c
+++ b/drivers/net/ixgbe/ixgbe_common.c
@@ -34,7 +34,6 @@
34#include "ixgbe_common.h" 34#include "ixgbe_common.h"
35#include "ixgbe_phy.h" 35#include "ixgbe_phy.h"
36 36
37static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
38static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 37static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
39static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 38static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 39static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
@@ -595,14 +594,14 @@ out:
595} 594}
596 595
597/** 596/**
598 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD 597 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
599 * @hw: pointer to hardware structure 598 * @hw: pointer to hardware structure
600 * @offset: offset of word in the EEPROM to read 599 * @offset: offset of word in the EEPROM to read
601 * @data: word read from the EEPROM 600 * @data: word read from the EEPROM
602 * 601 *
603 * Reads a 16 bit word from the EEPROM using the EERD register. 602 * Reads a 16 bit word from the EEPROM using the EERD register.
604 **/ 603 **/
605s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 604s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
606{ 605{
607 u32 eerd; 606 u32 eerd;
608 s32 status; 607 s32 status;
@@ -614,15 +613,15 @@ s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
614 goto out; 613 goto out;
615 } 614 }
616 615
617 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + 616 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) +
618 IXGBE_EEPROM_READ_REG_START; 617 IXGBE_EEPROM_RW_REG_START;
619 618
620 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 619 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
621 status = ixgbe_poll_eeprom_eerd_done(hw); 620 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
622 621
623 if (status == 0) 622 if (status == 0)
624 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 623 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
625 IXGBE_EEPROM_READ_REG_DATA); 624 IXGBE_EEPROM_RW_REG_DATA);
626 else 625 else
627 hw_dbg(hw, "Eeprom read timed out\n"); 626 hw_dbg(hw, "Eeprom read timed out\n");
628 627
@@ -631,20 +630,26 @@ out:
631} 630}
632 631
633/** 632/**
634 * ixgbe_poll_eeprom_eerd_done - Poll EERD status 633 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
635 * @hw: pointer to hardware structure 634 * @hw: pointer to hardware structure
635 * @ee_reg: EEPROM flag for polling
636 * 636 *
637 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 637 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
638 * read or write is done respectively.
638 **/ 639 **/
639static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) 640s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
640{ 641{
641 u32 i; 642 u32 i;
642 u32 reg; 643 u32 reg;
643 s32 status = IXGBE_ERR_EEPROM; 644 s32 status = IXGBE_ERR_EEPROM;
644 645
645 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) { 646 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
646 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 647 if (ee_reg == IXGBE_NVM_POLL_READ)
647 if (reg & IXGBE_EEPROM_READ_REG_DONE) { 648 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
649 else
650 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
651
652 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
648 status = 0; 653 status = 0;
649 break; 654 break;
650 } 655 }
@@ -2255,3 +2260,490 @@ s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2255 2260
2256 return 0; 2261 return 0;
2257} 2262}
2263
2264/**
2265 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2266 * @hw: pointer to hardware structure
2267 * @san_mac_offset: SAN MAC address offset
2268 *
2269 * This function will read the EEPROM location for the SAN MAC address
2270 * pointer, and returns the value at that location. This is used in both
2271 * get and set mac_addr routines.
2272 **/
2273static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2274 u16 *san_mac_offset)
2275{
2276 /*
2277 * First read the EEPROM pointer to see if the MAC addresses are
2278 * available.
2279 */
2280 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2281
2282 return 0;
2283}
2284
2285/**
2286 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2287 * @hw: pointer to hardware structure
2288 * @san_mac_addr: SAN MAC address
2289 *
2290 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2291 * per-port, so set_lan_id() must be called before reading the addresses.
2292 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2293 * upon for non-SFP connections, so we must call it here.
2294 **/
2295s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2296{
2297 u16 san_mac_data, san_mac_offset;
2298 u8 i;
2299
2300 /*
2301 * First read the EEPROM pointer to see if the MAC addresses are
2302 * available. If they're not, no point in calling set_lan_id() here.
2303 */
2304 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2305
2306 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2307 /*
2308 * No addresses available in this EEPROM. It's not an
2309 * error though, so just wipe the local address and return.
2310 */
2311 for (i = 0; i < 6; i++)
2312 san_mac_addr[i] = 0xFF;
2313
2314 goto san_mac_addr_out;
2315 }
2316
2317 /* make sure we know which port we need to program */
2318 hw->mac.ops.set_lan_id(hw);
2319 /* apply the port offset to the address offset */
2320 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2321 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2322 for (i = 0; i < 3; i++) {
2323 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2324 san_mac_addr[i * 2] = (u8)(san_mac_data);
2325 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2326 san_mac_offset++;
2327 }
2328
2329san_mac_addr_out:
2330 return 0;
2331}
2332
2333/**
2334 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2335 * @hw: pointer to hardware structure
2336 *
2337 * Read PCIe configuration space, and get the MSI-X vector count from
2338 * the capabilities table.
2339 **/
2340u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2341{
2342 struct ixgbe_adapter *adapter = hw->back;
2343 u16 msix_count;
2344 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
2345 &msix_count);
2346 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2347
2348 /* MSI-X count is zero-based in HW, so increment to give proper value */
2349 msix_count++;
2350
2351 return msix_count;
2352}
2353
2354/**
2355 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2356 * @hw: pointer to hardware struct
2357 * @rar: receive address register index to disassociate
2358 * @vmdq: VMDq pool index to remove from the rar
2359 **/
2360s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2361{
2362 u32 mpsar_lo, mpsar_hi;
2363 u32 rar_entries = hw->mac.num_rar_entries;
2364
2365 if (rar < rar_entries) {
2366 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2367 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2368
2369 if (!mpsar_lo && !mpsar_hi)
2370 goto done;
2371
2372 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2373 if (mpsar_lo) {
2374 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2375 mpsar_lo = 0;
2376 }
2377 if (mpsar_hi) {
2378 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2379 mpsar_hi = 0;
2380 }
2381 } else if (vmdq < 32) {
2382 mpsar_lo &= ~(1 << vmdq);
2383 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2384 } else {
2385 mpsar_hi &= ~(1 << (vmdq - 32));
2386 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2387 }
2388
2389 /* was that the last pool using this rar? */
2390 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2391 hw->mac.ops.clear_rar(hw, rar);
2392 } else {
2393 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2394 }
2395
2396done:
2397 return 0;
2398}
2399
2400/**
2401 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2402 * @hw: pointer to hardware struct
2403 * @rar: receive address register index to associate with a VMDq index
2404 * @vmdq: VMDq pool index
2405 **/
2406s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2407{
2408 u32 mpsar;
2409 u32 rar_entries = hw->mac.num_rar_entries;
2410
2411 if (rar < rar_entries) {
2412 if (vmdq < 32) {
2413 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2414 mpsar |= 1 << vmdq;
2415 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2416 } else {
2417 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2418 mpsar |= 1 << (vmdq - 32);
2419 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2420 }
2421 } else {
2422 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2423 }
2424 return 0;
2425}
2426
2427/**
2428 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2429 * @hw: pointer to hardware structure
2430 **/
2431s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2432{
2433 int i;
2434
2435
2436 for (i = 0; i < 128; i++)
2437 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2438
2439 return 0;
2440}
2441
2442/**
2443 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2444 * @hw: pointer to hardware structure
2445 * @vlan: VLAN id to write to VLAN filter
2446 *
2447 * return the VLVF index where this VLAN id should be placed
2448 *
2449 **/
2450s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
2451{
2452 u32 bits = 0;
2453 u32 first_empty_slot = 0;
2454 s32 regindex;
2455
2456 /* short cut the special case */
2457 if (vlan == 0)
2458 return 0;
2459
2460 /*
2461 * Search for the vlan id in the VLVF entries. Save off the first empty
2462 * slot found along the way
2463 */
2464 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2465 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2466 if (!bits && !(first_empty_slot))
2467 first_empty_slot = regindex;
2468 else if ((bits & 0x0FFF) == vlan)
2469 break;
2470 }
2471
2472 /*
2473 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2474 * in the VLVF. Else use the first empty VLVF register for this
2475 * vlan id.
2476 */
2477 if (regindex >= IXGBE_VLVF_ENTRIES) {
2478 if (first_empty_slot)
2479 regindex = first_empty_slot;
2480 else {
2481 hw_dbg(hw, "No space in VLVF.\n");
2482 regindex = IXGBE_ERR_NO_SPACE;
2483 }
2484 }
2485
2486 return regindex;
2487}
2488
2489/**
2490 * ixgbe_set_vfta_generic - Set VLAN filter table
2491 * @hw: pointer to hardware structure
2492 * @vlan: VLAN id to write to VLAN filter
2493 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2494 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2495 *
2496 * Turn on/off specified VLAN in the VLAN filter table.
2497 **/
2498s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2499 bool vlan_on)
2500{
2501 s32 regindex;
2502 u32 bitindex;
2503 u32 vfta;
2504 u32 bits;
2505 u32 vt;
2506 u32 targetbit;
2507 bool vfta_changed = false;
2508
2509 if (vlan > 4095)
2510 return IXGBE_ERR_PARAM;
2511
2512 /*
2513 * this is a 2 part operation - first the VFTA, then the
2514 * VLVF and VLVFB if VT Mode is set
2515 * We don't write the VFTA until we know the VLVF part succeeded.
2516 */
2517
2518 /* Part 1
2519 * The VFTA is a bitstring made up of 128 32-bit registers
2520 * that enable the particular VLAN id, much like the MTA:
2521 * bits[11-5]: which register
2522 * bits[4-0]: which bit in the register
2523 */
2524 regindex = (vlan >> 5) & 0x7F;
2525 bitindex = vlan & 0x1F;
2526 targetbit = (1 << bitindex);
2527 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2528
2529 if (vlan_on) {
2530 if (!(vfta & targetbit)) {
2531 vfta |= targetbit;
2532 vfta_changed = true;
2533 }
2534 } else {
2535 if ((vfta & targetbit)) {
2536 vfta &= ~targetbit;
2537 vfta_changed = true;
2538 }
2539 }
2540
2541 /* Part 2
2542 * If VT Mode is set
2543 * Either vlan_on
2544 * make sure the vlan is in VLVF
2545 * set the vind bit in the matching VLVFB
2546 * Or !vlan_on
2547 * clear the pool bit and possibly the vind
2548 */
2549 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2550 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
2551 s32 vlvf_index;
2552
2553 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
2554 if (vlvf_index < 0)
2555 return vlvf_index;
2556
2557 if (vlan_on) {
2558 /* set the pool bit */
2559 if (vind < 32) {
2560 bits = IXGBE_READ_REG(hw,
2561 IXGBE_VLVFB(vlvf_index*2));
2562 bits |= (1 << vind);
2563 IXGBE_WRITE_REG(hw,
2564 IXGBE_VLVFB(vlvf_index*2),
2565 bits);
2566 } else {
2567 bits = IXGBE_READ_REG(hw,
2568 IXGBE_VLVFB((vlvf_index*2)+1));
2569 bits |= (1 << (vind-32));
2570 IXGBE_WRITE_REG(hw,
2571 IXGBE_VLVFB((vlvf_index*2)+1),
2572 bits);
2573 }
2574 } else {
2575 /* clear the pool bit */
2576 if (vind < 32) {
2577 bits = IXGBE_READ_REG(hw,
2578 IXGBE_VLVFB(vlvf_index*2));
2579 bits &= ~(1 << vind);
2580 IXGBE_WRITE_REG(hw,
2581 IXGBE_VLVFB(vlvf_index*2),
2582 bits);
2583 bits |= IXGBE_READ_REG(hw,
2584 IXGBE_VLVFB((vlvf_index*2)+1));
2585 } else {
2586 bits = IXGBE_READ_REG(hw,
2587 IXGBE_VLVFB((vlvf_index*2)+1));
2588 bits &= ~(1 << (vind-32));
2589 IXGBE_WRITE_REG(hw,
2590 IXGBE_VLVFB((vlvf_index*2)+1),
2591 bits);
2592 bits |= IXGBE_READ_REG(hw,
2593 IXGBE_VLVFB(vlvf_index*2));
2594 }
2595 }
2596
2597 /*
2598 * If there are still bits set in the VLVFB registers
2599 * for the VLAN ID indicated we need to see if the
2600 * caller is requesting that we clear the VFTA entry bit.
2601 * If the caller has requested that we clear the VFTA
2602 * entry bit but there are still pools/VFs using this VLAN
2603 * ID entry then ignore the request. We're not worried
2604 * about the case where we're turning the VFTA VLAN ID
2605 * entry bit on, only when requested to turn it off as
2606 * there may be multiple pools and/or VFs using the
2607 * VLAN ID entry. In that case we cannot clear the
2608 * VFTA bit until all pools/VFs using that VLAN ID have also
2609 * been cleared. This will be indicated by "bits" being
2610 * zero.
2611 */
2612 if (bits) {
2613 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
2614 (IXGBE_VLVF_VIEN | vlan));
2615 if (!vlan_on) {
2616 /* someone wants to clear the vfta entry
2617 * but some pools/VFs are still using it.
2618 * Ignore it. */
2619 vfta_changed = false;
2620 }
2621 }
2622 else
2623 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
2624 }
2625
2626 if (vfta_changed)
2627 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
2628
2629 return 0;
2630}
2631
2632/**
2633 * ixgbe_clear_vfta_generic - Clear VLAN filter table
2634 * @hw: pointer to hardware structure
2635 *
2636 * Clears the VLAN filer table, and the VMDq index associated with the filter
2637 **/
2638s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
2639{
2640 u32 offset;
2641
2642 for (offset = 0; offset < hw->mac.vft_size; offset++)
2643 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
2644
2645 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
2646 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
2647 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
2648 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
2649 }
2650
2651 return 0;
2652}
2653
2654/**
2655 * ixgbe_check_mac_link_generic - Determine link and speed status
2656 * @hw: pointer to hardware structure
2657 * @speed: pointer to link speed
2658 * @link_up: true when link is up
2659 * @link_up_wait_to_complete: bool used to wait for link up or not
2660 *
2661 * Reads the links register to determine if link is up and the current speed
2662 **/
2663s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2664 bool *link_up, bool link_up_wait_to_complete)
2665{
2666 u32 links_reg;
2667 u32 i;
2668
2669 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2670 if (link_up_wait_to_complete) {
2671 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
2672 if (links_reg & IXGBE_LINKS_UP) {
2673 *link_up = true;
2674 break;
2675 } else {
2676 *link_up = false;
2677 }
2678 msleep(100);
2679 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2680 }
2681 } else {
2682 if (links_reg & IXGBE_LINKS_UP)
2683 *link_up = true;
2684 else
2685 *link_up = false;
2686 }
2687
2688 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2689 IXGBE_LINKS_SPEED_10G_82599)
2690 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2691 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2692 IXGBE_LINKS_SPEED_1G_82599)
2693 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2694 else
2695 *speed = IXGBE_LINK_SPEED_100_FULL;
2696
2697 /* if link is down, zero out the current_mode */
2698 if (*link_up == false) {
2699 hw->fc.current_mode = ixgbe_fc_none;
2700 hw->fc.fc_was_autonegged = false;
2701 }
2702
2703 return 0;
2704}
2705
2706/**
2707 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
2708 * the EEPROM
2709 * @hw: pointer to hardware structure
2710 * @wwnn_prefix: the alternative WWNN prefix
2711 * @wwpn_prefix: the alternative WWPN prefix
2712 *
2713 * This function will read the EEPROM from the alternative SAN MAC address
2714 * block to check the support for the alternative WWNN/WWPN prefix support.
2715 **/
2716s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2717 u16 *wwpn_prefix)
2718{
2719 u16 offset, caps;
2720 u16 alt_san_mac_blk_offset;
2721
2722 /* clear output first */
2723 *wwnn_prefix = 0xFFFF;
2724 *wwpn_prefix = 0xFFFF;
2725
2726 /* check if alternative SAN MAC is supported */
2727 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2728 &alt_san_mac_blk_offset);
2729
2730 if ((alt_san_mac_blk_offset == 0) ||
2731 (alt_san_mac_blk_offset == 0xFFFF))
2732 goto wwn_prefix_out;
2733
2734 /* check capability in alternative san mac address block */
2735 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2736 hw->eeprom.ops.read(hw, offset, &caps);
2737 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2738 goto wwn_prefix_out;
2739
2740 /* get the corresponding prefix for WWNN/WWPN */
2741 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2742 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2743
2744 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2745 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2746
2747wwn_prefix_out:
2748 return 0;
2749}
diff --git a/drivers/net/ixgbe/ixgbe_common.h b/drivers/net/ixgbe/ixgbe_common.h
index 264eef575cd6..3080afb12bdf 100644
--- a/drivers/net/ixgbe/ixgbe_common.h
+++ b/drivers/net/ixgbe/ixgbe_common.h
@@ -30,6 +30,7 @@
30 30
31#include "ixgbe_type.h" 31#include "ixgbe_type.h"
32 32
33u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
33s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw); 34s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
34s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw); 35s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
35s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw); 36s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
@@ -45,12 +46,13 @@ s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
45 46
46s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw); 47s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
47s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data); 48s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
48s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data); 49s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
49s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 50s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
50 u16 *data); 51 u16 *data);
51s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 52s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
52 u16 *checksum_val); 53 u16 *checksum_val);
53s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw); 54s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
55s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
54 56
55s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 57s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
56 u32 enable_addr); 58 u32 enable_addr);
@@ -70,9 +72,16 @@ s32 ixgbe_validate_mac_addr(u8 *mac_addr);
70s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask); 72s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
71void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask); 73void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
72s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); 74s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
73 75s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
74s32 ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 *val); 76s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
75s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val); 77s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
78s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
79s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
80 u32 vind, bool vlan_on);
81s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
82s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
83 ixgbe_link_speed *speed,
84 bool *link_up, bool link_up_wait_to_complete);
76 85
77s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index); 86s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
78s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index); 87s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index 8fc59ac3c0e8..bd69196ff522 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -73,6 +73,7 @@
73/* NVM Registers */ 73/* NVM Registers */
74#define IXGBE_EEC 0x10010 74#define IXGBE_EEC 0x10010
75#define IXGBE_EERD 0x10014 75#define IXGBE_EERD 0x10014
76#define IXGBE_EEWR 0x10018
76#define IXGBE_FLA 0x1001C 77#define IXGBE_FLA 0x1001C
77#define IXGBE_EEMNGCTL 0x10110 78#define IXGBE_EEMNGCTL 0x10110
78#define IXGBE_EEMNGDATA 0x10114 79#define IXGBE_EEMNGDATA 0x10114
@@ -699,6 +700,7 @@
699#define IXGBE_MREVID 0x11064 700#define IXGBE_MREVID 0x11064
700#define IXGBE_DCA_ID 0x11070 701#define IXGBE_DCA_ID 0x11070
701#define IXGBE_DCA_CTRL 0x11074 702#define IXGBE_DCA_CTRL 0x11074
703#define IXGBE_SWFW_SYNC IXGBE_GSSR
702 704
703/* PCIe registers 82599-specific */ 705/* PCIe registers 82599-specific */
704#define IXGBE_GCR_EXT 0x11050 706#define IXGBE_GCR_EXT 0x11050
@@ -1463,8 +1465,9 @@
1463#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 1465#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1464#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 1466#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1465#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 1467#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1468#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
1466 1469
1467/* GSSR definitions */ 1470/* SW_FW_SYNC/GSSR definitions */
1468#define IXGBE_GSSR_EEP_SM 0x0001 1471#define IXGBE_GSSR_EEP_SM 0x0001
1469#define IXGBE_GSSR_PHY0_SM 0x0002 1472#define IXGBE_GSSR_PHY0_SM 0x0002
1470#define IXGBE_GSSR_PHY1_SM 0x0004 1473#define IXGBE_GSSR_PHY1_SM 0x0004
@@ -1484,6 +1487,8 @@
1484#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 1487#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
1485#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 1488#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
1486#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 1489#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
1490#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */
1491#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */
1487/* EEPROM Addressing bits based on type (0-small, 1-large) */ 1492/* EEPROM Addressing bits based on type (0-small, 1-large) */
1488#define IXGBE_EEC_ADDR_SIZE 0x00000400 1493#define IXGBE_EEC_ADDR_SIZE 0x00000400
1489#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 1494#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
@@ -1539,10 +1544,12 @@
1539#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 1544#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1540 1545
1541/* EEPROM Read Register */ 1546/* EEPROM Read Register */
1542#define IXGBE_EEPROM_READ_REG_DATA 16 /* data offset in EEPROM read reg */ 1547#define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */
1543#define IXGBE_EEPROM_READ_REG_DONE 2 /* Offset to READ done bit */ 1548#define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */
1544#define IXGBE_EEPROM_READ_REG_START 1 /* First bit to start operation */ 1549#define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */
1545#define IXGBE_EEPROM_READ_ADDR_SHIFT 2 /* Shift to the address bits */ 1550#define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1551#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1552#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */
1546 1553
1547#define IXGBE_ETH_LENGTH_OF_ADDRESS 6 1554#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
1548 1555
@@ -1550,9 +1557,15 @@
1550#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1557#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1551#endif 1558#endif
1552 1559
1553#ifndef IXGBE_EERD_ATTEMPTS 1560#ifndef IXGBE_EERD_EEWR_ATTEMPTS
1554/* Number of 5 microseconds we wait for EERD read to complete */ 1561/* Number of 5 microseconds we wait for EERD read and
1555#define IXGBE_EERD_ATTEMPTS 100000 1562 * EERW write to complete */
1563#define IXGBE_EERD_EEWR_ATTEMPTS 100000
1564#endif
1565
1566#ifndef IXGBE_FLUDONE_ATTEMPTS
1567/* # attempts we wait for flush update to complete */
1568#define IXGBE_FLUDONE_ATTEMPTS 20000
1556#endif 1569#endif
1557 1570
1558#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 1571#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
@@ -2476,6 +2489,7 @@ struct ixgbe_mac_info {
2476 u32 mcft_size; 2489 u32 mcft_size;
2477 u32 vft_size; 2490 u32 vft_size;
2478 u32 num_rar_entries; 2491 u32 num_rar_entries;
2492 u32 rar_highwater;
2479 u32 max_tx_queues; 2493 u32 max_tx_queues;
2480 u32 max_rx_queues; 2494 u32 max_rx_queues;
2481 u32 max_msix_vectors; 2495 u32 max_msix_vectors;
@@ -2582,8 +2596,10 @@ struct ixgbe_info {
2582#define IXGBE_ERR_SFP_NOT_SUPPORTED -19 2596#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
2583#define IXGBE_ERR_SFP_NOT_PRESENT -20 2597#define IXGBE_ERR_SFP_NOT_PRESENT -20
2584#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 2598#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
2599#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
2585#define IXGBE_ERR_FDIR_REINIT_FAILED -23 2600#define IXGBE_ERR_FDIR_REINIT_FAILED -23
2586#define IXGBE_ERR_EEPROM_VERSION -24 2601#define IXGBE_ERR_EEPROM_VERSION -24
2602#define IXGBE_ERR_NO_SPACE -25
2587#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 2603#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
2588 2604
2589#endif /* _IXGBE_TYPE_H_ */ 2605#endif /* _IXGBE_TYPE_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 23:50:08 -0500