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authorAl Viro <viro@zeniv.linux.org.uk>2007-08-23 02:29:45 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-10 19:52:02 -0400
commit88b1943bd3e4d2620e5936181861e00bf6236aa4 (patch)
treedcdb8c0e72259aad81a43f4619feee1cb69d814a /drivers/net
parent37e1370b701b9a032399e8e2d130009eefa66782 (diff)
starfire: trivial endianness annotations
Note: we still have several fishy areas - mcast filter and vlan handling. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/starfire.c88
1 files changed, 44 insertions, 44 deletions
diff --git a/drivers/net/starfire.c b/drivers/net/starfire.c
index ea253754763a..bcc430bd9e49 100644
--- a/drivers/net/starfire.c
+++ b/drivers/net/starfire.c
@@ -155,7 +155,7 @@ static int full_duplex[MAX_UNITS] = {0, };
155#if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__alpha__) || defined(__mips64__) || (defined(__mips__) && defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) 155#if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__alpha__) || defined(__mips64__) || (defined(__mips__) && defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR))
156/* 64-bit dma_addr_t */ 156/* 64-bit dma_addr_t */
157#define ADDR_64BITS /* This chip uses 64 bit addresses. */ 157#define ADDR_64BITS /* This chip uses 64 bit addresses. */
158#define netdrv_addr_t u64 158#define netdrv_addr_t __le64
159#define cpu_to_dma(x) cpu_to_le64(x) 159#define cpu_to_dma(x) cpu_to_le64(x)
160#define dma_to_cpu(x) le64_to_cpu(x) 160#define dma_to_cpu(x) le64_to_cpu(x)
161#define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit 161#define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
@@ -164,7 +164,7 @@ static int full_duplex[MAX_UNITS] = {0, };
164#define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit 164#define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
165#define RX_DESC_ADDR_SIZE RxDescAddr64bit 165#define RX_DESC_ADDR_SIZE RxDescAddr64bit
166#else /* 32-bit dma_addr_t */ 166#else /* 32-bit dma_addr_t */
167#define netdrv_addr_t u32 167#define netdrv_addr_t __le32
168#define cpu_to_dma(x) cpu_to_le32(x) 168#define cpu_to_dma(x) cpu_to_le32(x)
169#define dma_to_cpu(x) le32_to_cpu(x) 169#define dma_to_cpu(x) le32_to_cpu(x)
170#define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit 170#define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
@@ -494,7 +494,7 @@ enum intr_ctrl_bits {
494 494
495/* The Rx and Tx buffer descriptors. */ 495/* The Rx and Tx buffer descriptors. */
496struct starfire_rx_desc { 496struct starfire_rx_desc {
497 dma_addr_t rxaddr; 497 netdrv_addr_t rxaddr;
498}; 498};
499enum rx_desc_bits { 499enum rx_desc_bits {
500 RxDescValid=1, RxDescEndRing=2, 500 RxDescValid=1, RxDescEndRing=2,
@@ -502,25 +502,25 @@ enum rx_desc_bits {
502 502
503/* Completion queue entry. */ 503/* Completion queue entry. */
504struct short_rx_done_desc { 504struct short_rx_done_desc {
505 u32 status; /* Low 16 bits is length. */ 505 __le32 status; /* Low 16 bits is length. */
506}; 506};
507struct basic_rx_done_desc { 507struct basic_rx_done_desc {
508 u32 status; /* Low 16 bits is length. */ 508 __le32 status; /* Low 16 bits is length. */
509 u16 vlanid; 509 __le16 vlanid;
510 u16 status2; 510 __le16 status2;
511}; 511};
512struct csum_rx_done_desc { 512struct csum_rx_done_desc {
513 u32 status; /* Low 16 bits is length. */ 513 __le32 status; /* Low 16 bits is length. */
514 u16 csum; /* Partial checksum */ 514 __le16 csum; /* Partial checksum */
515 u16 status2; 515 __le16 status2;
516}; 516};
517struct full_rx_done_desc { 517struct full_rx_done_desc {
518 u32 status; /* Low 16 bits is length. */ 518 __le32 status; /* Low 16 bits is length. */
519 u16 status3; 519 __le16 status3;
520 u16 status2; 520 __le16 status2;
521 u16 vlanid; 521 __le16 vlanid;
522 u16 csum; /* partial checksum */ 522 __le16 csum; /* partial checksum */
523 u32 timestamp; 523 __le32 timestamp;
524}; 524};
525/* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */ 525/* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
526#ifdef VLAN_SUPPORT 526#ifdef VLAN_SUPPORT
@@ -537,15 +537,15 @@ enum rx_done_bits {
537 537
538/* Type 1 Tx descriptor. */ 538/* Type 1 Tx descriptor. */
539struct starfire_tx_desc_1 { 539struct starfire_tx_desc_1 {
540 u32 status; /* Upper bits are status, lower 16 length. */ 540 __le32 status; /* Upper bits are status, lower 16 length. */
541 u32 addr; 541 __le32 addr;
542}; 542};
543 543
544/* Type 2 Tx descriptor. */ 544/* Type 2 Tx descriptor. */
545struct starfire_tx_desc_2 { 545struct starfire_tx_desc_2 {
546 u32 status; /* Upper bits are status, lower 16 length. */ 546 __le32 status; /* Upper bits are status, lower 16 length. */
547 u32 reserved; 547 __le32 reserved;
548 u64 addr; 548 __le64 addr;
549}; 549};
550 550
551#ifdef ADDR_64BITS 551#ifdef ADDR_64BITS
@@ -563,9 +563,9 @@ enum tx_desc_bits {
563 TxRingWrap=0x04000000, TxCalTCP=0x02000000, 563 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
564}; 564};
565struct tx_done_desc { 565struct tx_done_desc {
566 u32 status; /* timestamp, index. */ 566 __le32 status; /* timestamp, index. */
567#if 0 567#if 0
568 u32 intrstatus; /* interrupt status */ 568 __le32 intrstatus; /* interrupt status */
569#endif 569#endif
570}; 570};
571 571
@@ -963,7 +963,7 @@ static int netdev_open(struct net_device *dev)
963 dev->name, dev->irq); 963 dev->name, dev->irq);
964 964
965 /* Allocate the various queues. */ 965 /* Allocate the various queues. */
966 if (np->queue_mem == 0) { 966 if (!np->queue_mem) {
967 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; 967 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
968 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; 968 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
969 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; 969 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
@@ -1036,11 +1036,11 @@ static int netdev_open(struct net_device *dev)
1036 writew(0, ioaddr + PerfFilterTable + 4); 1036 writew(0, ioaddr + PerfFilterTable + 4);
1037 writew(0, ioaddr + PerfFilterTable + 8); 1037 writew(0, ioaddr + PerfFilterTable + 8);
1038 for (i = 1; i < 16; i++) { 1038 for (i = 1; i < 16; i++) {
1039 u16 *eaddrs = (u16 *)dev->dev_addr; 1039 __be16 *eaddrs = (__be16 *)dev->dev_addr;
1040 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16; 1040 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
1041 writew(cpu_to_be16(eaddrs[2]), setup_frm); setup_frm += 4; 1041 writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4;
1042 writew(cpu_to_be16(eaddrs[1]), setup_frm); setup_frm += 4; 1042 writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4;
1043 writew(cpu_to_be16(eaddrs[0]), setup_frm); setup_frm += 8; 1043 writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8;
1044 } 1044 }
1045 1045
1046 /* Initialize other registers. */ 1046 /* Initialize other registers. */
@@ -1767,26 +1767,26 @@ static void set_rx_mode(struct net_device *dev)
1767 } else if (dev->mc_count <= 14) { 1767 } else if (dev->mc_count <= 14) {
1768 /* Use the 16 element perfect filter, skip first two entries. */ 1768 /* Use the 16 element perfect filter, skip first two entries. */
1769 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16; 1769 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1770 u16 *eaddrs; 1770 __be16 *eaddrs;
1771 for (i = 2, mclist = dev->mc_list; mclist && i < dev->mc_count + 2; 1771 for (i = 2, mclist = dev->mc_list; mclist && i < dev->mc_count + 2;
1772 i++, mclist = mclist->next) { 1772 i++, mclist = mclist->next) {
1773 eaddrs = (u16 *)mclist->dmi_addr; 1773 eaddrs = (__be16 *)mclist->dmi_addr;
1774 writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 4; 1774 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4;
1775 writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4; 1775 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1776 writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 8; 1776 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8;
1777 } 1777 }
1778 eaddrs = (u16 *)dev->dev_addr; 1778 eaddrs = (__be16 *)dev->dev_addr;
1779 while (i++ < 16) { 1779 while (i++ < 16) {
1780 writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 4; 1780 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1781 writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4; 1781 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1782 writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 8; 1782 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1783 } 1783 }
1784 rx_mode |= AcceptBroadcast|PerfectFilter; 1784 rx_mode |= AcceptBroadcast|PerfectFilter;
1785 } else { 1785 } else {
1786 /* Must use a multicast hash table. */ 1786 /* Must use a multicast hash table. */
1787 void __iomem *filter_addr; 1787 void __iomem *filter_addr;
1788 u16 *eaddrs; 1788 __be16 *eaddrs;
1789 u16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */ 1789 __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
1790 1790
1791 memset(mc_filter, 0, sizeof(mc_filter)); 1791 memset(mc_filter, 0, sizeof(mc_filter));
1792 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; 1792 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
@@ -1794,17 +1794,17 @@ static void set_rx_mode(struct net_device *dev)
1794 /* The chip uses the upper 9 CRC bits 1794 /* The chip uses the upper 9 CRC bits
1795 as index into the hash table */ 1795 as index into the hash table */
1796 int bit_nr = ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 23; 1796 int bit_nr = ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 23;
1797 __u32 *fptr = (__u32 *) &mc_filter[(bit_nr >> 4) & ~1]; 1797 __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1];
1798 1798
1799 *fptr |= cpu_to_le32(1 << (bit_nr & 31)); 1799 *fptr |= cpu_to_le32(1 << (bit_nr & 31));
1800 } 1800 }
1801 /* Clear the perfect filter list, skip first two entries. */ 1801 /* Clear the perfect filter list, skip first two entries. */
1802 filter_addr = ioaddr + PerfFilterTable + 2 * 16; 1802 filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1803 eaddrs = (u16 *)dev->dev_addr; 1803 eaddrs = (__be16 *)dev->dev_addr;
1804 for (i = 2; i < 16; i++) { 1804 for (i = 2; i < 16; i++) {
1805 writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 4; 1805 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1806 writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4; 1806 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1807 writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 8; 1807 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1808 } 1808 }
1809 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++) 1809 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
1810 writew(mc_filter[i], filter_addr); 1810 writew(mc_filter[i], filter_addr);