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authorDivy Le Ray <divy@chelsio.com>2007-09-05 18:58:25 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-10 19:51:05 -0400
commit1c17ae8af93bed203d9760702882e9f747a51912 (patch)
tree622a2d32f794e0e97beda261bc05301fa3c0d8ae /drivers/net
parentb4687ff753c2c5c330989efed7cdf1a6bc6b512e (diff)
cxgb3 - Set the CQ_ERR bit in CQ contexts.
The cxgb3 driver is incorrectly configuring the HW CQ context for CQ's that use overflow-avoidance. Namely the RDMA control CQ. This results in a bad DMA from the device to bus address 0. The solution is to set the CQ_ERR bit in the context for these types of CQs. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/cxgb3/sge_defs.h4
-rw-r--r--drivers/net/cxgb3/t3_hw.c3
2 files changed, 6 insertions, 1 deletions
diff --git a/drivers/net/cxgb3/sge_defs.h b/drivers/net/cxgb3/sge_defs.h
index 514869e26a76..29b6c800b238 100644
--- a/drivers/net/cxgb3/sge_defs.h
+++ b/drivers/net/cxgb3/sge_defs.h
@@ -106,6 +106,10 @@
106#define V_CQ_GEN(x) ((x) << S_CQ_GEN) 106#define V_CQ_GEN(x) ((x) << S_CQ_GEN)
107#define F_CQ_GEN V_CQ_GEN(1U) 107#define F_CQ_GEN V_CQ_GEN(1U)
108 108
109#define S_CQ_ERR 30
110#define V_CQ_ERR(x) ((x) << S_CQ_ERR)
111#define F_CQ_ERR V_CQ_ERR(1U)
112
109#define S_CQ_OVERFLOW_MODE 31 113#define S_CQ_OVERFLOW_MODE 31
110#define V_CQ_OVERFLOW_MODE(x) ((x) << S_CQ_OVERFLOW_MODE) 114#define V_CQ_OVERFLOW_MODE(x) ((x) << S_CQ_OVERFLOW_MODE)
111#define F_CQ_OVERFLOW_MODE V_CQ_OVERFLOW_MODE(1U) 115#define F_CQ_OVERFLOW_MODE V_CQ_OVERFLOW_MODE(1U)
diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c
index cdcfc132e37d..bff1d028a96b 100644
--- a/drivers/net/cxgb3/t3_hw.c
+++ b/drivers/net/cxgb3/t3_hw.c
@@ -2046,7 +2046,8 @@ int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
2046 base_addr >>= 32; 2046 base_addr >>= 32;
2047 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, 2047 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
2048 V_CQ_BASE_HI((u32) base_addr) | V_CQ_RSPQ(rspq) | 2048 V_CQ_BASE_HI((u32) base_addr) | V_CQ_RSPQ(rspq) |
2049 V_CQ_GEN(1) | V_CQ_OVERFLOW_MODE(ovfl_mode)); 2049 V_CQ_GEN(1) | V_CQ_OVERFLOW_MODE(ovfl_mode) |
2050 V_CQ_ERR(ovfl_mode));
2050 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) | 2051 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) |
2051 V_CQ_CREDIT_THRES(credit_thres)); 2052 V_CQ_CREDIT_THRES(credit_thres));
2052 return t3_sge_write_context(adapter, id, F_CQ); 2053 return t3_sge_write_context(adapter, id, F_CQ);